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/qemu/tests/tcg/xtensa/
H A Dfpu.h49 .macro test_op1_rm op, fr0, fr1, v0, r, sr
52 movfp \fr0, \v0
57 .macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r, sr
60 movfp \fr0, \v0
69 movfp \fr0, \v0
76 .macro test_op1_ex op, fr0, fr1, v0, rm, r, sr
79 test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
82 test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
104 test_op1_ex \op, \fr0, \fr1, \v0, 0, \r0, \sr0
105 test_op1_ex \op, \fr0, \fr1, \v0, 1, \r1, \sr1
[all …]
H A Dtest_fp1.S13 .macro test_ord_ex op, br, fr0, fr1, v0, v1, r, sr
16 movfp \fr0, \v0
32 .macro test_ord op, br, fr0, fr1, v0, v1, r, sr
35 test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
38 test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
90 .macro test_cond op, fr0, fr1, cr, v0, v1, r
91 movfp \fr0, \v0
/qemu/tests/qemu-iotests/
H A D085.out43 'snapshot-file': 'TEST_DIR/2-snapshot-v0.IMGFMT' } },
55 'snapshot-file': 'TEST_DIR/3-snapshot-v0.IMGFMT' } },
67 'snapshot-file': 'TEST_DIR/4-snapshot-v0.IMGFMT' } },
79 'snapshot-file': 'TEST_DIR/5-snapshot-v0.IMGFMT' } },
91 'snapshot-file': 'TEST_DIR/6-snapshot-v0.IMGFMT' } },
103 'snapshot-file': 'TEST_DIR/7-snapshot-v0.IMGFMT' } },
115 'snapshot-file': 'TEST_DIR/8-snapshot-v0.IMGFMT' } },
150 Formatting 'TEST_DIR/11-snapshot-v0.IMGFMT', fmt=IMGFMT size=134217728 backing_file=TEST_DIR/10-sna…
161 Formatting 'TEST_DIR/12-snapshot-v0.IMGFMT', fmt=IMGFMT size=134217728 backing_file=TEST_DIR/11-sna…
222 Formatting 'TEST_DIR/14-snapshot-v0.IMGFMT', fmt=IMGFMT size=134217728 backing_file=TEST_DIR/13-sna…
[all …]
/qemu/target/riscv/
H A Dvector_internals.h101 static inline int vext_elem_mask(void *v0, int index) in vext_elem_mask() argument
105 return (((uint64_t *)v0)[idx] >> pos) & 1; in vext_elem_mask()
150 void HELPER(NAME)(void *vd, void *v0, void *vs2, \
164 if (!vm && !vext_elem_mask(v0, i)) { \
189 void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
195 void HELPER(NAME)(void *vd, void *v0, void *vs1, \
199 do_vext_vv(vd, v0, vs1, vs2, env, desc, \
216 void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
222 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
226 do_vext_vx(vd, v0, s1, vs2, env, desc, \
H A Dvector_internals.c36 void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, in do_vext_vv() argument
50 if (!vm && !vext_elem_mask(v0, i)) { in do_vext_vv()
62 void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, in do_vext_vx() argument
76 if (!vm && !vext_elem_mask(v0, i)) { in do_vext_vx()
H A Dvector_helper.c144 uint64_t old = ((uint64_t *)v0)[idx]; in vext_set_elem_mask()
491 if (!vm && !vext_elem_mask(v0, i)) {
1983 vext_vv_rm_1(vd, v0, vs1, vs2, in vext_vv_rm_2()
1987 vext_vv_rm_1(vd, v0, vs1, vs2, in vext_vv_rm_2()
1991 vext_vv_rm_1(vd, v0, vs1, vs2, in vext_vv_rm_2()
1995 vext_vv_rm_1(vd, v0, vs1, vs2, in vext_vv_rm_2()
2110 vext_vx_rm_1(vd, v0, s1, vs2, in vext_vx_rm_2()
2114 vext_vx_rm_1(vd, v0, s1, vs2, in vext_vx_rm_2()
2118 vext_vx_rm_1(vd, v0, s1, vs2, in vext_vx_rm_2()
2122 vext_vx_rm_1(vd, v0, s1, vs2, in vext_vx_rm_2()
[all …]
/qemu/docs/devel/
H A Dtcg-ops.rst722 * - mov_vec *v0*, *v1*
724 ld_vec *v0*, *t1*
726 st_vec *v0*, *t1*
730 * - dup_vec *v0*, *r1*
734 * - dupi_vec *v0*, *c*
744 * - add_vec *v0*, *v1*, *v2*
748 * - sub_vec *v0*, *v1*, *v2*
756 * - neg_vec *v0*, *v1*
760 * - abs_vec *v0*, *v1*
791 or_vec *v0*, *v1*, *v2*
[all …]
/qemu/tests/tcg/hexagon/
H A Dhvx_histogram_row.S34 v0 = #0 define
100 { v0.h = vshuff(v0.h)
105 v0.w = vdmpy(v0.h, r10.h):sat
195 { vshuff(v1, v0, r28)
202 v0.w = vadd(v1.w, v0.w)
239 vshuff(v2, v0, r7)
243 v0.w = vadd(v0.w, v2.w)
247 v0.w = vadd(v0.w, v1.w)
248 vmem(r4++#1) = v0.new
H A Dpreg_alias.c25 static uint32_t preg_alias(uint8_t v0, uint8_t v1, uint8_t v2, uint8_t v3) in preg_alias() argument
34 : "r"(v0), "r"(v1), "r"(v2), "r"(v3) in preg_alias()
39 static uint32_t preg_alias_pair(uint8_t v0, uint8_t v1, uint8_t v2, uint8_t v3) in preg_alias_pair() argument
48 : "r"(v0), "r"(v1), "r"(v2), "r"(v3) in preg_alias_pair()
/qemu/tests/tcg/s390x/
H A Dprecise-smc-softmmu.S20 vl %v0,patch1
25 vstl %v0,%r0,0b /* start writing before TB */
30 vl %v0,patch2
35 vstl %v0,%r0,0b /* start writing before TB */
H A Dunaligned-lowcore.S8 vst %v0,_unaligned
/qemu/common-user/host/mips/
H A Dsafe-syscall.inc.S64 move v0, a1 /* syscall number */
91 move v0, a1 /* syscall number */
130 li v0, QEMU_ERESTARTSYS
144 move a0, v0
/qemu/tcg/i386/
H A Dtcg-target.c.inc3798 tcg_gen_and_vec(MO_8, v0, v0, tcg_constant_vec(type, MO_8, mask));
3836 tcgv_vec_arg(v0), tcgv_vec_arg(v0),
3846 tcg_gen_or_vec(MO_64, v0, v0, t1);
3870 tcg_gen_or_vec(vece, v0, v0, t);
3891 tcg_gen_shrv_vec(vece, v0, v1, sh);
3894 tcg_gen_shlv_vec(vece, v0, v1, sh);
3896 tcg_gen_or_vec(vece, v0, v0, t);
3921 tcg_gen_or_vec(vece, v0, v0, t);
4102 tcg_gen_not_vec(vece, v0, v0);
4128 TCGv_vec v0, v1, v2, v3, v4;
[all …]
/qemu/include/libdecnumber/
H A DdecNumberLocal.h117 uInt u0, u1, v0, v1, w0, w1, w2, t; \
119 v0=v & 0xffff; v1=v>>16; \
120 w0=u0*v0; \
121 t=u1*v0 + (w0>>16); \
/qemu/tests/tcg/loongarch64/system/
H A Dregdef.h12 #define v0 $r4 /* return value - caller saved */ macro
/qemu/target/mips/tcg/
H A Dnanomips_translate.c.inc1674 gen_helper_dpa_w_ph(t0, v1, v0, tcg_env);
1678 gen_helper_dpaq_s_w_ph(t0, v1, v0, tcg_env);
1682 gen_helper_dps_w_ph(t0, v1, v0, tcg_env);
1686 gen_helper_dpsq_s_w_ph(t0, v1, v0, tcg_env);
1697 gen_helper_dpax_w_ph(t0, v0, v1, tcg_env);
1705 gen_helper_dpsx_w_ph(t0, v0, v1, tcg_env);
1720 gen_helper_dpau_h_qbl(t0, v0, v1, tcg_env);
1728 gen_helper_dpsu_h_qbl(t0, v0, v1, tcg_env);
1736 gen_helper_mulsa_w_ph(t0, v0, v1, tcg_env);
1747 gen_helper_dpau_h_qbr(t0, v1, v0, tcg_env);
[all …]
/qemu/tcg/s390x/
H A Dtcg-target.c.inc328 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
3078 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
3087 if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) {
3088 tcg_gen_not_vec(vece, v0, v0);
3100 tcg_gen_bitsel_vec(vece, v0, t, v4, v3);
3102 tcg_gen_bitsel_vec(vece, v0, t, v3, v4);
3148 TCGv_vec v0, v1, v2, v3, v4, t0;
3151 v0 = temp_tcgv_vec(arg_temp(a0));
3169 tcg_gen_rotlv_vec(vece, v0, v1, t0);
3174 expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec);
[all …]
/qemu/docs/system/riscv/
H A Dshakti-c.rst69 $ git clone https://github.com/riscv/opensbi.git -b v0.9
/qemu/tcg/ppc/
H A Dtcg-target.c.inc120 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
3921 vec_gen_3(opci, type, vece, tcgv_vec_arg(v0),
3967 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
3971 tcg_gen_not_vec(vece, v0, v0);
3994 tcgv_vec_arg(v0), tcgv_vec_arg(t1));
4014 tcg_gen_add_vec(MO_32, v0, t1, t2);
4028 TCGv_vec v0, v1, v2, t0;
4032 v0 = temp_tcgv_vec(arg_temp(a0));
4038 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec);
4055 expand_vec_mul(type, vece, v0, v1, v2);
[all …]
/qemu/tcg/arm/
H A Dtcg-target.c.inc2840 TCGv_vec v0, v1, v2, t1, t2, c1;
2844 v0 = temp_tcgv_vec(arg_temp(a0));
2857 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
2872 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
2881 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
2893 vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
2895 tcg_gen_or_vec(vece, v0, v0, t1);
2911 tcg_gen_or_vec(vece, v0, t1, t2);
/qemu/tests/fp/
H A Dwrap.c.inc90 to->v0 = a.low;
100 ret.low = from->v0;
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc29 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
2865 TCGv_vec v0, v1, v2, t1, t2, c1;
2869 v0 = temp_tcgv_vec(arg_temp(a0));
2879 tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
2891 vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
2904 vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(v0),
2906 tcg_gen_or_vec(vece, v0, v0, t1);
2922 tcg_gen_or_vec(vece, v0, t1, t2);
/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc253 * instruction cannot overlap the source mask register (v0).
303 * instruction cannot overlap the source mask register (v0).
358 * instruction cannot overlap the source mask register (v0).
391 * instruction cannot overlap the source mask register (v0),
419 * instruction cannot overlap the source mask register (v0).
446 * instruction cannot overlap the source mask register (v0).
562 * instruction cannot overlap the source mask register (v0).
1639 * destination vector register is v0 and LMUL > 1. (Section 11.4)
3069 * 2. If masked, cannot overlap the mask register ('v0').
/qemu/tcg/mips/
H A Dtcg-target.c.inc43 "v0",