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/qemu/target/hexagon/imported/mmvec/
H A Dencode_ext.def540 DEF_ENC(V6_vgtb_and, ICLASS_CJ" 1 100 100 vvvvv PP 1 uuuuu 000 100xx") //
541 DEF_ENC(V6_vgth_and, ICLASS_CJ" 1 100 100 vvvvv PP 1 uuuuu 000 101xx") //
542 DEF_ENC(V6_vgtw_and, ICLASS_CJ" 1 100 100 vvvvv PP 1 uuuuu 000 110xx") //
548 DEF_ENC(V6_veqb_or, ICLASS_CJ" 1 100 100 vvvvv PP 1 uuuuu 010 000xx") //
549 DEF_ENC(V6_veqh_or, ICLASS_CJ" 1 100 100 vvvvv PP 1 uuuuu 010 001xx") //
550 DEF_ENC(V6_veqw_or, ICLASS_CJ" 1 100 100 vvvvv PP 1 uuuuu 010 010xx") //
556 DEF_ENC(V6_vgtub_or, ICLASS_CJ" 1 100 100 vvvvv PP 1 uuuuu 011 000xx") //
557 DEF_ENC(V6_vgtuh_or, ICLASS_CJ" 1 100 100 vvvvv PP 1 uuuuu 011 001xx") //
558 DEF_ENC(V6_vgtuw_or, ICLASS_CJ" 1 100 100 vvvvv PP 1 uuuuu 011 010xx") //
564 DEF_ENC(V6_vgtb_xor, ICLASS_CJ" 1 100 100 vvvvv PP 1 uuuuu 100 100xx") //
[all …]
/qemu/
H A D.mailmap11 # Proper Name <commit@email.xx>
12 # <proper@email.xx> <commit@email.xx>
13 # Proper Name <proper@email.xx> <commit@email.xx>
14 # Proper Name <proper@email.xx> Commit Name <commit@email.xx>
/qemu/docs/system/
H A Dcpu-models-x86.rst.inc92 Intel Xeon E3-12xx v2 (Ivy Bridge, 2012)
101 Intel Core i7 9xx (Nehalem Class Core i7, 2008)
241 AMD Opteron 63xx class CPU (2012)
244 AMD Opteron 62xx class CPU (2011)
247 AMD Opteron 23xx (Gen 3 Class Opteron, 2009)
250 AMD Opteron 22xx (Gen 2 Class Opteron, 2006)
/qemu/target/hexagon/idef-parser/
H A Didef-parser.lex51 REG_ID_64 ee|ss|dd|tt|uu|vv|xx|yy
/qemu/hw/ppc/
H A Dmeson.build58 # PowerPC 4xx boards
/qemu/tests/data/qobject/
H A Dqdict.txt72 4xx: 4096
73 4xx.c: 16297
74 4xx.h: 1174
84 52xx: 4096
110 6xx-suspend.S: 1086
156 82xx: 4096
160 83xx: 4096
162 85xx: 4096
163 86xx: 4096
167 8xx: 4096
[all …]
/qemu/docs/system/s390x/
H A Dvfio-ap.rst170 ...... xx.yyyy
178 is AP adapter number xx (in hex)
180 ``xx.yyyy``
181 is an APQN with xx specifying the APID and yyyy specifying the APQI
842 The output will display the APQNs in the format ``xx.yyyy``, where xx is
/qemu/target/hexagon/imported/
H A Dencode_pp.def464 /* 0 1xx Available */
486 /* xx - st_misc */
597 DEF_FIELDROW_DESC32(ICLASS_CJ" 00-- -------- -------- --------","[#0-3] pd=cmp.xx(R,#u5) ; if ([!]…
661 DEF_FIELDROW_DESC32(ICLASS_NCJ" 00-- -------- -------- --------","[#0-3] if (cmp.xx(R.new,R)) jump:…
662 DEF_FIELDROW_DESC32(ICLASS_NCJ" 01-- -------- -------- --------","[#4-7] if (cmp.xx(R.new,#U5)) jum…
1767 SH_RRR_ENC(A4_addp_c, "0010","110","-","-xx","ddddd")
1768 SH_RRR_ENC(A4_subp_c, "0010","111","-","-xx","ddddd")
/qemu/target/arm/tcg/
H A Dsve_helper.c4996 intptr_t xx = x; local
4999 xx += 8;
5001 d[i] = float16_muladd(n[i], mm, coeff[xx], 0, vs);
5018 intptr_t xx = x; in HELPER() local
5021 xx += 8; in HELPER()
5023 d[i] = float32_muladd(n[i], mm, coeff[xx], 0, vs); in HELPER()
5044 intptr_t xx = x; in HELPER() local
5047 xx += 8; in HELPER()
5049 d[i] = float64_muladd(n[i], mm, coeff[xx], 0, vs); in HELPER()
/qemu/target/mips/
H A Dcpu-defs.c.inc990 * Octeon 68xx with MIPS64 Cavium Octeon features.