1 /* 2 * Copyright 2007-2008, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Ithamar Adema, ithamar AT unet DOT nl 7 * Axel Dörfler, axeld@pinc-software.de 8 */ 9 #ifndef HDA_CODEC_H 10 #define HDA_CODEC_H 11 12 enum hda_widget_type { 13 WT_AUDIO_OUTPUT = 0, 14 WT_AUDIO_INPUT = 1, 15 WT_AUDIO_MIXER = 2, 16 WT_AUDIO_SELECTOR = 3, 17 WT_PIN_COMPLEX = 4, 18 WT_POWER = 5, 19 WT_VOLUME_KNOB = 6, 20 WT_BEEP_GENERATOR = 7, 21 WT_VENDOR_DEFINED = 15 22 }; 23 24 enum pin_connectivity_type { 25 PIN_CONN_JACK, 26 PIN_CONN_NONE, 27 PIN_CONN_FIXED, 28 PIN_CONN_BOTH 29 }; 30 31 enum pin_dev_type { 32 PIN_DEV_LINE_OUT = 0, 33 PIN_DEV_SPEAKER, 34 PIN_DEV_HEAD_PHONE_OUT, 35 PIN_DEV_CD, 36 PIN_DEV_SPDIF_OUT, 37 PIN_DEV_DIGITAL_OTHER_OUT, 38 PIN_DEV_MODEM_LINE_SIDE, 39 PIN_DEV_MODEM_HAND_SIDE, 40 PIN_DEV_LINE_IN, 41 PIN_DEV_AUX, 42 PIN_DEV_MIC_IN, 43 PIN_DEV_TELEPHONY, 44 PIN_DEV_SPDIF_IN, 45 PIN_DEV_DIGITAL_OTHER_IN, 46 PIN_DEV_RESERVED, 47 PIN_DEV_OTHER 48 }; 49 50 51 /* Verb Helper Macro */ 52 #define MAKE_VERB(cad, nid, vid, payload) \ 53 (((cad) << 28) | ((nid) << 20) | (vid) | (payload)) 54 55 /* Verb IDs */ 56 #define VID_GET_PARAMETER 0xf0000 57 #define VID_GET_CONNECTION_SELECT 0xf0100 58 #define VID_SET_CONNECTION_SELECT 0x70100 59 #define VID_GET_CONNECTION_LIST_ENTRY 0xf0200 60 #define VID_GET_PROCESSING_STATE 0xf0300 61 #define VID_SET_PROCESSING_STATE 0x70300 62 #define VID_GET_COEFFICIENT_INDEX 0xd0000 63 #define VID_SET_COEFFICIENT_INDEX 0x50000 64 #define VID_GET_PROCESSING_COEFFICIENT 0xc0000 65 #define VID_SET_PROCESSING_COEFFICIENT 0x40000 66 #define VID_GET_AMPLIFIER_GAIN_MUTE 0xb0000 67 #define VID_SET_AMPLIFIER_GAIN_MUTE 0x30000 68 #define VID_GET_CONVERTER_FORMAT 0xa0000 69 #define VID_SET_CONVERTER_FORMAT 0x20000 70 #define VID_GET_CONVERTER_STREAM_CHANNEL 0xf0600 71 #define VID_SET_CONVERTER_STREAM_CHANNEL 0x70600 72 #define VID_GET_DIGITAL_CONVERTER_CONTROL 0xf0d00 73 #define VID_SET_DIGITAL_CONVERTER_CONTROL1 0x70d00 74 #define VID_SET_DIGITAL_CONVERTER_CONTROL2 0x70e00 75 #define VID_GET_POWER_STATE 0xf0500 76 #define VID_SET_POWER_STATE 0x70500 77 #define VID_GET_SDI_SELECT 0xf0400 78 #define VID_SET_SDI_SELECT 0x70400 79 #define VID_GET_PIN_WIDGET_CONTROL 0xf0700 80 #define VID_SET_PIN_WIDGET_CONTROL 0x70700 81 #define VID_GET_UNSOLRESP 0xF0800 82 #define VID_SET_UNSOLRESP 0x70800 83 #define VID_GET_PINSENSE 0xF0900 84 #define VID_SET_PINSENSE 0x70900 85 #define VID_GET_EAPDBTL_EN 0xF0C00 86 #define VID_SET_EAPDBTL_EN 0x70C00 87 #define VID_GET_VOLUME_KNOB_CONTROL 0xF0F00 88 #define VID_SET_VOLUME_KNOB_CONTROL 0x70F00 89 #define VID_GET_GPIDATA 0xF1000 90 #define VID_SET_GPIDATA 0x71000 91 #define VID_GET_GPIWAKE_EN 0xF1100 92 #define VID_SET_GPIWAKE_EN 0x71100 93 #define VID_GET_GPIUNSOL 0xF1200 94 #define VID_SET_GPIUNSOL 0x71200 95 #define VID_GET_GPISTICKY 0xF1300 96 #define VID_SET_GPISTICKY 0x71300 97 #define VID_GET_GPO_DATA 0xF1400 98 #define VID_SET_GPO_DATA 0x71400 99 #define VID_GET_GPIO_DATA 0xF1500 100 #define VID_SET_GPIO_DATA 0x71500 101 #define VID_GET_GPIO_EN 0xF1600 102 #define VID_SET_GPIO_EN 0x71600 103 #define VID_GET_GPIO_DIR 0xF1700 104 #define VID_SET_GPIO_DIR 0x71700 105 #define VID_GET_GPIOWAKE_EN 0xF1800 106 #define VID_SET_GPIOWAKE_EN 0x71800 107 #define VID_GET_GPIOUNSOL_EN 0xF1900 108 #define VID_SET_GPIOUNSOL_EN 0x71900 109 #define VID_GET_GPIOSTICKY 0xF1A00 110 #define VID_SET_GPIOSTICKY 0x71A00 111 #define VID_GET_BEEPGEN 0xF0A00 112 #define VID_SET_BEEPGEN 0x70A00 113 #define VID_GET_VOLUME_KNOB 0xf0f00 114 #define VID_SET_VOLUME_KNOB 0x70f00 115 #define VID_GET_SUBSYSTEMID 0xF2000 116 #define VID_SET_SUBSYSTEMID1 0x72000 117 #define VID_SET_SUBSYSTEMID2 0x72100 118 #define VID_SET_SUBSYSTEMID3 0x72200 119 #define VID_SET_SUBSYSTEMID4 0x72300 120 #define VID_GET_CONFIGURATION_DEFAULT 0xf1c00 121 #define VID_SET_CONFIGURATION_DEFAULT1 0x71c00 122 #define VID_SET_CONFIGURATION_DEFAULT2 0x71d00 123 #define VID_SET_CONFIGURATION_DEFAULT3 0x71e00 124 #define VID_SET_CONFIGURATION_DEFAULT4 0x71f00 125 #define VID_GET_STRIPE_CONTROL 0xf2400 126 #define VID_SET_STRIPE_CONTROL 0x72000 127 #define VID_FUNCTION_RESET 0x7ff00 128 /* later specification updates */ 129 #define VID_GET_EDID_LIKE_DATA 0xf2f00 130 #define VID_GET_CONVERTER_CHANNEL_COUNT 0xf2d00 131 #define VID_SET_CONVERTER_CHANNEL_COUNT 0x72d00 132 #define VID_GET_DATA_ISLAND_PACKET_SIZE 0xf2e00 133 #define VID_GET_DATA_ISLAND_PACKET_INDEX 0xf3000 134 #define VID_SET_DATA_ISLAND_PACKET_INDEX 0x73000 135 #define VID_GET_DATA_ISLAND_PACKET_DATA 0xf3100 136 #define VID_SET_DATA_ISLAND_PACKET_DATA 0x73100 137 #define VID_GET_DATA_ISLAND_PACKET_XMITCTRL 0xf3200 138 #define VID_SET_DATA_ISLAND_PACKET_XMITCTRL 0x73200 139 #define VID_GET_CONTENT_PROTECTION_CONTROL 0xf3300 140 #define VID_SET_CONTENT_PROTECTION_CONTROL 0x73300 141 #define VID_GET_ASP_CHANNEL_MAPPING 0xf3400 142 #define VID_SET_ASP_CHANNEL_MAPPING 0x73400 143 144 /* Parameter IDs */ 145 #define PID_VENDOR_ID 0x00 146 #define PID_REVISION_ID 0x02 147 #define PID_SUB_NODE_COUNT 0x04 148 #define PID_FUNCTION_GROUP_TYPE 0x05 149 #define PID_AUDIO_GROUP_CAP 0x08 150 #define PID_AUDIO_WIDGET_CAP 0x09 151 #define PID_PCM_SUPPORT 0x0a 152 #define PID_STREAM_SUPPORT 0x0b 153 #define PID_PIN_CAP 0x0c 154 #define PID_INPUT_AMPLIFIER_CAP 0x0d 155 #define PID_CONNECTION_LIST_LENGTH 0x0e 156 #define PID_POWERSTATE_SUPPORT 0x0f 157 #define PID_PROCESSING_CAP 0x10 158 #define PID_GPIO_COUNT 0x11 159 #define PID_OUTPUT_AMPLIFIER_CAP 0x12 160 #define PID_VOLUME_KNOB_CAP 0x13 161 162 /* Subordinate node count */ 163 #define SUB_NODE_COUNT_TOTAL_MASK 0x000000ff 164 #define SUB_NODE_COUNT_TOTAL_SHIFT 0 165 #define SUB_NODE_COUNT_START_MASK 0x00ff0000 166 #define SUB_NODE_COUNT_START_SHIFT 16 167 168 #define SUB_NODE_COUNT_TOTAL(c) ((c & SUB_NODE_COUNT_TOTAL_MASK) \ 169 >> SUB_NODE_COUNT_TOTAL_SHIFT) 170 #define SUB_NODE_COUNT_START(c) ((c & SUB_NODE_COUNT_START_MASK) \ 171 >> SUB_NODE_COUNT_START_SHIFT) 172 173 /* Function group type */ 174 #define FUNCTION_GROUP_NODETYPE_MASK 0x000000ff 175 #define FUNCTION_GROUP_UNSOLCAPABLE_MASK 0x00000100 176 177 #define FUNCTION_GROUP_NODETYPE_AUDIO 0x00000001 178 #define FUNCTION_GROUP_NODETYPE_MODEM 0x00000002 179 180 /* Audio Function group capabilities */ 181 #define AUDIO_GROUP_CAP_OUTPUT_DELAY_MASK 0x0000000f 182 #define AUDIO_GROUP_CAP_OUTPUT_DELAY_SHIFT 0 183 #define AUDIO_GROUP_CAP_INPUT_DELAY_MASK 0x00000f00 184 #define AUDIO_GROUP_CAP_INPUT_DELAY_SHIFT 8 185 #define AUDIO_GROUP_CAP_BEEPGEN_MASK 0x00010000 186 #define AUDIO_GROUP_CAP_BEEPGEN_SHIFT 16 187 188 #define AUDIO_GROUP_CAP_OUTPUT_DELAY(c) ((c & AUDIO_GROUP_CAP_OUTPUT_DELAY_MASK) \ 189 >> AUDIO_GROUP_CAP_OUTPUT_DELAY_SHIFT) 190 #define AUDIO_GROUP_CAP_INPUT_DELAY(c) ((c & AUDIO_GROUP_CAP_INPUT_DELAY_MASK) \ 191 >> AUDIO_GROUP_CAP_INPUT_DELAY_SHIFT) 192 #define AUDIO_GROUP_CAP_BEEPGEN(c) ((c & AUDIO_GROUP_CAP_BEEPGEN_MASK) \ 193 >> AUDIO_GROUP_CAP_BEEPGEN_SHIFT) 194 195 196 /* Audio widget capabilities */ 197 #define AUDIO_CAP_CHANNEL_COUNT_MASK 0x0000e000 198 #define AUDIO_CAP_CHANNEL_COUNT_SHIFT 13 199 #define AUDIO_CAP_DELAY_MASK 0x000f0000 200 #define AUDIO_CAP_DELAY_SHIFT 16 201 #define AUDIO_CAP_TYPE_MASK 0x00f00000 202 #define AUDIO_CAP_TYPE_SHIFT 20 203 204 #define AUDIO_CAP_STEREO (1L << 0) 205 #define AUDIO_CAP_INPUT_AMPLIFIER (1L << 1) 206 #define AUDIO_CAP_OUTPUT_AMPLIFIER (1L << 2) 207 #define AUDIO_CAP_AMPLIFIER_OVERRIDE (1L << 3) 208 #define AUDIO_CAP_FORMAT_OVERRIDE (1L << 4) 209 #define AUDIO_CAP_STRIPE (1L << 5) 210 #define AUDIO_CAP_PROCESSING_CONTROLS (1L << 6) 211 #define AUDIO_CAP_UNSOLICITED_RESPONSES (1L << 7) 212 #define AUDIO_CAP_CONNECTION_LIST (1L << 8) 213 #define AUDIO_CAP_DIGITAL (1L << 9) 214 #define AUDIO_CAP_POWER_CONTROL (1L << 10) 215 #define AUDIO_CAP_LEFT_RIGHT_SWAP (1L << 11) 216 #define AUDIO_CAP_CP_CAPS (1L << 12) 217 218 #define AUDIO_CAP_CHANNEL_COUNT(c) \ 219 (((c & AUDIO_CAP_CHANNEL_COUNT_MASK) >> (AUDIO_CAP_CHANNEL_COUNT_SHIFT - 1)) \ 220 | AUDIO_CAP_STEREO) 221 222 /* Amplifier capabilities */ 223 #define AMP_CAP_MUTE 0xf0000000 224 #define AMP_CAP_STEP_SIZE_MASK 0x007f0000 225 #define AMP_CAP_STEP_SIZE_SHIFT 16 226 #define AMP_CAP_NUM_STEPS_MASK 0x00007f00 227 #define AMP_CAP_NUM_STEPS_SHIFT 8 228 #define AMP_CAP_OFFSET_MASK 0x0000007f 229 230 #define AMP_CAP_STEP_SIZE(c) ((((c & AMP_CAP_STEP_SIZE_MASK) \ 231 >> AMP_CAP_STEP_SIZE_SHIFT) + 1) / 4.0) 232 #define AMP_CAP_NUM_STEPS(c) ((c & AMP_CAP_NUM_STEPS_MASK) \ 233 >> AMP_CAP_NUM_STEPS_SHIFT) 234 #define AMP_CAP_OFFSET(c) (c & AMP_CAP_OFFSET_MASK) 235 236 /* Pin capabilities */ 237 #define PIN_CAP_IMP_SENSE (1L << 0) 238 #define PIN_CAP_TRIGGER_REQ (1L << 1) 239 #define PIN_CAP_PRES_DETECT (1L << 2) 240 #define PIN_CAP_HP_DRIVE (1L << 3) 241 #define PIN_CAP_OUTPUT (1L << 4) 242 #define PIN_CAP_INPUT (1L << 5) 243 #define PIN_CAP_BALANCE (1L << 6) 244 #define PIN_CAP_HDMI (1L << 7) 245 #define PIN_CAP_VREF_CTRL_HIZ (1L << 8) 246 #define PIN_CAP_VREF_CTRL_50 (1L << 9) 247 #define PIN_CAP_VREF_CTRL_GROUND (1L << 10) 248 #define PIN_CAP_VREF_CTRL_80 (1L << 12) 249 #define PIN_CAP_VREF_CTRL_100 (1L << 13) 250 #define PIN_CAP_EAPD_CAP (1L << 16) 251 #define PIN_CAP_DP (1L << 24) 252 #define PIN_CAP_HBR (1L << 27) 253 254 #define PIN_CAP_IS_PRES_DETECT_CAP(c) ((c & PIN_CAP_PRES_DETECT) != 0) 255 #define PIN_CAP_IS_OUTPUT(c) ((c & PIN_CAP_OUTPUT) != 0) 256 #define PIN_CAP_IS_INPUT(c) ((c & PIN_CAP_INPUT) != 0) 257 #define PIN_CAP_IS_BALANCE(c) ((c & PIN_CAP_BALANCE) != 0) 258 #define PIN_CAP_IS_HDMI(c) ((c & PIN_CAP_HDMI) != 0) 259 #define PIN_CAP_IS_VREF_CTRL_50_CAP(c) ((c & PIN_CAP_VREF_CTRL_50) != 0) 260 #define PIN_CAP_IS_VREF_CTRL_80_CAP(c) ((c & PIN_CAP_VREF_CTRL_80) != 0) 261 #define PIN_CAP_IS_VREF_CTRL_100_CAP(c) ((c & PIN_CAP_VREF_CTRL_100) != 0) 262 #define PIN_CAP_IS_EAPD_CAP(c) ((c & PIN_CAP_EAPD_CAP) != 0) 263 #define PIN_CAP_IS_DP(c) ((c & PIN_CAP_DP) != 0) 264 #define PIN_CAP_IS_HBR(c) ((c & PIN_CAP_HBR) != 0) 265 266 /* PCM support */ 267 #define PCM_8_BIT (1L << 16) 268 #define PCM_16_BIT (1L << 17) 269 #define PCM_20_BIT (1L << 18) 270 #define PCM_24_BIT (1L << 19) 271 #define PCM_32_BIT (1L << 20) 272 273 /* stream support */ 274 #define STREAM_AC3 0x00000004 275 #define STREAM_FLOAT 0x00000002 276 #define STREAM_PCM 0x00000001 277 278 /* Amplifier Gain/Mute */ 279 #define AMP_GET_OUTPUT (1L << 15) 280 #define AMP_GET_INPUT (0L << 15) 281 #define AMP_GET_LEFT_CHANNEL (1L << 13) 282 #define AMP_GET_RIGHT_CHANNEL (0L << 13) 283 #define AMP_GET_INPUT_INDEX_MASK 0x0000000f 284 #define AMP_GET_INPUT_INDEX_SHIFT 0 285 286 #define AMP_GET_INPUT_INDEX(x) ((x << AMP_GET_INPUT_INDEX_SHIFT) & AMP_GET_INPUT_INDEX_MASK) 287 288 #define AMP_SET_OUTPUT (1L << 15) 289 #define AMP_SET_INPUT (1L << 14) 290 #define AMP_SET_LEFT_CHANNEL (1L << 13) 291 #define AMP_SET_RIGHT_CHANNEL (1L << 12) 292 #define AMP_SET_INPUT_INDEX_MASK 0x00000f00 293 #define AMP_SET_INPUT_INDEX_SHIFT 8 294 295 #define AMP_SET_INPUT_INDEX(x) ((x << AMP_SET_INPUT_INDEX_SHIFT) & AMP_SET_INPUT_INDEX_MASK) 296 297 #define AMP_GAIN_MASK 0x0000007f 298 #define AMP_MUTE (1L << 7) 299 300 /* Pin Widget Control */ 301 #define PIN_ENABLE_HEAD_PHONE (1L << 7) 302 #define PIN_ENABLE_OUTPUT (1L << 6) 303 #define PIN_ENABLE_INPUT (1L << 5) 304 #define PIN_ENABLE_VREF_HIZ 0 305 #define PIN_ENABLE_VREF_50 1 306 #define PIN_ENABLE_VREF_GROUND 2 307 #define PIN_ENABLE_VREF_80 4 308 #define PIN_ENABLE_VREF_100 5 309 310 /* Unsolicited Response */ 311 #define UNSOLRESP_ENABLE (1L << 7) 312 #define UNSOLRESP_TAG_MASK 0x0000003f 313 #define UNSOLRESP_TAG_SHIFT 0 314 315 /* Pin sense */ 316 #define PIN_SENSE_PRESENCE_DETECT (1L << 31) 317 #define PIN_SENSE_ELD_VALID (1L << 30) 318 #define PIN_SENSE_IMPEDANCE_MASK 0x7fffffff 319 #define PIN_SENSE_IMPEDANCE_SHIFT 0 320 321 #define PIN_SENSE_IMPEDANCE_INVALID 0x7fffffff 322 #define PIN_SENSE_SET_CHANNEL_LEFT 0 323 #define PIN_SENSE_SET_CHANNEL_RIGHT 1 324 325 /* Supported power states */ 326 #define POWER_STATE_D0 (1L << 0) 327 #define POWER_STATE_D1 (1L << 1) 328 #define POWER_STATE_D2 (1L << 2) 329 #define POWER_STATE_D3 (1L << 3) 330 #define POWER_STATE_D3COLD (1L << 4) 331 #define POWER_STATE_S3D3COLD (1L << 29) 332 #define POWER_STATE_CLKSTOP (1L << 30) 333 #define POWER_STATE_EPSS (1L << 31) 334 335 /* Configuration default */ 336 #define CONF_DEFAULT_SEQUENCE_MASK 0x0000000f 337 #define CONF_DEFAULT_SEQUENCE_SHIFT 0 338 #define CONF_DEFAULT_ASSOCIATION_MASK 0x000000f0 339 #define CONF_DEFAULT_ASSOCIATION_SHIFT 4 340 #define CONF_DEFAULT_MISC_MASK 0x00000f00 341 #define CONF_DEFAULT_MISC_SHIFT 8 342 #define CONF_DEFAULT_COLOR_MASK 0x0000f000 343 #define CONF_DEFAULT_COLOR_SHIFT 12 344 #define CONF_DEFAULT_CONNTYPE_MASK 0x000f0000 345 #define CONF_DEFAULT_CONNTYPE_SHIFT 16 346 #define CONF_DEFAULT_DEVICE_MASK 0x00f00000 347 #define CONF_DEFAULT_DEVICE_SHIFT 20 348 #define CONF_DEFAULT_LOCATION_MASK 0x3f000000 349 #define CONF_DEFAULT_LOCATION_SHIFT 24 350 #define CONF_DEFAULT_CONNECTIVITY_MASK 0xc0000000 351 #define CONF_DEFAULT_CONNECTIVITY_SHIFT 30 352 353 #define CONF_DEFAULT_SEQUENCE(c) ((c & CONF_DEFAULT_SEQUENCE_MASK) >> CONF_DEFAULT_SEQUENCE_SHIFT) 354 #define CONF_DEFAULT_ASSOCIATION(c) ((c & CONF_DEFAULT_ASSOCIATION_MASK) >> CONF_DEFAULT_ASSOCIATION_SHIFT) 355 #define CONF_DEFAULT_MISC(c) ((c & CONF_DEFAULT_MISC_MASK) >> CONF_DEFAULT_MISC_SHIFT) 356 #define CONF_DEFAULT_COLOR(c) ((c & CONF_DEFAULT_COLOR_MASK) >> CONF_DEFAULT_COLOR_SHIFT) 357 #define CONF_DEFAULT_CONNTYPE(c) ((c & CONF_DEFAULT_CONNTYPE_MASK) >> CONF_DEFAULT_CONNTYPE_SHIFT) 358 #define CONF_DEFAULT_DEVICE(c) ((c & CONF_DEFAULT_DEVICE_MASK) >> CONF_DEFAULT_DEVICE_SHIFT) 359 #define CONF_DEFAULT_LOCATION(c) ((c & CONF_DEFAULT_LOCATION_MASK) >> CONF_DEFAULT_LOCATION_SHIFT) 360 #define CONF_DEFAULT_CONNECTIVITY(c) ((c & CONF_DEFAULT_CONNECTIVITY_MASK) >> CONF_DEFAULT_CONNECTIVITY_SHIFT) 361 362 /* EAPD/BTL enable */ 363 #define EAPDBTL_ENABLE_BTL 0x1 364 #define EAPDBTL_ENABLE_EAPD 0x2 365 #define EAPDBTL_ENABLE_LRSWAP 0x4 366 367 /* GP I/O count */ 368 #define GPIO_COUNT_NUM_GPIO_MASK 0x000000ff 369 #define GPIO_COUNT_NUM_GPIO_SHIFT 0 370 #define GPIO_COUNT_NUM_GPO_MASK 0x0000ff00 371 #define GPIO_COUNT_NUM_GPO_SHIFT 8 372 #define GPIO_COUNT_NUM_GPI_MASK 0x00ff0000 373 #define GPIO_COUNT_NUM_GPI_SHIFT 16 374 #define GPIO_COUNT_GPIUNSOL_MASK 0x40000000 375 #define GPIO_COUNT_GPIUNSOL_SHIFT 30 376 #define GPIO_COUNT_GPIWAKE_MASK 0x80000000 377 #define GPIO_COUNT_GPIWAKE_SHIFT 31 378 379 #define GPIO_COUNT_NUM_GPIO(c) ((c & GPIO_COUNT_NUM_GPIO_MASK) >> GPIO_COUNT_NUM_GPIO_SHIFT) 380 #define GPIO_COUNT_NUM_GPO(c) ((c & GPIO_COUNT_NUM_GPO_MASK) >> GPIO_COUNT_NUM_GPO_SHIFT) 381 #define GPIO_COUNT_NUM_GPI(c) ((c & GPIO_COUNT_NUM_GPI_MASK) >> GPIO_COUNT_NUM_GPI_SHIFT) 382 #define GPIO_COUNT_GPIUNSOL(c) ((c & GPIO_COUNT_GPIUNSOL_MASK) >> GPIO_COUNT_GPIUNSOL_SHIFT) 383 #define GPIO_COUNT_GPIWAKE(c) ((c & GPIO_COUNT_GPIWAKE_MASK) >> GPIO_COUNT_GPIWAKE_SHIFT) 384 385 386 #endif /* HDA_CODEC_H */ 387