| /qemu/hw/core/ |
| H A D | cpu-sysemu.c | 28 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_paging_enabled() local
30 if (cc->sysemu_ops->get_paging_enabled) { in cpu_paging_enabled()
40 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_get_memory_mapping() local
53 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_get_phys_page_attrs_debug() local
84 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_write_elf32_qemunote() local
95 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_write_elf32_note() local
106 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_write_elf64_qemunote() local
117 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_write_elf64_note() local
127 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_virtio_is_big_endian() local
137 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_get_crash_info() local
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| /qemu/tests/tcg/s390x/ |
| H A D | add-logical-with-carry.c | 42 unsigned long c, int *cc) in test32rm() argument
50 : [a] "+&r" (a32), [cc] "+&r" (*cc) in test32rm()
53 *cc >>= 28; in test32rm()
68 : [a] "+&r" (a32), [c] "+&r" (c32), [cc] "+&r" (*cc) in test32mr()
71 *cc >>= 28; in test32mr()
84 : [a] "+&r" (a), [cc] "+&r" (*cc) in test64rm()
87 *cc >>= 28; in test64rm()
99 : [a] "+&r" (a), [c] "+&r" (c), [cc] "+&r" (*cc) in test64mr()
102 *cc >>= 28; in test64mr()
132 int cc; in main() local
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| H A D | rxsbg.c | 10 rxsbg(unsigned long *r1, unsigned long r2, int i3, int i4, int i5, int *cc) in rxsbg() argument
14 : [r1] "+r" (*r1), [cc] "=r" (*cc) in rxsbg()
17 *cc = (*cc >> 28) & 3; in rxsbg()
23 int cc; in test_cc0() local
25 rxsbg(&r1, 3, 61 | 0x80, 62, 1, &cc); in test_cc0()
27 assert(cc == 0); in test_cc0()
33 int cc; in test_cc1() local
35 rxsbg(&r1, 3, 61 | 0x80, 62, 1, &cc); in test_cc1()
37 assert(cc == 1); in test_cc1()
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| H A D | chrl.c | 7 uint32_t program_mask, cc; in test_chrl() local
21 cc = program_mask >> 28; in test_chrl()
22 assert(!cc); in test_chrl()
36 cc = program_mask >> 28; in test_chrl()
37 assert(!cc); in test_chrl()
42 uint32_t program_mask, cc; in test_cghrl() local
56 cc = program_mask >> 28; in test_cghrl()
57 assert(!cc); in test_cghrl()
71 cc = program_mask >> 28; in test_cghrl()
72 assert(!cc); in test_cghrl()
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| H A D | lcbb.c | 10 lcbb(long *r1, void *dxb2, int m3, int *cc) in lcbb() argument
14 : [r1] "+r" (*r1), [cc] "=r" (*cc) in lcbb()
17 *cc = (*cc >> 28) & 3; in lcbb()
26 int cc; in test_lcbb() local
28 lcbb(&r1, p, m3, &cc); in test_lcbb()
30 assert(cc == exp_cc); in test_lcbb()
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| H A D | clst.c | 9 int cc; in clst() local
17 : [r1] "+r" (r1), [r2] "+r" (r2), "+r" (r0), [cc] "=r" (cc) in clst()
22 } while (cc == 3); in clst()
24 return cc; in clst()
66 int cc; in main() local
72 cc = clst(t->sep, &s1, &s2); in main()
73 if (cc != t->exp_cc || in main()
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| H A D | cdsg.c | 27 int cc; in cdsg() local
38 , [cc] "=r" (cc) in cdsg()
45 return (cc >> 28) & 3; in cdsg()
51 int cc; in cdsg_loop() local
63 cc = cdsg(&orig0, &orig1, new0, new1, &val); in cdsg_loop()
65 if (cc == 0) { in cdsg_loop()
70 assert(cc == 1); in cdsg_loop()
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| H A D | csst.c | 15 uint64_t cc; in main() local
25 [cc] "=r" (cc) in main()
29 cc = (cc >> 28) & 3; in main()
30 if (cc) { in main()
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| H A D | exrl-trtr.c | 10 uint64_t cc; in main() local
27 [cc] "=r" (cc) in main()
32 cc = (cc >> 28) & 3; in main()
33 if (cc != 1) { in main()
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| H A D | exrl-trt.c | 10 uint64_t cc; in main() local
27 [cc] "=r" (cc) in main()
32 cc = (cc >> 28) & 3; in main()
33 if (cc != 2) { in main()
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| H A D | cgebra.c | 14 int cc; in main() local
20 , [cc] "=r" (cc) in main()
25 cc >>= 28; in main()
28 assert(cc == 3); in main()
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| /qemu/backends/ |
| H A D | cryptodev-vhost.c | 61 crypto->cc = options->cc; in cryptodev_vhost_init()
124 if (!cc) { in cryptodev_get_vhost()
128 switch (cc->type) { in cryptodev_get_vhost()
157 cc->vring_enable = enable; in vhost_set_vring_enable()
181 CryptoDevBackendClient *cc; in cryptodev_vhost_start() local
189 cc = b->conf.peers.ccs[i]; in cryptodev_vhost_start()
219 if (cc->vring_enable) { in cryptodev_vhost_start()
221 r = vhost_set_vring_enable(cc, b, i, cc->vring_enable); in cryptodev_vhost_start()
253 CryptoDevBackendClient *cc; in cryptodev_vhost_stop() local
278 CryptoDevBackendClient *cc; in cryptodev_vhost_virtqueue_mask() local
[all …]
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| H A D | cryptodev-vhost-user.c | 107 options.cc = b->conf.peers.ccs[i]; in cryptodev_vhost_user_start()
188 CryptoDevBackendClient *cc; in cryptodev_vhost_user_init() local
201 cc = cryptodev_backend_new_client(); in cryptodev_vhost_user_init()
204 cc->queue_index = i; in cryptodev_vhost_user_init()
207 backend->conf.peers.ccs[i] = cc; in cryptodev_vhost_user_init()
240 CryptoDevBackendClient *cc = in cryptodev_vhost_user_crypto_create_session() local
311 CryptoDevBackendClient *cc = in cryptodev_vhost_user_close_session() local
343 CryptoDevBackendClient *cc; in cryptodev_vhost_user_cleanup() local
348 cc = backend->conf.peers.ccs[i]; in cryptodev_vhost_user_cleanup()
349 if (cc) { in cryptodev_vhost_user_cleanup()
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| /qemu/target/cris/ |
| H A D | cpu.c | 206 CPUClass *cc = CPU_CLASS(oc); in crisv8_cpu_class_init() local
211 cc->tcg_ops = &crisv10_tcg_ops; in crisv8_cpu_class_init()
216 CPUClass *cc = CPU_CLASS(oc); in crisv9_cpu_class_init() local
226 CPUClass *cc = CPU_CLASS(oc); in crisv10_cpu_class_init() local
236 CPUClass *cc = CPU_CLASS(oc); in crisv11_cpu_class_init() local
246 CPUClass *cc = CPU_CLASS(oc); in crisv17_cpu_class_init() local
256 CPUClass *cc = CPU_CLASS(oc); in crisv32_cpu_class_init() local
266 CPUClass *cc = CPU_CLASS(oc); in cris_cpu_class_init() local
280 cc->set_pc = cris_cpu_set_pc; in cris_cpu_class_init()
281 cc->get_pc = cris_cpu_get_pc; in cris_cpu_class_init()
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| /qemu/accel/ |
| H A D | accel-target.c | 62 CPUClass *cc = CPU_CLASS(klass); in accel_init_cpu_int_aux() local
75 cc->accel_cpu = accel_cpu; in accel_init_cpu_int_aux()
77 accel_cpu->cpu_class_init(cc); in accel_init_cpu_int_aux()
79 if (cc->init_accel_cpu) { in accel_init_cpu_int_aux()
80 cc->init_accel_cpu(accel_cpu, cc); in accel_init_cpu_int_aux()
115 CPUClass *cc = CPU_GET_CLASS(cpu); in accel_cpu_instance_init() local
117 if (cc->accel_cpu && cc->accel_cpu->cpu_instance_init) { in accel_cpu_instance_init()
118 cc->accel_cpu->cpu_instance_init(cpu); in accel_cpu_instance_init()
124 CPUClass *cc = CPU_GET_CLASS(cpu); in accel_cpu_common_realize() local
129 if (cc->accel_cpu && cc->accel_cpu->cpu_target_realize in accel_cpu_common_realize()
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| /qemu/pc-bios/optionrom/ |
| H A D | Makefile | 24 cc-test = $(CC) -Werror $1 -c -o /dev/null -xc /dev/null >/dev/null 2>/dev/null
25 cc-option = if $(call cc-test, $1); then \
31 config-cc.mak: Makefile
32 $(quiet-@)($(call cc-option,-fcf-protection=none); \
33 $(call cc-option,-fno-pie); \
34 $(call cc-option,-no-pie); \
35 $(call cc-option,-fno-stack-protector); \
36 $(call cc-option,-Wno-array-bounds)) 3> config-cc.mak
37 -include config-cc.mak
64 rm -f config-cc.mak
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| /qemu/target/tricore/ |
| H A D | cpu.c | 177 CPUClass *cc = CPU_CLASS(c); in tricore_cpu_class_init() local
186 cc->class_by_name = tricore_cpu_class_by_name; in tricore_cpu_class_init()
187 cc->has_work = tricore_cpu_has_work; in tricore_cpu_class_init()
188 cc->mmu_index = tricore_cpu_mmu_index; in tricore_cpu_class_init()
192 cc->gdb_num_core_regs = 44; in tricore_cpu_class_init()
193 cc->gdb_arch_name = tricore_gdb_arch_name; in tricore_cpu_class_init()
195 cc->dump_state = tricore_cpu_dump_state; in tricore_cpu_class_init()
196 cc->set_pc = tricore_cpu_set_pc; in tricore_cpu_class_init()
197 cc->get_pc = tricore_cpu_get_pc; in tricore_cpu_class_init()
198 cc->sysemu_ops = &tricore_sysemu_ops; in tricore_cpu_class_init()
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| /qemu/target/s390x/ |
| H A D | cpu.c | 106 assert(cc <= 3); in s390_cpu_get_psw_mask()
108 r |= cc << 44; in s390_cpu_get_psw_mask()
347 CPUClass *cc = CPU_CLASS(scc); in s390_cpu_class_init() local
359 cc->has_work = s390_cpu_has_work; in s390_cpu_class_init()
360 cc->mmu_index = s390x_cpu_mmu_index; in s390_cpu_class_init()
361 cc->dump_state = s390_cpu_dump_state; in s390_cpu_class_init()
363 cc->set_pc = s390_cpu_set_pc; in s390_cpu_class_init()
364 cc->get_pc = s390_cpu_get_pc; in s390_cpu_class_init()
368 s390_cpu_class_init_sysemu(cc); in s390_cpu_class_init()
372 cc->gdb_arch_name = s390_gdb_arch_name; in s390_cpu_class_init()
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| H A D | sigp.c | 26 int cc; member
34 si->cc = SIGP_CC_STATUS_STORED; in set_sigp_status()
90 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_emergency()
104 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_start()
125 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_stop()
150 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_stop_and_store_status()
171 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_store_status_at_address()
224 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_store_adtl_status()
248 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_restart()
260 si->cc = SIGP_CC_ORDER_CODE_ACCEPTED; in sigp_initial_cpu_reset()
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| /qemu/pc-bios/s390-ccw/ |
| H A D | Makefile | 45 cc-test = $(CC) -Werror $1 -c -o /dev/null -xc /dev/null >/dev/null 2>/dev/null
46 cc-option = if $(call cc-test, $1); then \
50 config-cc.mak: Makefile
51 $(quiet-@)($(call cc-option,-Wno-stringop-overflow); \
52 $(call cc-option,-fno-stack-protector); \
53 $(call cc-option,-Wno-array-bounds); \
54 $(call cc-option,-Wno-gnu); \
55 $(call cc-option,-march=z900,-march=z10)) 3> config-cc.mak
56 -include config-cc.mak
79 rm -f config-cc.mak
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| /qemu/target/rx/ |
| H A D | cpu.c | 202 CPUClass *cc = CPU_CLASS(klass); in rx_cpu_class_init() local
211 cc->class_by_name = rx_cpu_class_by_name; in rx_cpu_class_init()
212 cc->has_work = rx_cpu_has_work; in rx_cpu_class_init()
213 cc->mmu_index = riscv_cpu_mmu_index; in rx_cpu_class_init()
214 cc->dump_state = rx_cpu_dump_state; in rx_cpu_class_init()
215 cc->set_pc = rx_cpu_set_pc; in rx_cpu_class_init()
216 cc->get_pc = rx_cpu_get_pc; in rx_cpu_class_init()
219 cc->sysemu_ops = &rx_sysemu_ops; in rx_cpu_class_init()
223 cc->disas_set_info = rx_cpu_disas_set_info; in rx_cpu_class_init()
225 cc->gdb_core_xml_file = "rx-core.xml"; in rx_cpu_class_init()
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| /qemu/target/hppa/ |
| H A D | cpu.c | 202 CPUClass *cc = CPU_CLASS(oc); in hppa_cpu_class_init() local
208 cc->class_by_name = hppa_cpu_class_by_name; in hppa_cpu_class_init()
209 cc->has_work = hppa_cpu_has_work; in hppa_cpu_class_init()
210 cc->mmu_index = hppa_cpu_mmu_index; in hppa_cpu_class_init()
211 cc->dump_state = hppa_cpu_dump_state; in hppa_cpu_class_init()
212 cc->set_pc = hppa_cpu_set_pc; in hppa_cpu_class_init()
213 cc->get_pc = hppa_cpu_get_pc; in hppa_cpu_class_init()
218 cc->sysemu_ops = &hppa_sysemu_ops; in hppa_cpu_class_init()
220 cc->disas_set_info = hppa_cpu_disas_set_info; in hppa_cpu_class_init()
221 cc->gdb_num_core_regs = 128; in hppa_cpu_class_init()
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| /qemu/target/xtensa/ |
| H A D | cpu.c | 247 CPUClass *cc = CPU_CLASS(oc); in xtensa_cpu_class_init() local
248 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); in xtensa_cpu_class_init()
257 cc->class_by_name = xtensa_cpu_class_by_name; in xtensa_cpu_class_init()
258 cc->has_work = xtensa_cpu_has_work; in xtensa_cpu_class_init()
259 cc->mmu_index = xtensa_cpu_mmu_index; in xtensa_cpu_class_init()
260 cc->dump_state = xtensa_cpu_dump_state; in xtensa_cpu_class_init()
261 cc->set_pc = xtensa_cpu_set_pc; in xtensa_cpu_class_init()
262 cc->get_pc = xtensa_cpu_get_pc; in xtensa_cpu_class_init()
265 cc->gdb_stop_before_watchpoint = true; in xtensa_cpu_class_init()
267 cc->sysemu_ops = &xtensa_sysemu_ops; in xtensa_cpu_class_init()
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| /qemu/target/alpha/ |
| H A D | cpu.c | 231 CPUClass *cc = CPU_CLASS(oc); in alpha_cpu_class_init() local
237 cc->class_by_name = alpha_cpu_class_by_name; in alpha_cpu_class_init()
238 cc->has_work = alpha_cpu_has_work; in alpha_cpu_class_init()
239 cc->mmu_index = alpha_cpu_mmu_index; in alpha_cpu_class_init()
240 cc->dump_state = alpha_cpu_dump_state; in alpha_cpu_class_init()
241 cc->set_pc = alpha_cpu_set_pc; in alpha_cpu_class_init()
242 cc->get_pc = alpha_cpu_get_pc; in alpha_cpu_class_init()
247 cc->sysemu_ops = &alpha_sysemu_ops; in alpha_cpu_class_init()
249 cc->disas_set_info = alpha_cpu_disas_set_info; in alpha_cpu_class_init()
251 cc->tcg_ops = &alpha_tcg_ops; in alpha_cpu_class_init()
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| /qemu/target/sparc/ |
| H A D | insns.decode | 10 &bcc i a cond cc
11 BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
13 FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc
33 &r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
197 &r_r_ri_cc rs1=0 cc=0
223 Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
300 FCMPs 10 000 cc:2 110101 rs1:5 0 0101 0001 rs2:5
301 FCMPd 10 000 cc:2 110101 rs1:5 0 0101 0010 rs2:5
302 FCMPq 10 000 cc:2 110101 rs1:5 0 0101 0011 rs2:5
303 FCMPEs 10 000 cc:2 110101 rs1:5 0 0101 0101 rs2:5
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