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Searched refs:config (Results 151 – 175 of 510) sorted by last modified time

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/qemu/hw/virtio/
H A Dvirtio-iommu.c89 bypassed = s->config.bypass; in virtio_iommu_device_bypassed()
95 bypassed = s->config.bypass; in virtio_iommu_device_bypassed()
901 bypass_allowed = s->config.bypass; in virtio_iommu_translate()
1158 s->config.page_size_mask &= new_mask; in virtio_iommu_set_page_size_mask()
1274 s->config.bypass = s->boot_bypass; in virtio_iommu_system_reset()
1284 if (likely(s->config.bypass)) { in virtio_iommu_freeze_granule()
1290 s->config.bypass = false; in virtio_iommu_freeze_granule()
1293 s->config.bypass = true; in virtio_iommu_freeze_granule()
1316 s->config.bypass = s->boot_bypass; in virtio_iommu_device_realize()
1321 s->config.input_range.end = in virtio_iommu_device_realize()
[all …]
H A Dvhost-vsock.c24 static void vhost_vsock_get_config(VirtIODevice *vdev, uint8_t *config) in vhost_vsock_get_config() argument
30 memcpy(config, &vsockcfg, sizeof(vsockcfg)); in vhost_vsock_get_config()
H A Dvhost-user.c221 VhostUserConfig config; member
2412 static int vhost_user_get_config(struct vhost_dev *dev, uint8_t *config, in vhost_user_get_config() argument
2430 msg.payload.config.offset = 0; in vhost_user_get_config()
2431 msg.payload.config.size = config_len; in vhost_user_get_config()
2456 memcpy(config, msg.payload.config.region, config_len); in vhost_user_get_config()
2488 msg.payload.config.offset = offset, in vhost_user_set_config()
2489 msg.payload.config.size = size, in vhost_user_set_config()
2490 msg.payload.config.flags = flags, in vhost_user_set_config()
2491 p = msg.payload.config.region; in vhost_user_set_config()
/qemu/hw/xen/
H A Dxen_pt_config_init.c1998 case 1: pci_set_byte(s->dev.config + offset, (uint8_t)val); in xen_pt_config_reg_init()
2000 case 2: pci_set_word(s->dev.config + offset, (uint16_t)val); in xen_pt_config_reg_init()
2002 case 4: pci_set_long(s->dev.config + offset, val); in xen_pt_config_reg_init()
2007 reg_entry->ptr.byte = s->dev.config + offset; in xen_pt_config_reg_init()
H A Dxen_pt.c792 memset(d->config, 0, PCI_CONFIG_SPACE_SIZE); in xen_pt_realize()
H A Dxen_pt_graphics.c411 pci_config_set_device_id(bridge_dev->config, pch_dev_id); in type_init()
412 pci_config_set_revision(bridge_dev->config, pch_rev_id); in type_init()
/qemu/hw/vfio/
H A Dpci-quirks.c1205 pci_set_long(vdev->pdev.config + IGD_ASLS, 0); in vfio_pci_igd_opregion_init()
1556 if (pci_get_byte(pdev->config + PCI_CLASS_DEVICE + 1) != in vfio_add_nv_gpudirect_cap()
1584 tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]; in vfio_add_nv_gpudirect_cap()
1604 pci_set_byte(pdev->config + pos++, 8); in vfio_add_nv_gpudirect_cap()
1605 pci_set_byte(pdev->config + pos++, 'P'); in vfio_add_nv_gpudirect_cap()
1606 pci_set_byte(pdev->config + pos++, '2'); in vfio_add_nv_gpudirect_cap()
1607 pci_set_byte(pdev->config + pos++, 'P'); in vfio_add_nv_gpudirect_cap()
1609 pci_set_byte(pdev->config + pos, 0); in vfio_add_nv_gpudirect_cap()
1662 pci_set_byte(vdev->pdev.config + pos++, VMD_SHADOW_CAP_LEN); in vfio_add_vmd_shadow_cap()
1663 pci_set_byte(vdev->pdev.config + pos++, VMD_SHADOW_CAP_VER); in vfio_add_vmd_shadow_cap()
[all …]
H A Dpci.c277 pci_config_set_interrupt_pin(vdev->pdev.config, pin); in vfio_intx_enable()
2144 cap_id = pdev->config[pos]; in vfio_add_std_cap()
2145 next = pdev->config[pos + PCI_CAP_LIST_NEXT]; in vfio_add_std_cap()
2169 pdev->config[PCI_CAPABILITY_LIST] = 0; in vfio_add_std_cap()
2274 uint8_t *config; in vfio_add_ext_cap() local
2288 config = g_memdup(pdev->config, vdev->config_size); in vfio_add_ext_cap()
2321 header = pci_get_long(config + next); in vfio_add_ext_cap()
2331 size = vfio_ext_cap_max_size(config, next); in vfio_add_ext_cap()
2359 g_free(config); in vfio_add_ext_cap()
2369 !pdev->config[PCI_CAPABILITY_LIST]) { in vfio_add_capabilities()
[all …]
/qemu/hw/misc/
H A Divshmem.c847 pci_conf = dev->config; in ivshmem_common_realize()
/qemu/hw/pci/
H A Dpcie.c73 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_v1_fill()
111 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_fill_slot_lnk()
201 exp_cap = dev->config + pos; in pcie_cap_init()
315 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_flags_set_vector()
366 uint8_t *exp_cap = dev->config + pos; in hotplug_event_update_event_status()
410 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_slot_enable_power()
559 uint8_t *exp_cap = dev->config + dev->exp.exp_cap; in pcie_cap_slot_do_unplug()
759 uint8_t *exp_cap = dev->config + pos; in pcie_cap_slot_get()
791 uint8_t *exp_cap = dev->config + pos; in pcie_cap_slot_write_config()
993 header = pci_get_long(dev->config + next); in pcie_find_capability_list()
[all …]
H A Dpcie_sriov.c32 uint8_t *cfg = dev->config + offset; in pcie_sriov_pf_init()
96 pci_set_long(dev->config + addr, type); in pcie_sriov_pf_init_vf_bar()
160 pci_config_set_vendor_id(dev->config, 0xffff); in register_vf()
161 pci_config_set_device_id(dev->config, 0xffff); in register_vf()
172 pci_get_word(dev->config + sriov_cap + PCI_SRIOV_VF_OFFSET); in register_vfs()
174 pci_get_word(dev->config + sriov_cap + PCI_SRIOV_VF_STRIDE); in register_vfs()
259 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); in pcie_sriov_pf_reset()
262 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0); in pcie_sriov_pf_reset()
268 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); in pcie_sriov_pf_reset()
271 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, in pcie_sriov_pf_reset()
[all …]
H A Dmsi.c129 uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev)); in msi_set_message()
173 (pci_get_word(dev->config + msi_flags_off(dev)) & in msi_enabled()
236 pci_set_word(dev->config + msi_flags_off(dev), flags); in msi_init()
265 flags = pci_get_word(dev->config + msi_flags_off(dev)); in msi_uninit()
283 flags = pci_get_word(dev->config + msi_flags_off(dev)); in msi_reset()
287 pci_set_word(dev->config + msi_flags_off(dev), flags); in msi_reset()
288 pci_set_long(dev->config + msi_address_lo_off(dev), 0); in msi_reset()
290 pci_set_long(dev->config + msi_address_hi_off(dev), 0); in msi_reset()
292 pci_set_word(dev->config + msi_data_off(dev, msi64bit), 0); in msi_reset()
316 mask = pci_get_long(dev->config + in msi_is_masked()
[all …]
H A Dshpc.c207 shpc->config[SHPC_SEC_BUS] |= speed; in shpc_set_sec_bus_speed()
220 memset(shpc->config, 0, SHPC_SIZEOF(d)); in shpc_reset()
223 pci_set_long(shpc->config + SHPC_SLOTS_66, 0); in shpc_reset()
225 pci_set_word(shpc->config + SHPC_PHYS_SLOT, in shpc_reset()
457 shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask); in shpc_write()
473 memcpy(&val, d->shpc->config + addr, l); in shpc_read()
501 uint8_t *config; in shpc_cap_add_config() local
509 config = d->config + config_offset; in shpc_cap_add_config()
512 pci_set_byte(config + SHPC_CAP_CxP, 0); in shpc_cap_add_config()
668 shpc->config = g_malloc0(SHPC_SIZEOF(d)); in shpc_init()
[all …]
/qemu/hw/ide/
H A Dich.c119 pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1); in pci_ich9_ahci_realize()
121 dev->config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ in pci_ich9_ahci_realize()
122 dev->config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */ in pci_ich9_ahci_realize()
123 pci_config_set_interrupt_pin(dev->config, 1); in pci_ich9_ahci_realize()
126 dev->config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ in pci_ich9_ahci_realize()
142 sata_cap = dev->config + sata_cap_offset; in pci_ich9_ahci_realize()
/qemu/hw/pci-bridge/
H A Dpci_expander_bridge.c380 pci_word_test_and_set_mask(dev->config + PCI_STATUS, in pxb_dev_realize_common()
382 pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_HOST); in pxb_dev_realize_common()
/qemu/hw/i386/
H A Dacpi-build.c2250 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS]; in insert_ivhd()
/qemu/hw/display/
H A Dati.c980 pci_set_word(dev->config + PCI_DEVICE_ID, s->dev_id); in ati_vga_realize()
1018 dev->config[PCI_INTERRUPT_PIN] = 1; in ati_vga_realize()
/qemu/hw/gpio/
H A DKconfig1 config MAX7310
5 config PL061
8 config GPIO_KEY
11 config GPIO_MPC8XXX
14 config GPIO_PWR
17 config SIFIVE_GPIO
20 config STM32L4X5_GPIO
23 config PCF8574
/qemu/hw/cxl/
H A Dcxl-component-utils.c387 pci_set_long(pdev->config + offset + PCIE_DVSEC_HEADER1_OFFSET, in cxl_component_create_dvsec()
389 pci_set_word(pdev->config + offset + PCIE_DVSEC_ID_OFFSET, type); in cxl_component_create_dvsec()
390 memcpy(pdev->config + offset + sizeof(DVSECHeader), in cxl_component_create_dvsec()
/qemu/ebpf/
H A Debpf_rss-stub.c37 bool ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct EBPFRSSConfig *config, in ebpf_rss_set_all() argument
H A Debpf_rss.h49 bool ebpf_rss_set_all(struct EBPFRSSContext *ctx, struct EBPFRSSConfig *config,
/qemu/docs/interop/
H A Dvhost-user.rst267 Virtio device config space
369 VhostUserConfig config;
1412 :request payload: virtio device config space
1413 :reply payload: virtio device config space
1426 :request payload: virtio device config space
H A Dfirmware.json375 # defaults to $HOME/.config).
/qemu/docs/devel/
H A Dacpi-bits.rst57 │ ├── bits-config
110 * ``tests/avocado/acpi-bits/bits-config``:
115 ``bits-config.txt``:
116 This is the biosbits config file that determines what tests
117 or actions are performed by bits. The description of the config options are
/qemu/hw/acpi/
H A Daml-build.c2372 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; in build_crs()
2374 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; in build_crs()

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