| /dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/imx/common/include/ |
| H A D | imx_clock.h | 193 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
204 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOTUSB_PLL ((BIT(26) | BIT(25) | BIT(24))
226 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
259 #define CCM_TRGT_MUX_AHB_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
358 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
369 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
380 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
424 #define CCM_TRGT_MUX_EIM_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
490 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
853 #define CCM_TRGT_MUX_CCM_CLKO1_REF_1M ((BIT(26) | BIT(25) | BIT(24))
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| /dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/imx/common/include/ |
| H A D | imx_clock.h | 193 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
204 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOTUSB_PLL ((BIT(26) | BIT(25) | BIT(24))
226 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
259 #define CCM_TRGT_MUX_AHB_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
358 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
369 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
380 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
424 #define CCM_TRGT_MUX_EIM_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
490 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
853 #define CCM_TRGT_MUX_CCM_CLKO1_REF_1M ((BIT(26) | BIT(25) | BIT(24))
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| /dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/imx/common/include/ |
| H A D | imx_clock.h | 193 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
204 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOTUSB_PLL ((BIT(26) | BIT(25) | BIT(24))
226 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
259 #define CCM_TRGT_MUX_AHB_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
358 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
369 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
380 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
424 #define CCM_TRGT_MUX_EIM_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
490 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
853 #define CCM_TRGT_MUX_CCM_CLKO1_REF_1M ((BIT(26) | BIT(25) | BIT(24))
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| /dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/imx/common/include/ |
| H A D | imx_clock.h | 193 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
204 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOTUSB_PLL ((BIT(26) | BIT(25) | BIT(24))
226 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
259 #define CCM_TRGT_MUX_AHB_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
358 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
369 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
380 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
424 #define CCM_TRGT_MUX_EIM_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
490 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
853 #define CCM_TRGT_MUX_CCM_CLKO1_REF_1M ((BIT(26) | BIT(25) | BIT(24))
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| /dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/imx/common/include/ |
| H A D | imx_clock.h | 193 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
204 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOTUSB_PLL ((BIT(26) | BIT(25) | BIT(24))
226 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
259 #define CCM_TRGT_MUX_AHB_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
358 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
369 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
380 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
424 #define CCM_TRGT_MUX_EIM_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
490 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
853 #define CCM_TRGT_MUX_CCM_CLKO1_REF_1M ((BIT(26) | BIT(25) | BIT(24))
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/bridge/ |
| H A D | sil-sii8620.h | 46 #define BIT_DPD_PWRON_PLL BIT(7)
47 #define BIT_DPD_PDNTX12 BIT(6)
48 #define BIT_DPD_PDNRX12 BIT(5)
49 #define BIT_DPD_OSC_EN BIT(4)
50 #define BIT_DPD_PWRON_HSIC BIT(3)
51 #define BIT_DPD_PDIDCK_N BIT(2)
60 #define BIT_DCTL_TRANSCODE BIT(3)
149 #define BIT_DDC_CMD_DONE BIT(3)
219 #define BIT_BIST_TRANS BIT(2)
220 #define BIT_BIST_RESET BIT(1)
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/bridge/ |
| H A D | sil-sii8620.h | 46 #define BIT_DPD_PWRON_PLL BIT(7)
47 #define BIT_DPD_PDNTX12 BIT(6)
48 #define BIT_DPD_PDNRX12 BIT(5)
49 #define BIT_DPD_OSC_EN BIT(4)
50 #define BIT_DPD_PWRON_HSIC BIT(3)
51 #define BIT_DPD_PDIDCK_N BIT(2)
60 #define BIT_DCTL_TRANSCODE BIT(3)
149 #define BIT_DDC_CMD_DONE BIT(3)
219 #define BIT_BIST_TRANS BIT(2)
220 #define BIT_BIST_RESET BIT(1)
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/bridge/ |
| H A D | sil-sii8620.h | 46 #define BIT_DPD_PWRON_PLL BIT(7)
47 #define BIT_DPD_PDNTX12 BIT(6)
48 #define BIT_DPD_PDNRX12 BIT(5)
49 #define BIT_DPD_OSC_EN BIT(4)
50 #define BIT_DPD_PWRON_HSIC BIT(3)
51 #define BIT_DPD_PDIDCK_N BIT(2)
60 #define BIT_DCTL_TRANSCODE BIT(3)
149 #define BIT_DDC_CMD_DONE BIT(3)
219 #define BIT_BIST_TRANS BIT(2)
220 #define BIT_BIST_RESET BIT(1)
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/freescale/dpaa2/ |
| H A D | dpkg.h | 64 #define NH_FLD_ETH_DA BIT(0)
65 #define NH_FLD_ETH_SA BIT(1)
67 #define NH_FLD_ETH_TYPE BIT(3)
73 #define NH_FLD_VLAN_VPRI BIT(0)
85 #define NH_FLD_IP_VER BIT(0)
86 #define NH_FLD_IP_DSCP BIT(2)
87 #define NH_FLD_IP_ECN BIT(3)
89 #define NH_FLD_IP_SRC BIT(5)
90 #define NH_FLD_IP_DST BIT(6)
92 #define NH_FLD_IP_ID BIT(8)
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/freescale/dpaa2/ |
| H A D | dpkg.h | 64 #define NH_FLD_ETH_DA BIT(0)
65 #define NH_FLD_ETH_SA BIT(1)
67 #define NH_FLD_ETH_TYPE BIT(3)
73 #define NH_FLD_VLAN_VPRI BIT(0)
85 #define NH_FLD_IP_VER BIT(0)
86 #define NH_FLD_IP_DSCP BIT(2)
87 #define NH_FLD_IP_ECN BIT(3)
89 #define NH_FLD_IP_SRC BIT(5)
90 #define NH_FLD_IP_DST BIT(6)
92 #define NH_FLD_IP_ID BIT(8)
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/freescale/dpaa2/ |
| H A D | dpkg.h | 64 #define NH_FLD_ETH_DA BIT(0)
65 #define NH_FLD_ETH_SA BIT(1)
67 #define NH_FLD_ETH_TYPE BIT(3)
73 #define NH_FLD_VLAN_VPRI BIT(0)
85 #define NH_FLD_IP_VER BIT(0)
86 #define NH_FLD_IP_DSCP BIT(2)
87 #define NH_FLD_IP_ECN BIT(3)
89 #define NH_FLD_IP_SRC BIT(5)
90 #define NH_FLD_IP_DST BIT(6)
92 #define NH_FLD_IP_ID BIT(8)
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| /dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/drivers/renesas/rcar/pfc/V3M/ |
| H A D | pfc_init_v3m.c | 20 #define GPSR0_DU_DB7 BIT(17)
21 #define GPSR0_DU_DB6 BIT(16)
22 #define GPSR0_DU_DB5 BIT(15)
23 #define GPSR0_DU_DB4 BIT(14)
24 #define GPSR0_DU_DB3 BIT(13)
28 #define GPSR0_DU_DG5 BIT(9)
29 #define GPSR0_DU_DG4 BIT(8)
30 #define GPSR0_DU_DG3 BIT(7)
31 #define GPSR0_DU_DG2 BIT(6)
32 #define GPSR0_DU_DR7 BIT(5)
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| /dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/drivers/renesas/rcar/pfc/V3M/ |
| H A D | pfc_init_v3m.c | 20 #define GPSR0_DU_DB7 BIT(17)
21 #define GPSR0_DU_DB6 BIT(16)
22 #define GPSR0_DU_DB5 BIT(15)
23 #define GPSR0_DU_DB4 BIT(14)
24 #define GPSR0_DU_DB3 BIT(13)
28 #define GPSR0_DU_DG5 BIT(9)
29 #define GPSR0_DU_DG4 BIT(8)
30 #define GPSR0_DU_DG3 BIT(7)
31 #define GPSR0_DU_DG2 BIT(6)
32 #define GPSR0_DU_DR7 BIT(5)
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| /dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/drivers/renesas/rcar/pfc/V3M/ |
| H A D | pfc_init_v3m.c | 20 #define GPSR0_DU_DB7 BIT(17)
21 #define GPSR0_DU_DB6 BIT(16)
22 #define GPSR0_DU_DB5 BIT(15)
23 #define GPSR0_DU_DB4 BIT(14)
24 #define GPSR0_DU_DB3 BIT(13)
28 #define GPSR0_DU_DG5 BIT(9)
29 #define GPSR0_DU_DG4 BIT(8)
30 #define GPSR0_DU_DG3 BIT(7)
31 #define GPSR0_DU_DG2 BIT(6)
32 #define GPSR0_DU_DR7 BIT(5)
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| /dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/drivers/renesas/rcar/pfc/V3M/ |
| H A D | pfc_init_v3m.c | 20 #define GPSR0_DU_DB7 BIT(17)
21 #define GPSR0_DU_DB6 BIT(16)
22 #define GPSR0_DU_DB5 BIT(15)
23 #define GPSR0_DU_DB4 BIT(14)
24 #define GPSR0_DU_DB3 BIT(13)
28 #define GPSR0_DU_DG5 BIT(9)
29 #define GPSR0_DU_DG4 BIT(8)
30 #define GPSR0_DU_DG3 BIT(7)
31 #define GPSR0_DU_DG2 BIT(6)
32 #define GPSR0_DU_DR7 BIT(5)
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| /dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/drivers/renesas/rcar/pfc/V3M/ |
| H A D | pfc_init_v3m.c | 20 #define GPSR0_DU_DB7 BIT(17)
21 #define GPSR0_DU_DB6 BIT(16)
22 #define GPSR0_DU_DB5 BIT(15)
23 #define GPSR0_DU_DB4 BIT(14)
24 #define GPSR0_DU_DB3 BIT(13)
28 #define GPSR0_DU_DG5 BIT(9)
29 #define GPSR0_DU_DG4 BIT(8)
30 #define GPSR0_DU_DG3 BIT(7)
31 #define GPSR0_DU_DG2 BIT(6)
32 #define GPSR0_DU_DR7 BIT(5)
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/wireless/realtek/rtl8xxxu/ |
| H A D | rtl8xxxu_regs.h | 121 #define EFUSE_CELL_SEL (BIT(8) | BIT(9))
281 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23))
296 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
299 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19))
318 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1))
319 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3))
320 #define GPIO_HCI_SEL (BIT(4) | BIT(5))
337 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
760 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8))
945 #define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26))
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/wireless/realtek/rtl8xxxu/ |
| H A D | rtl8xxxu_regs.h | 121 #define EFUSE_CELL_SEL (BIT(8) | BIT(9))
281 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23))
296 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
299 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19))
318 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1))
319 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3))
320 #define GPIO_HCI_SEL (BIT(4) | BIT(5))
337 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
760 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8))
945 #define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26))
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/wireless/realtek/rtl8xxxu/ |
| H A D | rtl8xxxu_regs.h | 121 #define EFUSE_CELL_SEL (BIT(8) | BIT(9))
281 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23))
296 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
299 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19))
318 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1))
319 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3))
320 #define GPIO_HCI_SEL (BIT(4) | BIT(5))
337 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
760 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8))
945 #define CCK0_AFE_RX_ANT_B (BIT(24) | BIT(26))
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8188eu/include/ |
| H A D | rtl8188e_spec.h | 803 #define EF_CELL_SEL (BIT(8) | BIT(9))
840 #define CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
854 #define EFS_HCI_SEL (BIT(0) | BIT(1))
855 #define PAD_HCI_SEL (BIT(2) | BIT(3))
856 #define HCI_SEL (BIT(4) | BIT(5))
873 #define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
1051 #define ACRC BIT(8)
1056 #define AAP BIT(0)
1057 #define APM BIT(1)
1058 #define AM BIT(2)
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8188eu/include/ |
| H A D | rtl8188e_spec.h | 803 #define EF_CELL_SEL (BIT(8) | BIT(9))
840 #define CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
854 #define EFS_HCI_SEL (BIT(0) | BIT(1))
855 #define PAD_HCI_SEL (BIT(2) | BIT(3))
856 #define HCI_SEL (BIT(4) | BIT(5))
873 #define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
1051 #define ACRC BIT(8)
1056 #define AAP BIT(0)
1057 #define APM BIT(1)
1058 #define AM BIT(2)
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8188eu/include/ |
| H A D | rtl8188e_spec.h | 803 #define EF_CELL_SEL (BIT(8) | BIT(9))
840 #define CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
854 #define EFS_HCI_SEL (BIT(0) | BIT(1))
855 #define PAD_HCI_SEL (BIT(2) | BIT(3))
856 #define HCI_SEL (BIT(4) | BIT(5))
873 #define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
1051 #define ACRC BIT(8)
1056 #define AAP BIT(0)
1057 #define APM BIT(1)
1058 #define AM BIT(2)
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/emxx_udc/ |
| H A D | emxx_udc.h | 48 #define TEST_FORCE_ENABLE (BIT(18) | BIT(16))
76 #define UFRAME (BIT(14) | BIT(13) | BIT(12))
82 #define SQUSET (BIT(7) | BIT(6) | BIT(5) | BIT(4))
84 #define USB_SQUSET (BIT(6) | BIT(5) | BIT(4))
156 #define EP0_DW (BIT(6) | BIT(5))
158 #define EP0_DW3 (BIT(6) | BIT(5))
189 #define EP0_STATUS_RW_BIT (BIT(16) | BIT(15) | BIT(11) | 0xFF)
221 #define EPN_MODE (BIT(25) | BIT(24))
234 #define EPN_DW (BIT(6) | BIT(5))
236 #define EPN_DW3 (BIT(6) | BIT(5))
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/emxx_udc/ |
| H A D | emxx_udc.h | 48 #define TEST_FORCE_ENABLE (BIT(18) | BIT(16))
76 #define UFRAME (BIT(14) | BIT(13) | BIT(12))
82 #define SQUSET (BIT(7) | BIT(6) | BIT(5) | BIT(4))
84 #define USB_SQUSET (BIT(6) | BIT(5) | BIT(4))
156 #define EP0_DW (BIT(6) | BIT(5))
158 #define EP0_DW3 (BIT(6) | BIT(5))
189 #define EP0_STATUS_RW_BIT (BIT(16) | BIT(15) | BIT(11) | 0xFF)
221 #define EPN_MODE (BIT(25) | BIT(24))
234 #define EPN_DW (BIT(6) | BIT(5))
236 #define EPN_DW3 (BIT(6) | BIT(5))
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/emxx_udc/ |
| H A D | emxx_udc.h | 48 #define TEST_FORCE_ENABLE (BIT(18) | BIT(16))
76 #define UFRAME (BIT(14) | BIT(13) | BIT(12))
82 #define SQUSET (BIT(7) | BIT(6) | BIT(5) | BIT(4))
84 #define USB_SQUSET (BIT(6) | BIT(5) | BIT(4))
156 #define EP0_DW (BIT(6) | BIT(5))
158 #define EP0_DW3 (BIT(6) | BIT(5))
189 #define EP0_STATUS_RW_BIT (BIT(16) | BIT(15) | BIT(11) | 0xFF)
221 #define EPN_MODE (BIT(25) | BIT(24))
234 #define EPN_DW (BIT(6) | BIT(5))
236 #define EPN_DW3 (BIT(6) | BIT(5))
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