| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 774 const MachineOperand *BaseOp1, *BaseOp2; in addLoopCarriedDependences() local
777 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, in addLoopCarriedDependences()
781 if (BaseOp1->isIdenticalTo(*BaseOp2) && in addLoopCarriedDependences()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3148 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
3150 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
3152 if (BaseOp1.getType() != BaseOp2.getType()) in shouldClusterMemOps()
3155 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
3159 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) in shouldClusterMemOps()
3196 if (BaseOp1.isFI()) { in shouldClusterMemOps()
3197 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps()
3202 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, in shouldClusterMemOps()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2811 const MachineOperand &BaseOp1 = *BaseOps1.front();
2813 assert((BaseOp1.isReg() || BaseOp1.isFI()) &&
2823 if ((BaseOp1.isReg() != BaseOp2.isReg()) ||
2824 (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) ||
2825 (BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex()))
2830 const MachineInstr &FirstLdSt = *BaseOp1.getParent();
2853 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 &&
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 362 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply() local
363 if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 || in apply()
364 BaseOp0->getReg() != BaseOp1->getReg()) in apply()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 774 const MachineOperand *BaseOp1, *BaseOp2; in addLoopCarriedDependences() local
777 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, in addLoopCarriedDependences()
781 if (BaseOp1->isIdenticalTo(*BaseOp2) && in addLoopCarriedDependences()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3148 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
3150 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
3152 if (BaseOp1.getType() != BaseOp2.getType()) in shouldClusterMemOps()
3155 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
3159 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) in shouldClusterMemOps()
3196 if (BaseOp1.isFI()) { in shouldClusterMemOps()
3197 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps()
3202 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, in shouldClusterMemOps()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 362 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply() local
363 if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 || in apply()
364 BaseOp0->getReg() != BaseOp1->getReg()) in apply()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2811 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
2813 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
2823 if ((BaseOp1.isReg() != BaseOp2.isReg()) || in shouldClusterMemOps()
2824 (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) || in shouldClusterMemOps()
2825 (BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex())) in shouldClusterMemOps()
2830 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
2853 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 && in shouldClusterMemOps()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 362 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply() local
363 if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 || in apply()
364 BaseOp0->getReg() != BaseOp1->getReg()) in apply()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2811 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
2813 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
2823 if ((BaseOp1.isReg() != BaseOp2.isReg()) || in shouldClusterMemOps()
2824 (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) || in shouldClusterMemOps()
2825 (BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex())) in shouldClusterMemOps()
2830 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
2853 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 && in shouldClusterMemOps()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 774 const MachineOperand *BaseOp1, *BaseOp2; in addLoopCarriedDependences() local
777 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, in addLoopCarriedDependences()
781 if (BaseOp1->isIdenticalTo(*BaseOp2) && in addLoopCarriedDependences()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3148 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
3150 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
3152 if (BaseOp1.getType() != BaseOp2.getType()) in shouldClusterMemOps()
3155 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
3159 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) in shouldClusterMemOps()
3196 if (BaseOp1.isFI()) { in shouldClusterMemOps()
3197 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps()
3202 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, in shouldClusterMemOps()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2811 const MachineOperand &BaseOp1 = *BaseOps1.front();
2813 assert((BaseOp1.isReg() || BaseOp1.isFI()) &&
2823 if ((BaseOp1.isReg() != BaseOp2.isReg()) ||
2824 (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) ||
2825 (BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex()))
2830 const MachineInstr &FirstLdSt = *BaseOp1.getParent();
2853 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 &&
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 362 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply() local
363 if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 || in apply()
364 BaseOp0->getReg() != BaseOp1->getReg()) in apply()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 774 const MachineOperand *BaseOp1, *BaseOp2;
777 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1,
781 if (BaseOp1->isIdenticalTo(*BaseOp2) &&
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3148 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
3150 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
3152 if (BaseOp1.getType() != BaseOp2.getType()) in shouldClusterMemOps()
3155 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
3159 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) in shouldClusterMemOps()
3196 if (BaseOp1.isFI()) { in shouldClusterMemOps()
3197 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps()
3202 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, in shouldClusterMemOps()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3148 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
3150 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
3152 if (BaseOp1.getType() != BaseOp2.getType()) in shouldClusterMemOps()
3155 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
3159 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) in shouldClusterMemOps()
3196 if (BaseOp1.isFI()) { in shouldClusterMemOps()
3197 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps()
3202 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, in shouldClusterMemOps()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 362 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply() local
363 if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 || in apply()
364 BaseOp0->getReg() != BaseOp1->getReg()) in apply()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2811 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
2813 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
2823 if ((BaseOp1.isReg() != BaseOp2.isReg()) || in shouldClusterMemOps()
2824 (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) || in shouldClusterMemOps()
2825 (BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex())) in shouldClusterMemOps()
2830 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
2853 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 && in shouldClusterMemOps()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 774 const MachineOperand *BaseOp1, *BaseOp2; in addLoopCarriedDependences() local
777 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, in addLoopCarriedDependences()
781 if (BaseOp1->isIdenticalTo(*BaseOp2) && in addLoopCarriedDependences()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 773 const MachineOperand *BaseOp1, *BaseOp2; in addLoopCarriedDependences() local
776 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, in addLoopCarriedDependences()
780 if (BaseOp1->isIdenticalTo(*BaseOp2) && in addLoopCarriedDependences()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3133 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
3135 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
3137 if (BaseOp1.getType() != BaseOp2.getType()) in shouldClusterMemOps()
3140 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
3144 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) in shouldClusterMemOps()
3181 if (BaseOp1.isFI()) { in shouldClusterMemOps()
3182 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps()
3187 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, in shouldClusterMemOps()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 362 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply() local
363 if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 || in apply()
364 BaseOp0->getReg() != BaseOp1->getReg()) in apply()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2819 const MachineOperand &BaseOp1 = *BaseOps1.front(); in shouldClusterMemOps() local
2821 assert((BaseOp1.isReg() || BaseOp1.isFI()) && in shouldClusterMemOps()
2831 if ((BaseOp1.isReg() != BaseOp2.isReg()) || in shouldClusterMemOps()
2832 (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg()) || in shouldClusterMemOps()
2833 (BaseOp1.isFI() && BaseOp1.getIndex() != BaseOp2.getIndex())) in shouldClusterMemOps()
2838 const MachineInstr &FirstLdSt = *BaseOp1.getParent(); in shouldClusterMemOps()
2861 assert(Base1 == &BaseOp1 && Base2 == &BaseOp2 && in shouldClusterMemOps()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 773 const MachineOperand *BaseOp1, *BaseOp2; in addLoopCarriedDependences() local
776 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, in addLoopCarriedDependences()
780 if (BaseOp1->isIdenticalTo(*BaseOp2) && in addLoopCarriedDependences()
|