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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/llvm80/llvm-8.0.1.src/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/NewGVN/
H A Dflags-simplify.ll16 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
17 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
18 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
32 ; CHECK-NEXT: [[CONV3:%.*]] = shl i64 [[TMP:%.*]], 32
33 ; CHECK-NEXT: store i64 [[CONV3]], i64* @f, align 8
34 ; CHECK-NEXT: [[CONV7:%.*]] = ashr exact i64 [[CONV3]], 32
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/LoopVectorize/X86/
H A Dpr35432.ll37 ; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i8
39 ; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[CONV3]], -1
48 ; CHECK-NEXT: [[TMP8:%.*]] = add i8 [[CONV3]], -1
71 ; CHECK-NEXT: [[IND_END:%.*]] = sub i8 [[CONV3]], [[CAST_CRD]]
79 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i8 [[CONV3]], [[TMP23]]
97 …L:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]…
/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/LoopVectorize/X86/
H A Dpr35432.ll37 ; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i8
39 ; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[CONV3]], -1
48 ; CHECK-NEXT: [[TMP8:%.*]] = add i8 [[CONV3]], -1
71 ; CHECK-NEXT: [[IND_END:%.*]] = sub i8 [[CONV3]], [[CAST_CRD]]
79 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i8 [[CONV3]], [[TMP23]]
97 …L:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]…
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/LoopVectorize/X86/
H A Dpr35432.ll37 ; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i8
39 ; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[CONV3]], -1
47 ; CHECK-NEXT: [[TMP7:%.*]] = add i8 [[CONV3]], -1
69 ; CHECK-NEXT: [[IND_END:%.*]] = sub i8 [[CONV3]], [[CAST_CRD]]
77 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i8 [[CONV3]], [[TMP21]]
95 …L:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]…
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/LoopVectorize/X86/
H A Dpr35432.ll37 ; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i8
39 ; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[CONV3]], -1
47 ; CHECK-NEXT: [[TMP7:%.*]] = add i8 [[CONV3]], -1
69 ; CHECK-NEXT: [[IND_END:%.*]] = sub i8 [[CONV3]], [[CAST_CRD]]
77 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i8 [[CONV3]], [[TMP21]]
95 …L:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]…
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/LoopVectorize/X86/
H A Dpr35432.ll37 ; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i8
39 ; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[CONV3]], -1
48 ; CHECK-NEXT: [[TMP8:%.*]] = add i8 [[CONV3]], -1
71 ; CHECK-NEXT: [[IND_END:%.*]] = sub i8 [[CONV3]], [[CAST_CRD]]
79 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i8 [[CONV3]], [[TMP23]]
97 …L:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]…
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/LoopVectorize/X86/
H A Dpr35432.ll37 ; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i8
39 ; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[CONV3]], -1
48 ; CHECK-NEXT: [[TMP8:%.*]] = add i8 [[CONV3]], -1
71 ; CHECK-NEXT: [[IND_END:%.*]] = sub i8 [[CONV3]], [[CAST_CRD]]
79 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i8 [[CONV3]], [[TMP23]]
97 …L:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]…
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/LoopVectorize/X86/
H A Dpr35432.ll37 ; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i8
39 ; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[CONV3]], -1
47 ; CHECK-NEXT: [[TMP7:%.*]] = add i8 [[CONV3]], -1
69 ; CHECK-NEXT: [[IND_END:%.*]] = sub i8 [[CONV3]], [[CAST_CRD]]
77 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i8 [[CONV3]], [[TMP21]]
95 …L:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]…
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/LoopVectorize/X86/
H A Dpr35432.ll37 ; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i8
39 ; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[CONV3]], -1
48 ; CHECK-NEXT: [[TMP8:%.*]] = add i8 [[CONV3]], -1
71 ; CHECK-NEXT: [[IND_END:%.*]] = sub i8 [[CONV3]], [[CAST_CRD]]
79 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i8 [[CONV3]], [[TMP23]]
97 …L:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]…
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/LoopVectorize/X86/
H A Dpr35432.ll37 ; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i8
39 ; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[CONV3]], -1
47 ; CHECK-NEXT: [[TMP7:%.*]] = add i8 [[CONV3]], -1
69 ; CHECK-NEXT: [[IND_END:%.*]] = sub i8 [[CONV3]], [[CAST_CRD]]
77 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i8 [[CONV3]], [[TMP21]]
95 …L:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]…
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/LoopVectorize/X86/
H A Dpr35432.ll37 ; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i8
39 ; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[CONV3]], -1
47 ; CHECK-NEXT: [[TMP7:%.*]] = add i8 [[CONV3]], -1
69 ; CHECK-NEXT: [[IND_END:%.*]] = sub i8 [[CONV3]], [[CAST_CRD]]
77 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i8 [[CONV3]], [[TMP21]]
95 …L:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]…
/dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/LoopVectorize/X86/
H A Dpr35432.ll37 ; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[STOREMERGE_IN9]] to i8
39 ; CHECK-NEXT: [[TMP3:%.*]] = add i8 [[CONV3]], -1
48 ; CHECK-NEXT: [[TMP8:%.*]] = add i8 [[CONV3]], -1
71 ; CHECK-NEXT: [[IND_END:%.*]] = sub i8 [[CONV3]], [[CAST_CRD]]
79 ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i8 [[CONV3]], [[TMP23]]
105 …L:%.*]] = phi i8 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[CONV3]], [[FOR_BODY8_LR_PH]] ], [ [[CONV3]…

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