/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/TableGen/ |
H A D | directive2.td | 83 // IMPL-EMPTY: 86 // IMPL-EMPTY: 88 // IMPL-EMPTY: 93 // IMPL-EMPTY: 96 // IMPL-EMPTY: 99 // IMPL-EMPTY: 104 // IMPL-EMPTY: 106 // IMPL-EMPTY: 109 // IMPL-EMPTY: 120 // IMPL-EMPTY: [all …]
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H A D | directive1.td | 105 // IMPL-EMPTY: 108 // IMPL-EMPTY: 110 // IMPL-EMPTY: 115 // IMPL-EMPTY: 118 // IMPL-EMPTY: 121 // IMPL-EMPTY: 126 // IMPL-EMPTY: 128 // IMPL-EMPTY: 131 // IMPL-EMPTY: 142 // IMPL-EMPTY: [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/TableGen/ |
H A D | directive2.td | 83 // IMPL-EMPTY: 86 // IMPL-EMPTY: 88 // IMPL-EMPTY: 93 // IMPL-EMPTY: 96 // IMPL-EMPTY: 99 // IMPL-EMPTY: 104 // IMPL-EMPTY: 106 // IMPL-EMPTY: 109 // IMPL-EMPTY: 120 // IMPL-EMPTY: [all …]
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H A D | directive1.td | 105 // IMPL-EMPTY: 108 // IMPL-EMPTY: 110 // IMPL-EMPTY: 115 // IMPL-EMPTY: 118 // IMPL-EMPTY: 121 // IMPL-EMPTY: 126 // IMPL-EMPTY: 128 // IMPL-EMPTY: 131 // IMPL-EMPTY: 142 // IMPL-EMPTY: [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/TableGen/ |
H A D | directive2.td | 83 // IMPL-EMPTY: 86 // IMPL-EMPTY: 88 // IMPL-EMPTY: 93 // IMPL-EMPTY: 96 // IMPL-EMPTY: 99 // IMPL-EMPTY: 104 // IMPL-EMPTY: 106 // IMPL-EMPTY: 109 // IMPL-EMPTY: 120 // IMPL-EMPTY: [all …]
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H A D | directive1.td | 105 // IMPL-EMPTY: 108 // IMPL-EMPTY: 110 // IMPL-EMPTY: 115 // IMPL-EMPTY: 118 // IMPL-EMPTY: 121 // IMPL-EMPTY: 126 // IMPL-EMPTY: 128 // IMPL-EMPTY: 131 // IMPL-EMPTY: 142 // IMPL-EMPTY: [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/TableGen/ |
H A D | directive2.td | 83 // IMPL-EMPTY: 86 // IMPL-EMPTY: 88 // IMPL-EMPTY: 93 // IMPL-EMPTY: 96 // IMPL-EMPTY: 99 // IMPL-EMPTY: 104 // IMPL-EMPTY: 106 // IMPL-EMPTY: 109 // IMPL-EMPTY: 120 // IMPL-EMPTY: [all …]
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H A D | directive1.td | 105 // IMPL-EMPTY: 108 // IMPL-EMPTY: 110 // IMPL-EMPTY: 115 // IMPL-EMPTY: 118 // IMPL-EMPTY: 121 // IMPL-EMPTY: 126 // IMPL-EMPTY: 128 // IMPL-EMPTY: 131 // IMPL-EMPTY: 142 // IMPL-EMPTY: [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/TableGen/ |
H A D | directive2.td | 83 // IMPL-EMPTY: 86 // IMPL-EMPTY: 88 // IMPL-EMPTY: 93 // IMPL-EMPTY: 96 // IMPL-EMPTY: 99 // IMPL-EMPTY: 104 // IMPL-EMPTY: 106 // IMPL-EMPTY: 109 // IMPL-EMPTY: 120 // IMPL-EMPTY: [all …]
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H A D | directive1.td | 105 // IMPL-EMPTY: 108 // IMPL-EMPTY: 110 // IMPL-EMPTY: 115 // IMPL-EMPTY: 118 // IMPL-EMPTY: 121 // IMPL-EMPTY: 126 // IMPL-EMPTY: 128 // IMPL-EMPTY: 131 // IMPL-EMPTY: 142 // IMPL-EMPTY: [all …]
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/dports/emulators/qemu60/qemu-6.0.0/include/tcg/ |
H A D | tcg-opc.h | 63 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 64 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 65 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 66 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 76 DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) 101 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 102 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 155 IMPL(TCG_TARGET_HAS_extrl_i64_i32) 158 IMPL(TCG_TARGET_HAS_extrh_i64_i32) 215 IMPL(TCG_TARGET_HAS_qemu_st8_i32)) [all …]
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/dports/emulators/qemu/qemu-6.2.0/include/tcg/ |
H A D | tcg-opc.h | 63 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 64 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 65 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 66 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 76 DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) 101 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 102 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 155 IMPL(TCG_TARGET_HAS_extrl_i64_i32) 158 IMPL(TCG_TARGET_HAS_extrh_i64_i32) 214 IMPL(TCG_TARGET_HAS_qemu_st8_i32)) [all …]
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/dports/emulators/qemu5/qemu-5.2.0/include/tcg/ |
H A D | tcg-opc.h | 64 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 65 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 66 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 67 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 77 DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) 102 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 103 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 105 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) 157 IMPL(TCG_TARGET_HAS_extrl_i64_i32) 160 IMPL(TCG_TARGET_HAS_extrh_i64_i32) [all …]
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/tcg/ |
H A D | tcg-opc.h | 63 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 64 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 65 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 66 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 76 DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) 101 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 102 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 155 IMPL(TCG_TARGET_HAS_extrl_i64_i32) 158 IMPL(TCG_TARGET_HAS_extrh_i64_i32) 214 IMPL(TCG_TARGET_HAS_qemu_st8_i32)) [all …]
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/dports/emulators/qemu-utils/qemu-4.2.1/tcg/ |
H A D | tcg-opc.h | 64 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 65 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 66 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 67 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 101 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 102 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 104 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) 105 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) 156 IMPL(TCG_TARGET_HAS_extrl_i64_i32) 159 IMPL(TCG_TARGET_HAS_extrh_i64_i32) [all …]
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/dports/emulators/qemu42/qemu-4.2.1/tcg/ |
H A D | tcg-opc.h | 64 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 65 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 66 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 67 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 101 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 102 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 104 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) 105 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) 156 IMPL(TCG_TARGET_HAS_extrl_i64_i32) 159 IMPL(TCG_TARGET_HAS_extrh_i64_i32) [all …]
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/tcg/ |
H A D | tcg-opc.h | 64 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 65 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 66 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 67 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 101 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 102 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 104 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) 105 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) 156 IMPL(TCG_TARGET_HAS_extrl_i64_i32) 159 IMPL(TCG_TARGET_HAS_extrh_i64_i32) [all …]
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/tcg/ |
H A D | tcg-opc.h | 64 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 65 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 66 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 67 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 101 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 102 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 104 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) 105 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) 156 IMPL(TCG_TARGET_HAS_extrl_i64_i32) 159 IMPL(TCG_TARGET_HAS_extrh_i64_i32) [all …]
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/ |
H A D | tcg-opc.h | 64 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 65 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 66 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 67 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 100 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 101 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 103 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) 104 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) 154 IMPL(TCG_TARGET_HAS_extrl_i64_i32) 157 IMPL(TCG_TARGET_HAS_extrh_i64_i32) [all …]
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/dports/misc/py-cinder/cinder-12.0.10/cinder/db/ |
H A D | api.py | 69 IMPL = oslo_db_api.DBAPI.from_config(conf=CONF, variable 87 if 'sqlite' not in IMPL.get_engine().name: 88 return IMPL.dispose_engine() 146 return IMPL.service_create(context, values) 234 return IMPL.cluster_destroy(context, id) 242 return IMPL.volume_attach(context, values) 1178 return IMPL.reservation_expire(context) 1269 return IMPL.transfer_get_all(context) 1341 return IMPL.cg_has_cgsnapshot_filter() 1730 return IMPL.workers_init() [all …]
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/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/tcg/ |
H A D | tcg-opc.h | 76 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 77 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 78 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 79 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 110 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 111 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 113 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) 114 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) 116 DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32)) 156 IMPL(TCG_TARGET_HAS_trunc_shr_i32) [all …]
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/dports/emulators/unicorn/unicorn-1.0.2/qemu/tcg/ |
H A D | tcg-opc.h | 76 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 77 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 78 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 79 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 110 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 111 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 113 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) 114 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) 116 DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32)) 156 IMPL(TCG_TARGET_HAS_trunc_shr_i32) [all …]
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/dports/science/simbody/simbody-Simbody-3.7/SimTKcommon/include/SimTKcommon/internal/ |
H A D | PrivateImplementation_Defs.h | 52 template <class HANDLE, class IMPL> 56 template <class HANDLE, class IMPL> 61 template <class HANDLE, class IMPL> 66 template <class HANDLE, class IMPL> 71 template <class HANDLE, class IMPL> 76 template <class HANDLE, class IMPL> 129 PIMPLHandle(IMPL* p) : impl(p) { in PIMPLHandle() 150 PIMPLHandle<HANDLE,IMPL,PTR>& PIMPLHandle<HANDLE,IMPL,PTR>:: 192 PIMPLHandle<HANDLE,IMPL,PTR>& PIMPLHandle<HANDLE,IMPL,PTR>:: 209 PIMPLHandle<HANDLE,IMPL,PTR>& PIMPLHandle<HANDLE,IMPL,PTR>:: [all …]
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/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/frv/ |
H A D | registers.c | 27 #define IMPL 1 /* Implemented */ macro 50 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 51 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 52 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 53 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 54 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 55 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 57 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 58 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 59 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, [all …]
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/dports/devel/avr-gdb/gdb-7.3.1/sim/frv/ |
H A D | registers.c | 27 #define IMPL 1 /* Implemented */ macro 50 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 51 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 52 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 53 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 54 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 55 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 57 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 58 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, 59 {0x00000000, 0x00000000, 0xffffffff, 0x00000000, IMPL, SUP}, [all …]
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