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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dreduction.ll212 ; GFX9-NEXT: v_pk_min_u16 [[MIN3:v[0-9]+]], [[MIN2]], [[MIN1]]{{$}}
213 ; GFX9-NEXT: v_min_u16_sdwa v{{[0-9]+}}, [[MIN3]], [[MIN3]] dst_sel:DWORD dst_unused:UNUSED_PAD src…
/dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
679 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
680 ; VI-NEXT: ret half [[MIN3]]
/dports/devel/ode/ode-0.13/GIMPACT/include/GIMPACT/
H A Dgim_geometry.h1397 (aabb).minX = MIN3(V1[0],V2[0],V3[0]);\
1399 (aabb).minY = MIN3(V1[1],V2[1],V3[1]);\
1401 (aabb).minZ = MIN3(V1[2],V2[2],V3[2]);\
H A Dgim_math.h106 #define MIN3(a,b,c) MIN(a,MIN(b,c)) macro
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dreduction.ll212 ; GFX9-NEXT: v_pk_min_u16 [[MIN3:v[0-9]+]], [[MIN2]], [[MIN1]]{{$}}
213 ; GFX9-NEXT: v_min_u16_sdwa v{{[0-9]+}}, [[MIN3]], [[MIN3]] dst_sel:DWORD dst_unused:UNUSED_PAD src…
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
679 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
680 ; VI-NEXT: ret half [[MIN3]]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreduction.ll212 ; GFX9-NEXT: v_pk_min_u16 [[MIN3:v[0-9]+]], [[MIN2]], [[MIN1]]{{$}}
213 ; GFX9-NEXT: v_min_u16_sdwa v{{[0-9]+}}, [[MIN3]], [[MIN3]] dst_sel:DWORD dst_unused:UNUSED_PAD src…
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
661 ; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
662 ; GCN-NEXT: ret half [[MIN3]]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreduction.ll212 ; GFX9-NEXT: v_pk_min_u16 [[MIN3:v[0-9]+]], [[MIN2]], [[MIN1]]{{$}}
213 ; GFX9-NEXT: v_min_u16_sdwa v{{[0-9]+}}, [[MIN3]], [[MIN3]] dst_sel:DWORD dst_unused:UNUSED_PAD src…
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll278 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
279 ; VI-NEXT: ret i16 [[MIN3]]
318 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
319 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
320 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
388 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
389 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
390 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
594 ; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
595 ; GCN-NEXT: ret half [[MIN3]]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dreduction.ll212 ; GFX9-NEXT: v_pk_min_u16 [[MIN3:v[0-9]+]], [[MIN2]], [[MIN1]]{{$}}
213 ; GFX9-NEXT: v_min_u16_sdwa v{{[0-9]+}}, [[MIN3]], [[MIN3]] dst_sel:DWORD dst_unused:UNUSED_PAD src…
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll278 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
279 ; VI-NEXT: ret i16 [[MIN3]]
318 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
319 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
320 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
388 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
389 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
390 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
594 ; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
595 ; GCN-NEXT: ret half [[MIN3]]
/dports/editors/libreoffice/libreoffice-7.2.6.2/lotuswordpro/inc/xfilter/
H A Dxfglobal.hxx71 #define MIN3(a, b, c) MIN2(a, MIN2(b, c)) macro
/dports/editors/libreoffice6/libreoffice-6.4.7.2/lotuswordpro/inc/xfilter/
H A Dxfglobal.hxx81 #define MIN3(a,b,c) MIN2(a,MIN2(b,c)) macro
/dports/emulators/mame/mame-mame0226/3rdparty/bgfx/3rdparty/glsl-optimizer/src/mesa/main/
H A Dmacros.h681 #define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C))
/dports/emulators/mame/mame-mame0226/3rdparty/bimg/3rdparty/astc/
H A Dastc_kmeans_partitioning.cpp340 static inline int MIN3(int a, int b, int c) in MIN3() function
376 int v0 = p00 + MIN3(p11 + mx23, p12 + mx13, p13 + mx12); in partition_mismatch4()
377 int v1 = p01 + MIN3(p10 + mx23, p12 + mx03, p13 + mx02); in partition_mismatch4()
378 int v2 = p02 + MIN3(p11 + mx03, p10 + mx13, p13 + mx01); in partition_mismatch4()
379 int v3 = p03 + MIN3(p11 + mx02, p12 + mx01, p10 + mx12); in partition_mismatch4()
/dports/emulators/mess/mame-mame0226/3rdparty/bgfx/3rdparty/glsl-optimizer/src/mesa/main/
H A Dmacros.h681 #define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C))
/dports/emulators/mess/mame-mame0226/3rdparty/bimg/3rdparty/astc/
H A Dastc_kmeans_partitioning.cpp340 static inline int MIN3(int a, int b, int c) in MIN3() function
376 int v0 = p00 + MIN3(p11 + mx23, p12 + mx13, p13 + mx12); in partition_mismatch4()
377 int v1 = p01 + MIN3(p10 + mx23, p12 + mx03, p13 + mx02); in partition_mismatch4()
378 int v2 = p02 + MIN3(p11 + mx03, p10 + mx13, p13 + mx01); in partition_mismatch4()
379 int v3 = p03 + MIN3(p11 + mx02, p12 + mx01, p10 + mx12); in partition_mismatch4()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/hexagon/imported/
H A Dencode_pp.def1438 #define SH_RRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1441 #define SH_RRRiENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1447 #define SH3_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1450 #define SH_PPP_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1453 #define SH2_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1459 #define SH_RRI4_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \
1462 #define SH_RRI5_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \
1465 #define SH_RRI6_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \
1475 #define I5SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \
1491 #define I4SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \
[all …]
/dports/emulators/qemu/qemu-6.2.0/target/hexagon/imported/
H A Dencode_pp.def1438 #define SH_RRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1441 #define SH_RRRiENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1447 #define SH3_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1450 #define SH_PPP_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1453 #define SH2_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1459 #define SH_RRI4_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \
1462 #define SH_RRI5_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \
1465 #define SH_RRI6_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \
1475 #define I5SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \
1491 #define I4SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \
[all …]
/dports/emulators/qemu/qemu-6.2.0/target/hexagon/imported/mmvec/
H A Dencode_ext.def67 …fine LDST_ENC(TAG,MAJ3,MID3,RREG,TINY6,MIN3,VREG) DEF_ENC(TAG, ICLASS_NCJ "1" #MAJ3 #MID3 #RREG "P…
69 #define LDST_BO(TAGPRE,MID3,PRED,MIN3,VREG) LDST_ENC(TAGPRE##_ai, 000,MID3,ttttt,i PRED iii,MIN3,VR…
70 #define LDST_PI(TAGPRE,MID3,PRED,MIN3,VREG) LDST_ENC(TAGPRE##_pi, 001,MID3,xxxxx,- PRED iii,MIN3,VR…
71 #define LDST_PM(TAGPRE,MID3,PRED,MIN3,VREG) LDST_ENC(TAGPRE##_ppu,011,MID3,xxxxx,u PRED ---,MIN3,VR…
/dports/emulators/qemu60/qemu-6.0.0/target/hexagon/imported/
H A Dencode_pp.def1409 #define SH_RRR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1412 #define SH_RRRiENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1418 #define SH3_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1421 #define SH_PPP_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1424 #define SH2_RR_ENC(TAG,MAJ4,MIN3,SMOD1,VMIN3,DSTCHARS) \
1430 #define SH_RRI4_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \
1433 #define SH_RRI5_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \
1436 #define SH_RRI6_ENC(TAG,MAJ4,MIN3,VMIN3,DSTCHARS) \
1446 #define I5SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \
1462 #define I4SHIFTTYPES(TAGEND,MAJ4,MIN3,SMOD1,DSTCHARS) \
[all …]
/dports/games/libretro-scummvm/scummvm-7b1e929/backends/fs/psp/
H A Dpsp-stream.cpp30 #define MIN3(a,b,c) ( (a < b) ? (a < c ? a : c) : (b < c ? b : c) ) macro
/dports/games/magiccube4d/magiccube4d-src-2_2/
H A DMagicCube.h101 #define MIN3(a,b,c) ((a)<(b) ? MIN(a,c) : MIN(b,c)) macro
103 #define MIN4(a,b,c,d) ((a)<(b) ? MIN3(a,c,d) : MIN3(b,c,d))
/dports/games/scummvm/scummvm-2.5.1/backends/fs/psp/
H A Dpsp-stream.cpp30 #define MIN3(a,b,c) ( (a < b) ? (a < c ? a : c) : (b < c ? b : c) ) macro

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