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Searched refs:NUM_CHANNELS (Results 1 – 25 of 829) sorted by relevance

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/dports/audio/eq10q-lv2/eq10q-2.2/
H A Deq.c61 #if NUM_CHANNELS == 2
188 …if(port >= (PORT_OFFSET + 2*NUM_CHANNELS + 5*NUM_BANDS) && port < (PORT_OFFSET + 2*NUM_CHANNELS + … in connectPortEQ()
194 …>= (PORT_OFFSET + 2*NUM_CHANNELS + 5*NUM_BANDS + NUM_CHANNELS) && port < (PORT_OFFSET + 2*NUM_CHAN… in connectPortEQ()
200 else if(port == PORT_OFFSET + 2*NUM_CHANNELS + 5*NUM_BANDS + 2*NUM_CHANNELS) in connectPortEQ()
239 #if NUM_CHANNELS == 2 in instantiateEQ()
304 #if NUM_CHANNELS == 2 in runEQ_v2()
322 #if NUM_CHANNELS == 2 in runEQ_v2()
344 #if NUM_CHANNELS == 2 in runEQ_v2()
417 #if NUM_CHANNELS == 2 in runEQ_v2()
428 #if NUM_CHANNELS == 2 in runEQ_v2()
[all …]
/dports/comms/hamlib/hamlib-4.3.1/rotators/ts7400/include/
H A Dtest7400ADC.c15 #define NUM_CHANNELS 4 macro
33 int read_calibration(int buf[NUM_CHANNELS][2]) in read_calibration()
36 unsigned short cal[NUM_CHANNELS * 2]; in read_calibration()
57 if (k < NUM_CHANNELS * 2) in read_calibration()
85 for (i = 0; i < NUM_CHANNELS; i++) in write_calibration()
220 for (i = 0; i < NUM_CHANNELS; i++) in calc_calibration()
227 for (i = 0; i < NUM_CHANNELS; i++) in calc_calibration()
243 for (i = 0; i < NUM_CHANNELS; i++) in calc_calibration()
298 for (i = 0; i < NUM_CHANNELS; i++) in read_7xxx_adc()
354 for (i = 0; i < NUM_CHANNELS; i++) in test_ADC()
[all …]
H A DreadADC.c16 #define NUM_CHANNELS 4 macro
35 int read_calibration(int buf[NUM_CHANNELS][2]) in read_calibration()
38 unsigned short cal[NUM_CHANNELS * 2]; in read_calibration()
59 if (k < NUM_CHANNELS * 2) in read_calibration()
87 for (i = 0; i < NUM_CHANNELS; i++) in write_calibration()
222 for (i = 0; i < NUM_CHANNELS; i++) in calc_calibration()
229 for (i = 0; i < NUM_CHANNELS; i++) in calc_calibration()
245 for (i = 0; i < NUM_CHANNELS; i++) in calc_calibration()
295 for (i = 0; i < NUM_CHANNELS; i++) in read_7xxx_adc()
360 for (i = 0; i < NUM_CHANNELS; i++) in test_ADC()
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/
H A De31x_core.v24 parameter NUM_CHANNELS = 2, constant
86 output wire [32*NUM_CHANNELS-1:0] leds_flat,
89 output wire [NUM_CHANNELS-1:0] rx_atr,
90 output wire [NUM_CHANNELS-1:0] tx_atr,
93 input wire [NUM_CHANNELS-1:0] rx_stb,
94 input wire [NUM_CHANNELS-1:0] tx_stb,
95 input wire [32*NUM_CHANNELS-1:0] rx,
96 output wire [32*NUM_CHANNELS-1:0] tx,
481 wire [31:0] leds[0:NUM_CHANNELS-1];
484 wire rx_running[0:NUM_CHANNELS-1], tx_running[0:NUM_CHANNELS-1];
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
H A Dmrc.h18 #define NUM_CHANNELS 1 // number of channels
58 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
59 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
60 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
61 uint32_t wdq [NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
62 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
63 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
64 uint32_t wcmd[NUM_CHANNELS];
140 uint32_t channel_size[NUM_CHANNELS];
141 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/x86/include/asm/arch-quark/
H A Dmrc.h16 #define NUM_CHANNELS 1 /* number of channels */ macro
75 uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
76 uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
77 uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
78 uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
79 uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
80 uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
81 uint32_t wcmd[NUM_CHANNELS];
143 uint32_t channel_size[NUM_CHANNELS];
144 uint32_t column_bits[NUM_CHANNELS];
[all …]

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