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Searched refs:RD4 (Results 1 – 25 of 84) sorted by relevance

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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c1007 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); in usb3_port_init()
1051 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init()
1056 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init()
1061 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init()
1079 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_enable()
1091 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_disable()
1111 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_enable()
1123 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_disable()
1275 reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP); in usb2_enable()
1379 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in pad_common_enable()
[all …]
H A Dtegra210_pmc.c234 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra210_pmc_set_powergate()
274 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_remove_clamping()
295 reg = RD4(sc, PMC_CLAMP_STATUS); in tegra_powergate_remove_clamping()
310 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_is_powered()
505 orig = RD4(sc, PMC_SCRATCH0); in tegra210_pmc_check_secure()
507 if (RD4(sc, PMC_SCRATCH0) == 0) { in tegra210_pmc_check_secure()
512 if (RD4(sc, PMC_SCRATCH0) == 0) { in tegra210_pmc_check_secure()
577 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach()
582 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach()
590 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach()
[all …]
H A Dtegra210_clk_pll.c603 RD4(sc, sc->base_reg, &reg); in pll_enable()
616 RD4(sc, sc->base_reg, &reg); in pll_disable()
688 RD4(sc, sc->base_reg, &val); in get_divisors()
758 RD4(sc, sc->base_reg, &reg); in plle_enable()
763 RD4(sc, PLLE_AUX, &reg); in plle_enable()
817 RD4(sc, PLLE_AUX, &reg); in plle_enable()
1162 RD4(sc, PLLX_MISC_2, &reg); in pllx_set_freq()
1167 RD4(sc, PLLX_MISC_2, &reg); in pllx_set_freq()
1173 RD4(sc, PLLX_MISC_2, &reg); in pllx_set_freq()
1196 RD4(sc, PLLX_MISC_2, &reg); in pllx_set_freq()
[all …]
/freebsd/sys/arm/nvidia/
H A Dtegra_efuse.c194 sku->sku_id = RD4(sc, TEGRA124_FUSE_SKU_INFO); in tegra124_init()
284 reg = RD4(sc, TEGRA210_FUSE_SPARE + 2 * 4); in tegra210_get_speedo_revision()
286 reg = RD4(sc, TEGRA210_FUSE_SPARE + 3 * 4); in tegra210_get_speedo_revision()
288 reg = RD4(sc, TEGRA210_FUSE_SPARE + 4 * 4); in tegra210_get_speedo_revision()
335 cpu_speedo[0] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_0); in tegra210_init()
336 cpu_speedo[1] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_1); in tegra210_init()
337 cpu_speedo[2] = RD4(sc, TEGRA210_FUSE_CPU_SPEEDO_2); in tegra210_init()
338 soc_speedo[0] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_0); in tegra210_init()
339 soc_speedo[1] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_1); in tegra210_init()
340 soc_speedo[2] = RD4(sc, TEGRA210_FUSE_SOC_SPEEDO_2); in tegra210_init()
[all …]
H A Dtegra_usbphy.c306 #define RD4(sc, offs) \ macro
354 val = RD4(sc, IF_USB_SUSP_CTRL); in usbphy_utmi_enable()
358 val = RD4(sc, UTMIP_TX_CFG0); in usbphy_utmi_enable()
362 val = RD4(sc, UTMIP_HSRX_CFG0); in usbphy_utmi_enable()
369 val = RD4(sc, UTMIP_HSRX_CFG1); in usbphy_utmi_enable()
379 val = RD4(sc, UTMIP_MISC_CFG0); in usbphy_utmi_enable()
432 val = RD4(sc, UTMIP_XCVR_CFG0); in usbphy_utmi_enable()
453 val = RD4(sc, UTMIP_XCVR_CFG1); in usbphy_utmi_enable()
461 val = RD4(sc, UTMIP_BIAS_CFG1); in usbphy_utmi_enable()
523 val = RD4(sc, UTMIP_XCVR_CFG0); in usbphy_utmi_disable()
[all …]
H A Dtegra_i2c.c242 reg = RD4(sc, I2C_FIFO_CONTROL); in tegra_i2c_flush_fifo()
248 reg = RD4(sc, I2C_FIFO_CONTROL); in tegra_i2c_flush_fifo()
290 if (RD4(sc, I2C_CONFIG_LOAD) == 0) in tegra_i2c_bus_clear()
296 reg = RD4(sc, I2C_BUS_CLEAR_CONFIG); in tegra_i2c_bus_clear()
301 if ((RD4(sc, I2C_BUS_CLEAR_CONFIG) & in tegra_i2c_bus_clear()
309 status = RD4(sc, I2C_BUS_CLEAR_STATUS); in tegra_i2c_bus_clear()
344 if (RD4(sc, I2C_CONFIG_LOAD) == 0) in tegra_i2c_hw_init()
365 reg = RD4(sc, I2C_FIFO_STATUS); in tegra_i2c_tx()
391 reg = RD4(sc, I2C_FIFO_STATUS); in tegra_i2c_rx()
395 reg = RD4(sc, I2C_RX_FIFO); in tegra_i2c_rx()
[all …]
H A Dtegra_soctherm.c132 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
546 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0), in soctherm_init_tsensor()
547 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG1), in soctherm_init_tsensor()
548 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG2), in soctherm_init_tsensor()
549 RD4(sc, sensor->sensor_base + TSENSOR_STATUS0), in soctherm_init_tsensor()
550 RD4(sc, sensor->sensor_base + TSENSOR_STATUS1), in soctherm_init_tsensor()
551 RD4(sc, sensor->sensor_base + TSENSOR_STATUS2) in soctherm_init_tsensor()
590 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG0), in soctherm_read_temp()
591 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG1), in soctherm_read_temp()
592 RD4(sc, sensor->sensor_base + TSENSOR_CONFIG2), in soctherm_read_temp()
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c255 val = RD4(sc, off & ~3); in RD2()
266 val = RD4(sc, off & ~3); in RD1()
276 val32 = RD4(sc, off & ~3); in WR2()
287 val32 = RD4(sc, off & ~3); in WR1()
302 RD4(sc, HC_COMMAND)); in bcm_sdhost_print_regs()
304 RD4(sc, HC_ARGUMENT)); in bcm_sdhost_print_regs()
320 RD4(sc, HC_POWER)); in bcm_sdhost_print_regs()
322 RD4(sc, HC_DEBUG)); in bcm_sdhost_print_regs()
357 dbg = RD4(sc, HC_DEBUG); in bcm_sdhost_reset()
564 cmd = RD4(sc, HC_COMMAND); in bcm_sdhost_intr()
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_ccm.c66 RD4(struct ccm_softc *sc, bus_size_t off) in RD4() function
177 reg = RD4(sc, CCM_CGPR); in ccm_attach()
180 reg = RD4(sc, CCM_CLPCR); in ccm_attach()
224 reg = RD4(sc, CCM_CSCMR1); in imx_ccm_ssi_configure()
239 reg = RD4(sc, CCM_CS1CDR); in imx_ccm_ssi_configure()
253 reg = RD4(sc, CCM_CS2CDR); in imx_ccm_ssi_configure()
328 v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET); in imx6_ccm_sata_enable()
448 reg = RD4(sc, CCM_CCGR3); in imx_ccm_ipu_enable()
456 reg = RD4(sc, CCM_CHSCCDR); in imx_ccm_ipu_enable()
481 reg = RD4(sc, CCM_CCGR2); in imx_ccm_hdmi_enable()
[all …]
H A Dimx6_snvs.c80 RD4(struct snvs_softc *sc, bus_size_t offset) in RD4() function
106 while ((RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV) != enbit) in snvs_rtc_enable()
119 if (!(RD4(sc, SNVS_LPCR) & LPCR_SRTC_ENV)) { in snvs_gettime()
131 counter1 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); in snvs_gettime()
132 counter1 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB); in snvs_gettime()
133 counter2 = (uint64_t)RD4(sc, SNVS_LPSRTCMR) << (SBT_LSB + 32); in snvs_gettime()
134 counter2 |= (uint64_t)RD4(sc, SNVS_LPSRTCLR) << (SBT_LSB); in snvs_gettime()
/freebsd/sys/dev/sdhci/
H A Dsdhci_fsl_fdt.c56 #define RD4 (sc->read) macro
445 val32 = RD4(sc, off); in sdhci_fsl_fdt_read_4()
497 val32 = RD4(sc, off & ~3); in sdhci_fsl_fdt_write_1()
540 val32 = RD4(sc, off & ~3); in sdhci_fsl_fdt_write_2()
1130 reg = RD4(sc, SDHCI_FSL_TBCTL); in sdhci_fsl_switch_tuning_block()
1156 reg = RD4(sc, SDHCI_FSL_TBPTR); in sdhci_fsl_sw_tuning()
1174 reg = RD4(sc, SDHCI_FSL_TBCTL); in sdhci_fsl_sw_tuning()
1246 reg = RD4(sc, SDHCI_FSL_TBCTL); in sdhci_fsl_fdt_tune()
1264 reg = RD4(sc, SDHCI_FSL_TBPTR); in sdhci_fsl_fdt_tune()
1341 reg = RD4(sc, SDHCI_FSL_TBCTL); in sdhci_fsl_disable_hs400_mode()
[all …]
H A Dfsl_sdhci.c215 wrk32 = RD4(sc, SDHC_PROT_CTRL); in fsl_sdhci_read_1()
298 val32 = RD4(sc, SDHCI_INT_STATUS); in fsl_sdhci_read_2()
299 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); in fsl_sdhci_read_2()
320 val32 = RD4(sc, off); in fsl_sdhci_read_4()
388 val32 = RD4(sc, SDHC_PROT_CTRL); in fsl_sdhci_write_1()
412 val32 = RD4(sc, off & ~3); in fsl_sdhci_write_1()
451 val32 = RD4(sc, USDHC_MIX_CONTROL); in fsl_sdhci_write_2()
472 val32 = RD4(sc, USDHC_MIX_CONTROL); in fsl_sdhci_write_2()
492 val32 = RD4(sc, off & ~3); in fsl_sdhci_write_2()
572 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); in fsl_sdhc_set_clock()
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c368 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); in usb3_port_init()
389 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); in usb3_port_init()
394 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); in usb3_port_init()
399 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); in usb3_port_init()
440 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_powerup()
452 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_powerdown()
499 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_powerup()
503 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_powerup()
515 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_powerdown()
644 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM); in phy_powerup()
[all …]
H A Dtegra124_clk_pll.c417 RD4(sc, sc->base_reg, &reg); in pll_enable()
430 RD4(sc, sc->base_reg, &reg); in pll_disable()
495 RD4(sc, sc->base_reg, &val); in get_divisors()
566 RD4(sc, sc->base_reg, &reg); in plle_enable()
570 RD4(sc, PLLE_AUX, &reg); in plle_enable()
576 RD4(sc, sc->misc_reg, &reg); in plle_enable()
586 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
590 RD4(sc, sc->base_reg, &reg); in plle_enable()
602 RD4(sc, PLLE_SS_CNTL, &reg); in plle_enable()
618 RD4(sc, sc->misc_reg, &reg); in plle_enable()
[all …]
H A Dtegra124_pmc.c198 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra124_pmc_set_powergate()
211 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra124_pmc_set_powergate()
238 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_remove_clamping()
251 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD); in tegra_powergate_remove_clamping()
259 reg = RD4(sc, PMC_CLAMP_STATUS); in tegra_powergate_remove_clamping()
274 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_is_powered()
512 reg = RD4(sc, PMC_CNTRL); in tegra124_pmc_attach()
517 reg = RD4(sc, PMC_CNTRL); in tegra124_pmc_attach()
525 reg = RD4(sc, PMC_CNTRL); in tegra124_pmc_attach()
533 reg = RD4(sc, PMC_IO_DPD_STATUS); in tegra124_pmc_attach()
[all …]
/freebsd/sys/dev/cadence/
H A Dif_cgem.c251 uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i)); in cgem_get_mac()
384 queue_mask = (RD4(sc, CGEM_DESIGN_CFG6) & in cgem_null_qs()
896 n = RD4(sc, CGEM_SINGLE_COLL_FRAMES); in cgem_poll_hw_stats()
899 n = RD4(sc, CGEM_MULTI_COLL_FRAMES); in cgem_poll_hw_stats()
902 n = RD4(sc, CGEM_EXCESSIVE_COLL_FRAMES); in cgem_poll_hw_stats()
905 n = RD4(sc, CGEM_LATE_COLL); in cgem_poll_hw_stats()
990 istatus = RD4(sc, CGEM_INTR_STAT); in cgem_intr()
1004 RD4(sc, CGEM_RX_STAT)); in cgem_intr()
1038 switch (RD4(sc, CGEM_DESIGN_CFG1) & in cgem_reset()
1290 RD4(sc, CGEM_DMA_CFG) | in cgem_ioctl()
[all …]
/freebsd/sys/arm/xilinx/
H A Dzy7_slcr.c137 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff); in zy7_slcr_cpu_reset()
271 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_set_source()
297 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_get_source()
361 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_set_freq()
410 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_get_freq()
490 reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit)); in zy7_pl_fclk_enabled()
507 reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN); in zy7_pl_level_shifters_enabled()
596 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE); in zy7_slcr_attach()
601 pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE); in zy7_slcr_attach()
626 arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL); in zy7_slcr_attach()
[all …]
H A Duart_dev_cdnc.c54 #define RD4(bas, reg) \ macro
333 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_putc()
339 while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_putc()
351 return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_rxready()
365 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_getc()
372 c = RD4(bas, CDNC_UART_FIFO); in cdnc_uart_getc()
515 status = RD4(bas, CDNC_UART_ISTAT_REG); in cdnc_uart_bus_receive()
525 while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) & in cdnc_uart_bus_receive()
527 c = RD4(bas, CDNC_UART_FIFO) & 0xff; in cdnc_uart_bus_receive()
563 istatus = RD4(bas, CDNC_UART_ISTAT_REG); in cdnc_uart_bus_ipend()
[all …]
H A Dzy7_gpio.c182 #define RD4(sc, off) bus_read_4((sc)->mem_res, (off)) macro
298 if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) { in zy7_gpio_pin_getflags()
300 if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0) in zy7_gpio_pin_getflags()
327 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31))); in zy7_gpio_pin_setflags()
331 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & in zy7_gpio_pin_setflags()
335 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) | in zy7_gpio_pin_setflags()
340 RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31))); in zy7_gpio_pin_setflags()
342 RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31))); in zy7_gpio_pin_setflags()
381 *value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1; in zy7_gpio_pin_get()
398 RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31))); in zy7_gpio_pin_toggle()
/freebsd/sys/dev/eqos/
H A Dif_eqos.c126 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); in eqos_miibus_readreg()
159 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); in eqos_miibus_writereg()
186 reg = RD4(sc, GMAC_MAC_CONFIGURATION); in eqos_miibus_statchg()
461 val = RD4(sc, GMAC_DMA_MODE); in eqos_reset()
508 val = RD4(sc, GMAC_DMA_CHAN0_CONTROL); in eqos_init()
543 val = RD4(sc, GMAC_MAC_RX_FLOW_CTRL); in eqos_init()
552 val = RD4(sc, GMAC_MAC_CONFIGURATION); in eqos_init()
639 val = RD4(sc, GMAC_MAC_CONFIGURATION); in eqos_stop()
861 RD4(sc, GMAC_DMA_CHAN0_STATUS)); in eqos_intr()
962 val = RD4(sc, GMAC_DMA_SYSBUS_MODE); in eqos_axi_configure()
[all …]
/freebsd/sys/dev/tpm/
H A Dtpm_crb.c190 crb_sc->rsp_off = RD4(sc, TPM_CRB_CTRL_RSP_ADDR); in tpmcrb_attach()
191 crb_sc->rsp_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_RSP_HADDR) << 32); in tpmcrb_attach()
193 crb_sc->cmd_off = RD4(sc, TPM_CRB_CTRL_CMD_LADDR); in tpmcrb_attach()
194 crb_sc->cmd_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_CMD_HADDR) << 32); in tpmcrb_attach()
195 crb_sc->cmd_buf_size = RD4(sc, TPM_CRB_CTRL_CMD_SIZE); in tpmcrb_attach()
196 crb_sc->rsp_buf_size = RD4(sc, TPM_CRB_CTRL_RSP_SIZE); in tpmcrb_attach()
251 if ((RD4(sc, off) & mask) == val) in tpm_wait_for_u32()
255 if ((RD4(sc, off) & mask) == val) in tpm_wait_for_u32()
323 if (RD4(sc, TPM_CRB_CTRL_STS) & TPM_CRB_CTRL_STS_ERR_BIT) { in tpmcrb_transmit()
337 if (!(RD4(sc, TPM_CRB_CTRL_STS) & TPM_CRB_CTRL_STS_IDLE_BIT)) { in tpmcrb_transmit()
H A Dtpm_tis.c228 reg = RD4(sc, TPM_INT_STS); in tpmtis_setup_intr()
231 reg = RD4(sc, TPM_INT_ENABLE); in tpmtis_setup_intr()
250 status = RD4(sc, TPM_INT_STS); in tpmtis_intr_handler()
268 if ((RD4(sc, off) & mask) == val) in tpm_wait_for_u32()
276 return ((RD4(sc, off) & mask) == val); in tpm_wait_for_u32()
281 if ((RD4(sc, off) & mask) == val) in tpm_wait_for_u32()
299 burst_count = (RD4(sc, TPM_STS) & TPM_STS_BURST_MASK) >> in tpmtis_wait_for_burst()
390 AND4(sc, TPM_INT_STS, RD4(sc, TPM_INT_STS)); in tpmtis_relinquish_locality()
443 if (RD4(sc, TPM_STS) & TPM_STS_DATA_EXPECTED) { in tpmtis_transmit()
/freebsd/sys/arm/mv/clk/
H A Da37x0_tbg_pll.c42 #define RD4(_clk, offset, val) \ macro
61 RD4(clk, sc->tbg_bypass.offset, &val); in a37x0_tbg_pll_recalc_freq()
65 RD4(clk, sc->vcodiv.offset, &val); in a37x0_tbg_pll_recalc_freq()
68 RD4(clk, sc->refdiv.offset, &val); in a37x0_tbg_pll_recalc_freq()
71 RD4(clk, sc->fbdiv.offset, &val); in a37x0_tbg_pll_recalc_freq()
/freebsd/sys/arm/mv/
H A Dmv_thermal.c121 #define RD4(sc, reg) \ macro
142 reg = RD4(sc, STATUS); in mv_thermal_wait_sensor()
163 reg = RD4(sc, CONTROL0); in mv_thermal_select_sensor()
185 reg = RD4(sc, CONTROL0); in mv_thermal_select_sensor()
202 reg = RD4(sc, STATUS) & STATUS_TEMP_MASK; in mv_thermal_read_sensor()
221 reg = RD4(sc, CONTROL0); in ap806_init()
241 reg = RD4(sc, CONTROL1); in cp110_init()
247 reg = RD4(sc, CONTROL0); in cp110_init()
/freebsd/sys/dev/ffec/
H A Dif_ffec.c482 mibc = RD4(sc, FEC_MIBC_REG); in ffec_clear_stats()
532 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) + in ffec_harvest_stats()
533 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) + in ffec_harvest_stats()
534 RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP)); in ffec_harvest_stats()
541 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) + in ffec_harvest_stats()
542 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) + in ffec_harvest_stats()
543 RD4(sc, FEC_RMON_T_JAB)); in ffec_harvest_stats()
949 palr = RD4(sc, FEC_PALR_REG); in ffec_get_hwaddr()
1229 regval = RD4(sc, FEC_MIBC_REG); in ffec_init_locked()
1251 regval = RD4(sc, FEC_ECR_REG); in ffec_init_locked()
[all …]

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