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Searched refs:RD4 (Results 26 – 50 of 84) sorted by relevance

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/freebsd/sys/dev/hwpmc/
H A Dpmu_dmc620.c69 #define RD4(sc, r) bus_read_4((sc)->sc_res[0], (r)) macro
71 #define MD4(sc, r, c, s) WR4((sc), (r), RD4((sc), (r)) & ~(c) | (s))
87 val = RD4(sc, DMC620_REG(cntr, reg)); in pmu_dmc620_rd4()
215 clkdiv2_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLKDIV2); in pmu_dmc620_counter_overflow_intr()
216 clk_stat = RD4(sc, DMC620_OVERFLOW_STATUS_CLK); in pmu_dmc620_counter_overflow_intr()
222 sc->sc_saved_control[i] = RD4(sc, DMC620_REG(i, in pmu_dmc620_counter_overflow_intr()
/freebsd/sys/arm64/broadcom/genet/
H A Dif_genet.c491 val = RD4(sc, GENET_RBUF_CTRL); in gen_enable()
498 val = RD4(sc, GENET_UMAC_CMD); in gen_enable()
523 val = RD4(sc, GENET_UMAC_CMD); in gen_disable()
528 val = RD4(sc, GENET_UMAC_CMD); in gen_disable()
567 val = RD4(sc, GENET_TX_DMA_CTRL); in gen_dma_disable()
572 val = RD4(sc, GENET_RX_DMA_CTRL); in gen_dma_disable()
954 cmd = RD4(sc, GENET_UMAC_CMD); in gen_setup_rxfilter()
1647 val = RD4(sc, GENET_MDIO_CMD); in gen_miibus_readreg()
1678 val = RD4(sc, GENET_MDIO_CMD); in gen_miibus_writereg()
1681 val = RD4(sc, GENET_MDIO_CMD); in gen_miibus_writereg()
[all …]
/freebsd/sys/arm/allwinner/
H A Daw_thermal.c374 #define RD4(sc, reg) bus_read_4((sc)->res[0], (reg)) macro
418 WR4(sc, THS_INTS, RD4(sc, THS_INTS)); in aw_thermal_init()
419 WR4(sc, THS_INTC, RD4(sc, THS_INTC) | SHUT_INT_ALL | ALARM_INT_ALL); in aw_thermal_init()
422 WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL); in aw_thermal_init()
432 val = RD4(sc, THS_DATA0 + (sensor * 4)); in aw_thermal_gettemp()
442 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4)); in aw_thermal_getshut()
453 val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4)); in aw_thermal_setshut()
464 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); in aw_thermal_gethyst()
475 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); in aw_thermal_getalarm()
486 val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4)); in aw_thermal_setalarm()
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H A Daw_usb3phy.c106 #define RD4(res, o) bus_read_4(res, (o)) macro
123 val = RD4(sc->res, USB3PHY_PHY_EXTERNAL_CONTROL); in awusb3phy_phy_enable()
131 val = RD4(sc->res, USB3PHY_PIPE_CLOCK_CONTROL); in awusb3phy_phy_enable()
137 val = RD4(sc->res, USB3PHY_APP); in awusb3phy_phy_enable()
145 val = RD4(sc->res, USB3PHY_PHY_TUNE_HIGH); in awusb3phy_phy_enable()
H A Dif_awg.c336 val = RD4(sc, EMAC_RX_CTL_0); in awg_miibus_statchg()
476 tx = RD4(sc, EMAC_TX_CTL_0); in awg_enable_mac()
477 rx = RD4(sc, EMAC_RX_CTL_0); in awg_enable_mac()
566 val = RD4(sc, EMAC_TX_CTL_1); in awg_init_dma()
570 val = RD4(sc, EMAC_RX_CTL_1); in awg_init_dma()
582 val = RD4(sc, EMAC_TX_CTL_1); in awg_stop_dma()
591 val = RD4(sc, EMAC_TX_CTL_1); in awg_stop_dma()
595 val = RD4(sc, EMAC_RX_CTL_1); in awg_stop_dma()
947 val = RD4(sc, EMAC_TX_CTL_1); in awg_dma_start_tx()
1323 val = RD4(sc, EMAC_INT_STA); in awg_intr()
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/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_super.c159 RD4(sc, sc->base_reg, &reg); in super_mux_init()
197 RD4(sc, sc->base_reg, &reg); in super_mux_set_mux()
211 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
215 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
222 RD4(sc, sc->base_reg, &dummy); in super_mux_set_mux()
/freebsd/sys/arm/xilinx/
H A Dzy7_devcfg.c96 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
415 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) & in zy7_devcfg_init_hw()
428 devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL); in zy7_devcfg_reset_pl()
442 if ((RD4(sc, ZY7_DEVCFG_STATUS) & in zy7_devcfg_reset_pl()
460 while ((RD4(sc, ZY7_DEVCFG_STATUS) & in zy7_devcfg_reset_pl()
569 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) & in zy7_devcfg_write()
615 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) & in zy7_devcfg_write()
649 istatus = RD4(sc, ZY7_DEVCFG_INT_STATUS); in zy7_devcfg_intr()
650 imask = ~RD4(sc, ZY7_DEVCFG_INT_MASK); in zy7_devcfg_intr()
684 pl_done = ((RD4(sc, ZY7_DEVCFG_INT_STATUS) & in zy7_devcfg_sysctl_pl_done()
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H A Dzy7_qspi.c105 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
228 if (nvalid < 4 && (RD4(sc, ZY7_QSPI_INTR_STAT_REG) & in zy7_qspi_write_fifo()
277 data = RD4(sc, ZY7_QSPI_RX_DATA_REG); in zy7_qspi_read_fifo()
307 (RD4(sc, ZY7_QSPI_INTR_STAT_REG) & in zy7_qspi_read_fifo()
316 while ((RD4(sc, ZY7_QSPI_INTR_STAT_REG) & in zy7_qspi_abort_transfer()
318 (void)RD4(sc, ZY7_QSPI_RX_DATA_REG); in zy7_qspi_abort_transfer()
337 istatus = RD4(sc, ZY7_QSPI_INTR_STAT_REG); in zy7_qspi_intr()
417 sc->lqspi_cfg_shadow = RD4(sc, ZY7_QSPI_LQSPI_CFG_REG); in zy7_qspi_init_hw()
H A Dzy7_spi.c92 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
177 byte = RD4(sc, ZY7_SPI_RX_DATA_REG) & 0xff; in zy7_spi_read_fifo()
192 (RD4(sc, ZY7_SPI_INTR_STAT_REG) & in zy7_spi_read_fifo()
201 while ((RD4(sc, ZY7_SPI_INTR_STAT_REG) & in zy7_spi_abort_transfer()
203 (void)RD4(sc, ZY7_SPI_RX_DATA_REG); in zy7_spi_abort_transfer()
222 istatus = RD4(sc, ZY7_SPI_INTR_STAT_REG); in zy7_spi_intr()
/freebsd/sys/arm64/rockchip/
H A Drk_pcie_phy.c97 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) macro
110 RD4(sc, GRF_SOC_CON8); in cfg_write()
114 RD4(sc, GRF_SOC_CON8); in cfg_write()
117 RD4(sc, GRF_SOC_CON8); in cfg_write()
127 RD4(sc, GRF_SOC_CON8); in cfg_read()
129 val = RD4(sc, GRF_SOC_STATUS1); in cfg_read()
H A Drk_tsadc.c101 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
475 val = RD4(sc, TSADC_INT_EN); in tsadc_init_tsensor()
489 val = RD4(sc, TSADC_AUTO_CON); in tsadc_init_tsensor()
496 val = RD4(sc, TSADC_INT_EN); in tsadc_init_tsensor()
574 val = RD4(sc, TSADC_DATA(sensor->channel)); in tsadc_read_temp()
582 __func__, RD4(sc, TSADC_USER_CON), RD4(sc, TSADC_AUTO_CON), in tsadc_read_temp()
583 RD4(sc, TSADC_COMP_INT(sensor->channel)), in tsadc_read_temp()
584 RD4(sc, TSADC_COMP_SHUT(sensor->channel))); in tsadc_read_temp()
671 val = RD4(sc, TSADC_INT_PD); in tsadc_intr()
810 val = RD4(sc, TSADC_AUTO_CON); in tsadc_attach()
/freebsd/sys/arm/nvidia/
H A Dtegra_rtc.c76 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
111 if ((RD4(sc, RTC_BUSY) & RTC_BUSY_STATUS) == 0) in tegra_rtc_wait()
134 msec = RD4(sc, RTC_MILLI_SECONDS); in tegra_rtc_gettime()
135 sec = RD4(sc, RTC_SHADOW_SECONDS); in tegra_rtc_gettime()
168 status = RD4(sc, RTC_INTR_STATUS); in tegra_rtc_intr()
H A Dtegra_mc.c98 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
146 stat = RD4(sc, MC_INTSTATUS); in tegra_mc_intr()
172 err = RD4(sc, MC_ERR_STATUS); in tegra_mc_intr()
173 addr = RD4(sc, MC_ERR_STATUS); in tegra_mc_intr()
/freebsd/sys/arm/freescale/imx/
H A Dimx6_src.c57 RD4(struct src_softc *sc, bus_size_t off) in RD4() function
79 reg = RD4(src_sc, SRC_SCR); in src_reset_ipu()
84 reg = RD4(src_sc, SRC_SCR); in src_reset_ipu()
H A Dimx_iomux.c105 RD4(struct iomux_softc *sc, bus_size_t off) in RD4() function
139 val = (RD4(sc, reg) & ~mask) | (select << shift); in iomux_configure_input()
273 return (RD4(iomux_sc, regaddr)); in imx_iomux_gpr_get()
302 val = RD4(iomux_sc, regaddr * 4); in imx_iomux_gpr_set_masked()
H A Dimx_spi.c153 RD4(struct spi_softc *sc, bus_size_t offset) in RD4() function
269 (void)RD4(sc, ECSPI_CFGREG); in spi_hw_setup()
276 while (sc->rxidx < sc->rxlen && (RD4(sc, ECSPI_STATREG) & SREG_RR)) { in spi_empty_rxfifo()
277 sc->rxbuf[sc->rxidx++] = (uint8_t)RD4(sc, ECSPI_RXDATA); in spi_empty_rxfifo()
309 status = RD4(sc, ECSPI_STATREG); in spi_intr()
359 (void)RD4(sc, ECSPI_INTREG); in spi_intr()
/freebsd/sys/arm/nvidia/drm2/
H A Dtegra_hdmi.c547 val = RD4(sc, HDMI_NV_PDISP_SOR_AUDIO_SPARE0); in audio_setup()
567 val = RD4(sc, HDMI_NV_PDISP_AUDIO_N); in audio_setup()
581 val = RD4(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); in audio_disable()
665 val = RD4(sc, HDMI_NV_PDISP_SOR_PLL0); in hdmi_sor_start()
672 val = RD4(sc, HDMI_NV_PDISP_SOR_PLL0); in hdmi_sor_start()
681 val = RD4(sc, HDMI_NV_PDISP_SOR_PWR); in hdmi_sor_start()
707 val = RD4(sc, HDMI_NV_PDISP_SOR_STATE1); in hdmi_sor_start()
789 val = RD4(sc, HDMI_NV_PDISP_SOR_PLL0); in hdmi_enable()
794 val = RD4(sc, HDMI_NV_PDISP_SOR_PLL0); in hdmi_enable()
852 val = RD4(sc,HDMI_NV_PDISP_SOR_CSTM); in hdmi_enable()
[all …]
/freebsd/sys/dev/tpm/
H A Dtpm20.h147 RD4(struct tpm_sc *sc, bus_size_t off) in RD4() function
176 WR4(sc, off, RD4(sc, off) & val); in AND4()
188 WR4(sc, off, RD4(sc, off) | val); in OR4()
/freebsd/sys/arm64/freescale/imx/clk/
H A Dimx_clk_mux.c45 #define RD4(_clk, off, val) \ macro
83 rv = RD4(clk, sc->offset, &reg); in imx_clk_mux_init()
109 RD4(clk, sc->offset, &reg); in imx_clk_mux_set_mux()
/freebsd/sys/dev/clk/
H A Dclk_mux.c41 #define RD4(_clk, off, val) \ macro
80 rv = RD4(clk, sc->offset, &reg); in clknode_mux_init()
106 RD4(clk, sc->offset, &reg); in clknode_mux_set_mux()
H A Dclk_gate.c41 #define RD4(_clk, off, val) \ macro
95 RD4(clk, sc->offset, &reg); in clknode_gate_set_gate()
109 rv = RD4(clk, sc->offset, &reg); in clknode_gate_get_gate()
/freebsd/sys/arm/ti/
H A Dti_sdhci.c149 RD4(struct ti_sdhci_softc *sc, bus_size_t off) in RD4() function
167 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); in ti_sdhci_read_1()
190 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); in ti_sdhci_read_2()
210 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); in ti_sdhci_read_2()
219 val32 = RD4(sc, off); in ti_sdhci_read_4()
269 val32 = RD4(sc, off & ~3); in ti_sdhci_write_1()
296 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); in ti_sdhci_write_2()
319 val32 = RD4(sc, off & ~3); in ti_sdhci_write_2()
/freebsd/sys/dev/clk/rockchip/
H A Drk_clk_gate.c41 #define RD4(_clk, off, val) \ macro
80 rv = RD4(clk, sc->offset, &reg); in rk_clk_gate_init()
107 RD4(clk, sc->offset, &reg); in rk_clk_gate_set_gate()
/freebsd/sys/arm/mv/clk/
H A Darmada38x_gen.c47 #define RD4(_clk, offset, val) \ macro
60 RD4(clk, 0, &reg); in armada38x_gen_recalc()
/freebsd/sys/arm64/qoriq/
H A Dqoriq_gpio_pic.c67 #define RD4(sc, off) bus_read_4((sc)->base.sc_mem, (off)) macro
79 reg = RD4(sc, GPIO_GPIMR); in qoriq_gpio_pic_set_intr()
107 status = RD4(sc, GPIO_GPIER); in qoriq_gpio_pic_intr()
108 status &= RD4(sc, GPIO_GPIMR); in qoriq_gpio_pic_intr()
248 reg = RD4(sc, GPIO_GPICR); in qoriq_gpio_pic_setup_intr()

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