/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/none/tests/mips64/ |
H A D | branches.stdout.exp-r6 | 76 --- BEQ --- if RSval == RTval then out = RDval + 1 else out = RDval + 6 93 --- BNE --- if RSval != RTval then out = RDval + 1 else out = RDval + 6 110 --- BEQZ --- if RSval == 0 then out = RDval + 1 else out = RDval + 6 111 beqz :: out: 1, RDval: 0, RSval: 0 112 beqz :: out: 7, RDval: 1, RSval: 1 127 --- BGEZ --- if RSval >= 0 then out = RDval + 1 else out = RDval + 6 128 bgez :: out: 1, RDval: 0, RSval: 0 144 --- BGTZ --- if RSval > 0 then out = RDval + 1 else out = RDval + 6 161 --- BLEZ --- if RSval <= 0 then out = RDval + 1 else out = RDval + 6 178 --- BLTZ --- if RSval < 0 then out = RDval + 1 else out = RDval + 6 [all …]
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H A D | branches.c | 153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument 175 #define TESTINST6(instruction, RDval, RSval, RD, RS) \ argument 182 instruction" $"#RS", end21"instruction#RDval "\n\t" \ 185 "b r_end"instruction#RDval "\n\t" \ 187 "end21"instruction#RDval":" "\n\t" \ 190 "r_end"instruction#RDval":" "\n\t" \ 194 : "r" (RSval), "r" (RDval) \ 198 out, RDval, RSval); \ 224 #define TESTINST5l(instruction, RDval, RSval, RD, RS) \ argument 231 instruction" $"#RS", end"instruction#RDval "\n\t" \ [all …]
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H A D | macro_fpu.h | 219 #define TESTINST1s(instruction, RDval) \ argument 228 instruction" end"instruction"s"#RDval "\n\t" \ 231 "end"instruction"s"#RDval":" "\n\t" \ 243 #define TESTINST1d(instruction, RDval) \ argument 252 instruction" end"instruction"d"#RDval "\n\t" \ 313 #define TESTINST_CONDs(instruction, RDval) \ argument 322 "bc1f end"instruction"s"#RDval "\n\t" \ 325 "end"instruction"s"#RDval":" "\n\t" \ 336 #define TESTINST_CONDd(instruction, RDval) \ argument 345 "bc1f end"instruction"d"#RDval "\n\t" \ [all …]
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H A D | branch_and_jump_instructions.c | 108 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument 131 #define TEST4(instruction, RDval, RSval, RD, RS) \ argument 138 instruction" $"#RS", end"instruction#RDval "\n\t" \ 141 "end"instruction#RDval":" "\n\t" \ 146 : "r" (RSval), "r" (RDval) \ 153 #define TEST5(instruction, RDval, RSval, RD, RS) \ argument 160 instruction" $"#RS", end21"instruction#RDval "\n\t" \ 163 "b r_end"instruction#RDval "\n\t" \ 165 "end21"instruction#RDval":" "\n\t" \ 168 "r_end"instruction#RDval":" "\n\t" \ [all …]
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H A D | move_instructions.stdout.exp-BE | 1167 movf :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1265 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1269 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1273 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1277 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1281 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1285 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1289 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1293 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1297 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 [all …]
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H A D | move_instructions.stdout.exp-LE | 1167 movf :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1265 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1269 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1273 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1277 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1281 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1285 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1289 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1293 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1297 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 [all …]
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H A D | branches.stdout.exp | 76 --- BEQ --- if RSval == RTval then out = RDval + 1 else out = RDval + 6 93 --- BNE --- if RSval != RTval then out = RDval + 1 else out = RDval + 6 110 --- BEQZ --- if RSval == 0 then out = RDval + 1 else out = RDval + 6 127 --- BGEZ --- if RSval >= 0 then out = RDval + 1 else out = RDval + 6 144 --- BGTZ --- if RSval > 0 then out = RDval + 1 else out = RDval + 6 161 --- BLEZ --- if RSval <= 0 then out = RDval + 1 else out = RDval + 6 178 --- BLTZ --- if RSval < 0 then out = RDval + 1 else out = RDval + 6 195 --- BGEZAL --- if RSval >= 0 then out = RDval + 6 else out = RDval + 5 212 --- BLTZAL --- if RSval < 0 then out = RDval + 6 else out = RDval + 5 229 --- BNEZ --- if RSval != 0 then out = RDval + 1 else out = RDval + 6 [all …]
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/dports/devel/valgrind/valgrind-dragonfly-dragonfly/none/tests/mips64/ |
H A D | branches.stdout.exp-r6 | 76 --- BEQ --- if RSval == RTval then out = RDval + 1 else out = RDval + 6 93 --- BNE --- if RSval != RTval then out = RDval + 1 else out = RDval + 6 110 --- BEQZ --- if RSval == 0 then out = RDval + 1 else out = RDval + 6 111 beqz :: out: 1, RDval: 0, RSval: 0 112 beqz :: out: 7, RDval: 1, RSval: 1 127 --- BGEZ --- if RSval >= 0 then out = RDval + 1 else out = RDval + 6 128 bgez :: out: 1, RDval: 0, RSval: 0 144 --- BGTZ --- if RSval > 0 then out = RDval + 1 else out = RDval + 6 161 --- BLEZ --- if RSval <= 0 then out = RDval + 1 else out = RDval + 6 178 --- BLTZ --- if RSval < 0 then out = RDval + 1 else out = RDval + 6 [all …]
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H A D | branches.c | 153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument 175 #define TESTINST6(instruction, RDval, RSval, RD, RS) \ argument 182 instruction" $"#RS", end21"instruction#RDval "\n\t" \ 185 "b r_end"instruction#RDval "\n\t" \ 187 "end21"instruction#RDval":" "\n\t" \ 190 "r_end"instruction#RDval":" "\n\t" \ 194 : "r" (RSval), "r" (RDval) \ 198 out, RDval, RSval); \ 224 #define TESTINST5l(instruction, RDval, RSval, RD, RS) \ argument 231 instruction" $"#RS", end"instruction#RDval "\n\t" \ [all …]
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H A D | macro_fpu.h | 219 #define TESTINST1s(instruction, RDval) \ argument 228 instruction" end"instruction"s"#RDval "\n\t" \ 231 "end"instruction"s"#RDval":" "\n\t" \ 243 #define TESTINST1d(instruction, RDval) \ argument 252 instruction" end"instruction"d"#RDval "\n\t" \ 313 #define TESTINST_CONDs(instruction, RDval) \ argument 322 "bc1f end"instruction"s"#RDval "\n\t" \ 325 "end"instruction"s"#RDval":" "\n\t" \ 336 #define TESTINST_CONDd(instruction, RDval) \ argument 345 "bc1f end"instruction"d"#RDval "\n\t" \ [all …]
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H A D | branch_and_jump_instructions.c | 108 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument 131 #define TEST4(instruction, RDval, RSval, RD, RS) \ argument 138 instruction" $"#RS", end"instruction#RDval "\n\t" \ 141 "end"instruction#RDval":" "\n\t" \ 146 : "r" (RSval), "r" (RDval) \ 153 #define TEST5(instruction, RDval, RSval, RD, RS) \ argument 160 instruction" $"#RS", end21"instruction#RDval "\n\t" \ 163 "b r_end"instruction#RDval "\n\t" \ 165 "end21"instruction#RDval":" "\n\t" \ 168 "r_end"instruction#RDval":" "\n\t" \ [all …]
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H A D | move_instructions.stdout.exp-BE | 1167 movf :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1265 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1269 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1273 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1277 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1281 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1285 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1289 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1293 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1297 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 [all …]
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H A D | move_instructions.stdout.exp-LE | 1167 movf :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1265 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1269 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1273 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1277 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1281 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1285 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1289 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1293 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 1297 movt :: RDval: 0x0, RSval: 0xffffffff, out: 0x0 [all …]
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H A D | branches.stdout.exp | 76 --- BEQ --- if RSval == RTval then out = RDval + 1 else out = RDval + 6 93 --- BNE --- if RSval != RTval then out = RDval + 1 else out = RDval + 6 110 --- BEQZ --- if RSval == 0 then out = RDval + 1 else out = RDval + 6 127 --- BGEZ --- if RSval >= 0 then out = RDval + 1 else out = RDval + 6 144 --- BGTZ --- if RSval > 0 then out = RDval + 1 else out = RDval + 6 161 --- BLEZ --- if RSval <= 0 then out = RDval + 1 else out = RDval + 6 178 --- BLTZ --- if RSval < 0 then out = RDval + 1 else out = RDval + 6 195 --- BGEZAL --- if RSval >= 0 then out = RDval + 6 else out = RDval + 5 212 --- BLTZAL --- if RSval < 0 then out = RDval + 6 else out = RDval + 5 229 --- BNEZ --- if RSval != 0 then out = RDval + 1 else out = RDval + 6 [all …]
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/dports/devel/valgrind-lts/valgrind-dragonfly-dragonfly/none/tests/mips32/ |
H A D | fpu_branches.c | 44 #define TESTINST1s(instruction, RDval) \ argument 52 instruction" end"instruction"s"#RDval "\n\t" \ 55 "end"instruction"s"#RDval":" "\n\t" \ 66 #define TESTINST1d(instruction, RDval) \ argument 74 instruction" end"instruction"d"#RDval "\n\t" \ 130 #define TESTINST_CONDs(instruction, RDval) \ argument 138 "bc1f end"instruction"s"#RDval "\n\t" \ 141 "end"instruction"s"#RDval":" "\n\t" \ 152 #define TESTINST_CONDd(instruction, RDval) \ argument 160 "bc1f end"instruction"d"#RDval "\n\t" \ [all …]
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H A D | branches.c | 141 "end"instruction#RDval":\n\t" \ 164 "end"instruction#RDval":\n\t" \ 169 : "r" (RSval), "r" (RDval) \ 189 "end21"instruction#RDval":\n\t" \ 192 "r_end"instruction#RDval":\n\t" \ 196 : "r" (RSval), "r" (RDval) \ 215 "end"instruction#RDval":\n\t" \ 238 "end"instruction#RDval":\n\t" \ 243 : "r" (RSval), "r" (RDval) \ 263 "end21"instruction#RDval":\n\t" \ [all …]
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H A D | MoveIns.stdout.exp-BE | 114 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 117 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 118 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 119 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0 125 movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 128 movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 230 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 233 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 235 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 238 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 [all …]
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H A D | MoveIns.stdout.exp-mips32r2-LE | 148 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 151 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 152 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 153 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0 159 movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 162 movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 264 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 267 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 269 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 272 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 [all …]
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H A D | MoveIns.stdout.exp-mips32r2-BE | 148 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 151 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 152 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 153 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0 159 movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 162 movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 264 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 267 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 269 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 272 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 [all …]
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H A D | branches_r6.c | 53 #define TESTINST2(instruction, RDval, RSval, RD, RS) \ argument 62 "b r_end"instruction#RDval"\n\t" \ 64 "end21"instruction#RDval":\n\t" \ 67 "r_end"instruction#RDval":\n\t" \ 70 : "r" (RSval), "r" (RDval) \ 77 #define TESTINST3(instruction, RDval, RSval, RD, RS) \ argument 83 instruction" $" #RS ", end"instruction#RDval"\n\t" \ 86 "end"instruction#RDval":\n\t" \ 90 : "r" (RSval), "r" (RDval) \ 107 "end"instruction#RDval":\n\t" \ [all …]
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/dports/devel/valgrind/valgrind-dragonfly-dragonfly/none/tests/mips32/ |
H A D | fpu_branches.c | 44 #define TESTINST1s(instruction, RDval) \ argument 52 instruction" end"instruction"s"#RDval "\n\t" \ 55 "end"instruction"s"#RDval":" "\n\t" \ 66 #define TESTINST1d(instruction, RDval) \ argument 74 instruction" end"instruction"d"#RDval "\n\t" \ 130 #define TESTINST_CONDs(instruction, RDval) \ argument 138 "bc1f end"instruction"s"#RDval "\n\t" \ 141 "end"instruction"s"#RDval":" "\n\t" \ 152 #define TESTINST_CONDd(instruction, RDval) \ argument 160 "bc1f end"instruction"d"#RDval "\n\t" \ [all …]
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H A D | branches.c | 141 "end"instruction#RDval":\n\t" \ 164 "end"instruction#RDval":\n\t" \ 169 : "r" (RSval), "r" (RDval) \ 189 "end21"instruction#RDval":\n\t" \ 192 "r_end"instruction#RDval":\n\t" \ 196 : "r" (RSval), "r" (RDval) \ 215 "end"instruction#RDval":\n\t" \ 238 "end"instruction#RDval":\n\t" \ 243 : "r" (RSval), "r" (RDval) \ 263 "end21"instruction#RDval":\n\t" \ [all …]
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H A D | MoveIns.stdout.exp-BE | 114 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 117 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 118 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 119 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0 125 movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 128 movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 230 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 233 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 235 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 238 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 [all …]
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H A D | MoveIns.stdout.exp-mips32r2-LE | 148 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 151 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 152 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 153 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0 159 movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 162 movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 264 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 267 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 269 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 272 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 [all …]
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H A D | MoveIns.stdout.exp-mips32r2-BE | 148 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 151 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 152 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 153 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0 159 movf $t0, $t1, $fcc4 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0 162 movf $t0, $t1, $fcc4 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 264 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 267 movt $t0, $t1, $fcc0 :: out: 0x0, RDval: 0xffffffff, RSval: 0x0, cc: 1 269 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1 272 movt $t0, $t1, $fcc4 :: out: 0x0, RDval: 0x0, RSval: 0x5, cc: 0 [all …]
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