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/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dfsl-sec2.txt1 Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
10 - interrupts : the SEC's interrupt number
21 bit 1 = set if SEC has the ARC4 EU (AFEU)
22 bit 2 = set if SEC has the DES/3DES EU (DEU)
23 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
25 bit 5 = set if SEC has the public key EU (PKEU)
26 bit 6 = set if SEC has the AES EU (AESU)
27 bit 7 = set if SEC has the Kasumi EU (KEU)
28 bit 8 = set if SEC has the CRC EU (CRCU)
31 remaining bits are reserved for future SEC EUs.
[all …]
H A Dfsl-sec6.txt1 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
2 Currently Freescale powerpc chip C29X is embedded with SEC 6.
3 SEC 6 device tree binding include:
4 -SEC 6 Node
9 SEC 6 Node
13 Node defines the base address of the SEC 6 block.
15 configuration registers for the SEC 6 block.
16 For example, In C293, we could see three SEC 6 node.
28 Definition: A standard property. Define the 'ERA' of the SEC
48 address and length of the SEC 6 configuration registers.
[all …]
H A Dfsl,sec-v4.0.yaml8 title: Freescale SEC 4
16 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
19 SEC 4 h/w can process requests from 2 types of sources.
20 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
21 2. Job Rings (HW interface between cores & SEC 4 registers).
25 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
28 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
79 description: Defines the 'ERA' of the SEC device.
87 Job Ring (JR) Node. Defines data processing interface to SEC 4 across the
H A Dfsl-sec4.txt2 SEC 4 Device Tree Binding
7 -SEC 4 Node
15 NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
23 SEC 4 h/w can process requests from 2 types of sources.
25 2. Job Rings (HW interface between cores & SEC 4 registers).
29 HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
32 SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
42 SEC 4 Node
46 Node defines the base address of the SEC 4 block.
48 configuration registers for the SEC 4 block. It
[all …]
H A Dhisilicon,hip07-sec.txt1 * Hisilicon hip07 Security Accelerator (SEC)
16 Interrupt 0 is for the SEC unit error queue.
22 - iommus: The SEC units are behind smmu-v3 iommus.
/freebsd/contrib/ntp/scripts/monitoring/
H A Dtimelocal.pl34 $SEC = 1;
35 $MIN = 60 * $SEC;
46 $cheat + $_[0] * $SEC + $_[1] * $MIN + $_[2] * $HR + ($_[3]-1) * $DAYS;
54 $cheat + $_[0] * $SEC + $_[1] * $MIN + $_[2] * $HR + ($_[3]-1) * $DAYS
75 $guess -= $g[0] * $SEC + $g[1] * $MIN + $g[2] * $HR + $g[3] * $DAYS;
/freebsd/sys/contrib/openzfs/lib/libspl/include/sys/
H A Dtime.h34 #ifndef SEC
35 #define SEC 1 macro
71 #define NSEC2SEC(n) ((n) / (NANOSEC / SEC))
75 #define SEC2NSEC(m) ((hrtime_t)(m) * (NANOSEC / SEC))
/freebsd/sys/contrib/openzfs/include/os/linux/spl/sys/
H A Dtime.h40 #define SEC 1 macro
51 #define NSEC2SEC(n) ((n) / (NANOSEC / SEC))
52 #define SEC2NSEC(m) ((hrtime_t)(m) * (NANOSEC / SEC))
/freebsd/sys/contrib/openzfs/include/os/freebsd/spl/sys/
H A Dtime.h36 #define SEC 1 macro
48 #define NSEC2SEC(n) ((n) / (NANOSEC / SEC))
49 #define SEC2NSEC(m) ((hrtime_t)(m) * (NANOSEC / SEC))
/freebsd/usr.bin/mkuzip/
H A Dmkuz_time.h30 #define SEC(x) ((x)->tv_sec) macro
33 #define timespec2dtime(s) ((double)SEC(s) + \
/freebsd/usr.bin/calendar/
H A Dsunpos.c192 #define SEC(h) 0 macro
313 sunpos(year, 6, d, UTCoffset, HOUR(h), MIN(h), SEC(h), in fequinoxsolstice()
343 sunpos(year, 12, d, UTCoffset, HOUR(h), MIN(h), SEC(h), in fequinoxsolstice()
382 HOUR(h), MIN(h), SEC(h), 0.0, 0.0, &prevL, &dec); in calculatesunlongitude30()
389 HOUR(h), MIN(h), SEC(h), in calculatesunlongitude30()
/freebsd/tools/kerneldoc/subsys/
H A DDoxyfile-dev_sec6 PROJECT_NAME = "FreeBSD kernel SEC device code"
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dsnps,dw-umctl2-ddrc.yaml16 be equipped with SEC/DEC ECC feature if DRAM data bus width is either
20 controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
/freebsd/crypto/openssl/doc/man7/
H A DEVP_PKEY-EC.pod64 operations. The encoding conforms with Sec. 2.3.3 of the SECG SEC 1 ("Elliptic Curve
114 2.3.4 of the SECG SEC 1 ("Elliptic Curve Cryptography") standard.
134 is expected to be a point conforming to Sec. 2.3.4 of the SECG SEC 1 ("Elliptic
H A DEVP_KDF-X963.pod83 "SEC 1: Elliptic Curve Cryptography"
/freebsd/sys/cddl/dev/profile/
H A Dprofile.c346 { "s", NANOSEC / SEC }, in profile_provide()
347 { "sec", NANOSEC / SEC }, in profile_provide()
/freebsd/tools/regression/sockets/udp_pingpong/
H A Dudp_pingpong.c101 #define SEC(x) ((x)->tv_sec) macro
108 SEC(ts) = (tv)->tv_sec; \
/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra194-cbb.yaml60 A secure interrupt is received for SEC(firewall) & SLV errors and a
/freebsd/crypto/openssl/doc/man3/
H A DEVP_PKEY_set1_encoded_public_key.pod39 should be a point conforming to Sec. 2.3.4 of the SECG SEC 1 ("Elliptic
H A DEC_POINT_new.pod187 The encoding conforms with Sec. 2.3.3 of the SECG SEC 1 ("Elliptic Curve
191 to Sec. 2.3.4 of the SECG SEC 1 ("Elliptic Curve Cryptography") standard.
/freebsd/cddl/contrib/opensolaris/lib/libdtrace/common/
H A Ddt_options.c756 { "s", NANOSEC / SEC }, in dt_opt_rate()
757 { "sec", NANOSEC / SEC }, in dt_opt_rate()
/freebsd/sys/sys/
H A Dmount.h901 #define VFS_CHECKEXP(MP, NAM, EXFLG, CRED, NUMSEC, SEC) ({ \ argument
905 SEC); \
/freebsd/contrib/ldns/packaging/fedora/
H A Dldns.spec8 Summary: Lowlevel DNS(SEC) library with API
/freebsd/contrib/unbound/contrib/
H A Dunbound.spec_fedora9 Summary: Validating, recursive, and caching DNS(SEC) resolver
44 Unbound is a validating, recursive, and caching DNS(SEC) resolver.
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dhaleakala.dts96 0x6 0x4>; /* ECC SEC Error */

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