Home
last modified time | relevance | path

Searched refs:SF (Results 1 – 25 of 5656) sorted by relevance

12345678910>>...227

/dports/math/palp/palp-2.20/
H A DSingularInput.c82 FILE *SF; in HyperSurfSingular() local
101 fprintf(SF,"0"); in HyperSurfSingular()
110 fprintf(SF,";"); in HyperSurfSingular()
118 fprintf(SF,","); in HyperSurfSingular()
236 fprintf(SF,";\n"); in HyperSurfSingular()
240 fprintf(SF,";\n"); in HyperSurfSingular()
255 fprintf(SF,"}\n"); in HyperSurfSingular()
268 fprintf(SF,"}\n"); in HyperSurfSingular()
323 fprintf(SF,"};\n"); in HyperSurfSingular()
511 fprintf(SF,"" in HyperSurfSingular()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.h241 SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
293 SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
300 SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
307 SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
315 SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
322 SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
330 SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
337 SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
345 SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
352 SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
[all …]
H A Ddcn30_optc.h127 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
133 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
140 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
144 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
177 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
206 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
207 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
208 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
220 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
222 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
H A Ddcn30_mpc.h292 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
297 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
300 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
316 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
322 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
323 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
399 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
404 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
424 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
430 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.h241 SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
293 SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
300 SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
307 SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
315 SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
322 SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
330 SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
337 SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
345 SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
352 SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
[all …]
H A Ddcn30_optc.h127 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
133 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
140 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
144 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
177 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
206 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
207 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
208 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
220 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
222 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
H A Ddcn30_mpc.h292 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
297 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
300 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
316 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
322 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
323 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
399 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
404 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
424 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
430 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.h241 SF(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
293 SF(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
300 SF(MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
307 SF(MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
315 SF(MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
322 SF(MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
330 SF(MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
337 SF(MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
345 SF(MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\
352 SF(MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\
[all …]
H A Ddcn30_optc.h127 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
133 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
140 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
144 SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
177 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
206 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
207 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
208 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
220 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
222 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
[all …]
H A Ddcn30_mpc.h292 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
297 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
300 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
316 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
322 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
323 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \
399 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
404 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
424 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\
430 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \
[all …]
/dports/games/libretro-cap32/libretro-cap32-ad7397f/cap32/
H A Dz80daa.h27 #define SF 0x80 macro
152 (0x80<<8)+SF +HF ,
153 (0x81<<8)+SF +HF +VF ,
154 (0x82<<8)+SF +HF +VF ,
155 (0x83<<8)+SF +HF ,
156 (0x84<<8)+SF +HF +VF ,
157 (0x85<<8)+SF +HF ,
158 (0x80<<8)+SF ,
159 (0x81<<8)+SF +VF ,
160 (0x82<<8)+SF +VF ,
[all …]
/dports/games/libretro-mame2000/mame2000-libretro-e364a15/src/cpu/i8085/
H A Di8085daa.h124 (0x80<<8)+SF +HF ,
125 (0x81<<8)+SF +HF +VF ,
126 (0x82<<8)+SF +HF +VF ,
127 (0x83<<8)+SF +HF ,
128 (0x84<<8)+SF +HF +VF ,
129 (0x85<<8)+SF +HF ,
130 (0x80<<8)+SF ,
131 (0x81<<8)+SF +VF ,
132 (0x82<<8)+SF +VF ,
133 (0x83<<8)+SF ,
[all …]
/dports/games/libretro-fbalpha/fbalpha-84eb9d9/src/cpu/z180/
H A Dz180daa.h124 (0x80<<8)+SF +HF ,
125 (0x81<<8)+SF +HF +VF ,
126 (0x82<<8)+SF +HF +VF ,
127 (0x83<<8)+SF +HF ,
128 (0x84<<8)+SF +HF +VF ,
129 (0x85<<8)+SF +HF ,
130 (0x80<<8)+SF ,
131 (0x81<<8)+SF +VF ,
132 (0x82<<8)+SF +VF ,
133 (0x83<<8)+SF ,
[all …]
/dports/emulators/gngeo/gngeo-gngeo_0.8/src/mamez80/
H A Dz80daa.h124 (0x80<<8)+SF +HF ,
125 (0x81<<8)+SF +HF +VF ,
126 (0x82<<8)+SF +HF +VF ,
127 (0x83<<8)+SF +HF ,
128 (0x84<<8)+SF +HF +VF ,
129 (0x85<<8)+SF +HF ,
130 (0x80<<8)+SF ,
131 (0x81<<8)+SF +VF ,
132 (0x82<<8)+SF +VF ,
133 (0x83<<8)+SF ,
[all …]
/dports/games/libretro-mame2003_plus/mame2003-plus-libretro-17e9889/src/cpu/z180/
H A Dz180daa.h124 (0x80<<8)+SF +HF ,
125 (0x81<<8)+SF +HF +VF ,
126 (0x82<<8)+SF +HF +VF ,
127 (0x83<<8)+SF +HF ,
128 (0x84<<8)+SF +HF +VF ,
129 (0x85<<8)+SF +HF ,
130 (0x80<<8)+SF ,
131 (0x81<<8)+SF +VF ,
132 (0x82<<8)+SF +VF ,
133 (0x83<<8)+SF ,
[all …]
/dports/games/libretro-mame2003_plus/mame2003-plus-libretro-17e9889/src/cpu/i8085/
H A Di8085daa.h124 (0x80<<8)+SF +HF ,
125 (0x81<<8)+SF +HF +VF ,
126 (0x82<<8)+SF +HF +VF ,
127 (0x83<<8)+SF +HF ,
128 (0x84<<8)+SF +HF +VF ,
129 (0x85<<8)+SF +HF ,
130 (0x80<<8)+SF ,
131 (0x81<<8)+SF +VF ,
132 (0x82<<8)+SF +VF ,
133 (0x83<<8)+SF ,
[all …]
/dports/games/libretro-mame2003/mame2003-libretro-4358db4/src/cpu/i8085/
H A Di8085daa.h124 (0x80<<8)+SF +HF ,
125 (0x81<<8)+SF +HF +VF ,
126 (0x82<<8)+SF +HF +VF ,
127 (0x83<<8)+SF +HF ,
128 (0x84<<8)+SF +HF +VF ,
129 (0x85<<8)+SF +HF ,
130 (0x80<<8)+SF ,
131 (0x81<<8)+SF +VF ,
132 (0x82<<8)+SF +VF ,
133 (0x83<<8)+SF ,
[all …]
/dports/games/libretro-mame2003/mame2003-libretro-4358db4/src/cpu/z180/
H A Dz180daa.h124 (0x80<<8)+SF +HF ,
125 (0x81<<8)+SF +HF +VF ,
126 (0x82<<8)+SF +HF +VF ,
127 (0x83<<8)+SF +HF ,
128 (0x84<<8)+SF +HF +VF ,
129 (0x85<<8)+SF +HF ,
130 (0x80<<8)+SF ,
131 (0x81<<8)+SF +VF ,
132 (0x82<<8)+SF +VF ,
133 (0x83<<8)+SF ,
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mmhubbub.h104 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
114 SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
121 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
124 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\
133 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
141 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
153 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
161 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
173 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
254 SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\
[all …]
H A Ddcn20_dwb.h53 #define SF(reg_name, field_name, post_fix)\ macro
106 SF(WB_ENABLE, WB_ENABLE, mask_sh),\
111 SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
112 SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
120 SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\
123 SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
129 SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
154 SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
157 SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
169 SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mmhubbub.h104 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
114 SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
121 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
124 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\
133 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
141 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
153 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
161 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
173 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
254 SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\
[all …]
H A Ddcn20_dwb.h53 #define SF(reg_name, field_name, post_fix)\ macro
106 SF(WB_ENABLE, WB_ENABLE, mask_sh),\
111 SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
112 SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
120 SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\
123 SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
129 SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
154 SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
157 SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
169 SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mmhubbub.h104 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
114 SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
121 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\
124 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\
133 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\
141 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\
153 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\
161 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\
173 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\
254 SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\
[all …]
H A Ddcn20_dwb.h53 #define SF(reg_name, field_name, post_fix)\ macro
106 SF(WB_ENABLE, WB_ENABLE, mask_sh),\
111 SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
112 SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
120 SF(CNV_MODE, CNV_OUT_BPC, mask_sh),\
123 SF(CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
129 SF(CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
154 SF(WB_DBG_MODE, WB_DBG_CMAP, mask_sh),\
157 SF(WB_HW_DEBUG, WB_HW_DEBUG, mask_sh),\
169 SF(WBSCL_MODE, WBSCL_MODE, mask_sh),\
[all …]
/dports/www/miniserve/miniserve-0.18.0/cargo-crates/actix-service-2.0.0/src/
H A Dmap_config.rs19 pub fn unit_config<I, SF, Cfg, Req>(factory: I) -> UnitConfig<SF, Cfg, Req> in unit_config() argument
29 factory: SF,
34 impl<SF, Req, F, Cfg> MapConfig<SF, Req, F, Cfg> {
49 impl<SF, Req, F, Cfg> Clone for MapConfig<SF, Req, F, Cfg>
51 SF: Clone,
63 impl<SF, Req, F, Cfg> ServiceFactory<Req> for MapConfig<SF, Req, F, Cfg>
84 factory: SF,
88 impl<SF, Cfg, Req> UnitConfig<SF, Cfg, Req>
101 impl<SF, Cfg, Req> Clone for UnitConfig<SF, Cfg, Req>
103 SF: Clone,
[all …]

12345678910>>...227