Searched refs:UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV (Results 1 – 1 of 1) sorted by relevance
262 #define UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(x) (((x) & 0xFF) << 20) macro837 reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(~0); in uphy_sata_enable()839 reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x19); in uphy_sata_enable()841 reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x1e); in uphy_sata_enable()