| /dports/cad/opentimer/OpenTimer-18d28ff/example/map9v3/ |
| H A D | map9v3.sdc | 1 create_clock -period 10000 -name clock [get_ports clock]
2 set_input_transition 100 -min -rise [get_ports clock] -clock clock
3 set_input_transition 100 -min -fall [get_ports clock] -clock clock
4 set_input_transition 100 -max -rise [get_ports clock] -clock clock
5 set_input_transition 100 -max -fall [get_ports clock] -clock clock
6 set_input_delay 1000 -min -rise [get_ports N_0_] -clock clock
7 set_input_delay 1000 -min -fall [get_ports N_0_] -clock clock
8 set_input_delay 1000 -max -rise [get_ports N_0_] -clock clock
9 set_input_delay 1000 -max -fall [get_ports N_0_] -clock clock
10 set_input_delay 1000 -min -rise [get_ports N_1_] -clock clock
[all …]
|
| /dports/devel/babeltrace/babeltrace-1.5.7/formats/ctf/ir/ |
| H A D | clock.c | 46 if (!clock) { in _bt_ctf_clock_create()
54 return clock; in _bt_ctf_clock_create()
88 if (!clock) { in bt_ctf_clock_create()
153 if (!clock || !desc || clock->frozen) { in bt_ctf_clock_set_description()
182 if (!clock || clock->frozen) { in bt_ctf_clock_set_frequency()
210 if (!clock || clock->frozen) { in bt_ctf_clock_set_precision()
239 if (!clock || clock->frozen) { in bt_ctf_clock_set_offset_s()
268 if (!clock || clock->frozen) { in bt_ctf_clock_set_offset()
296 if (!clock || clock->frozen) { in bt_ctf_clock_set_is_absolute()
311 if (!clock || !clock->uuid_set) { in bt_ctf_clock_get_uuid()
[all …]
|
| /dports/cad/openroad/OpenROAD-2.0/src/replace/test/design/nangate45/dynamic_node_top_wrap/ |
| H A D | dynamic_node_top_wrap.sdc | 10 set_input_delay -clock clk -max 5.1 [get_ports clk]
11 set_input_delay -clock clk -min 4.02 [get_ports clk]
12 set_input_delay -clock clk -max 5.1 [get_ports reset_in]
13 set_input_delay -clock clk -min 4.02 [get_ports reset_in]
14 set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[63]}]
15 set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[63]}]
16 set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[62]}]
17 set_input_delay -clock clk -min 4.02 [get_ports {dataIn_N[62]}]
18 set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[61]}]
20 set_input_delay -clock clk -max 5.1 [get_ports {dataIn_N[60]}]
[all …]
|
| /dports/net/chrony/chrony-4.2/ |
| H A D | hwclock.c | 116 return clock; in HCL_CreateInstance()
126 Free(clock); in HCL_DestroyInstance()
154 if (clock->n_samples >= clock->max_samples) in HCL_AccumulateSample()
165 for (i = clock->max_samples - clock->n_samples; i < clock->max_samples; i++) { in HCL_AccumulateSample()
166 clock->y_data[i - 1] = clock->y_data[i] - hw_delta; in HCL_AccumulateSample()
178 RGR_FindBestRobustRegression(clock->x_data + clock->max_samples - clock->n_samples, in HCL_AccumulateSample()
179 clock->y_data + clock->max_samples - clock->n_samples, in HCL_AccumulateSample()
191 if (clock->n_samples > clock->min_samples) in HCL_AccumulateSample()
192 clock->n_samples -= MIN(best_start, clock->n_samples - clock->min_samples); in HCL_AccumulateSample()
204 clock->n_samples, clock->offset, clock->frequency - 1.0, raw_freq - 1.0, err, in HCL_AccumulateSample()
[all …]
|
| /dports/net/chrony-lite/chrony-4.2/ |
| H A D | hwclock.c | 116 return clock; in HCL_CreateInstance()
126 Free(clock); in HCL_DestroyInstance()
154 if (clock->n_samples >= clock->max_samples) in HCL_AccumulateSample()
165 for (i = clock->max_samples - clock->n_samples; i < clock->max_samples; i++) { in HCL_AccumulateSample()
166 clock->y_data[i - 1] = clock->y_data[i] - hw_delta; in HCL_AccumulateSample()
178 RGR_FindBestRobustRegression(clock->x_data + clock->max_samples - clock->n_samples, in HCL_AccumulateSample()
179 clock->y_data + clock->max_samples - clock->n_samples, in HCL_AccumulateSample()
191 if (clock->n_samples > clock->min_samples) in HCL_AccumulateSample()
192 clock->n_samples -= MIN(best_start, clock->n_samples - clock->min_samples); in HCL_AccumulateSample()
204 clock->n_samples, clock->offset, clock->frequency - 1.0, raw_freq - 1.0, err, in HCL_AccumulateSample()
[all …]
|
| /dports/cad/openroad/OpenROAD-2.0/src/replace/test/design/nangate45/aes_cipher_top/ |
| H A D | aes_cipher_top.sdc | 11 set_input_delay -clock clk -max 0 [get_ports clk]
12 set_input_delay -clock clk -max 0 [get_ports rst]
13 set_input_delay -clock clk -max 0 [get_ports ld]
14 set_input_delay -clock clk -max 0 [get_ports {key[127]}]
15 set_input_delay -clock clk -max 0 [get_ports {key[126]}]
16 set_input_delay -clock clk -max 0 [get_ports {key[125]}]
17 set_input_delay -clock clk -max 0 [get_ports {key[124]}]
18 set_input_delay -clock clk -max 0 [get_ports {key[123]}]
19 set_input_delay -clock clk -max 0 [get_ports {key[122]}]
270 set_input_delay -clock clk -max 0 [get_ports SE]
[all …]
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/dts/ |
| H A D | am43xx-clocks.dtsi | 12 #clock-cells = <0>;
20 #clock-cells = <0>;
39 clock-mult = <1>;
40 clock-div = <1>;
47 clock-mult = <1>;
48 clock-div = <1>;
56 clock-div = <1>;
64 clock-div = <1>;
72 clock-div = <1>;
80 clock-div = <1>;
[all …]
|