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Searched refs:clock_type (Results 1 – 15 of 15) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c441 pp_clock_request.clock_type = dc_to_pp_clock_type(clock_for_voltage_req->clk_type); in dm_pp_apply_clock_for_voltage_request()
444 if (!pp_clock_request.clock_type) in dm_pp_apply_clock_for_voltage_request()
491 clock.clock_type = amd_pp_dcf_clock; in pp_rv_set_display_requirement()
495 clock.clock_type = amd_pp_f_clock; in pp_rv_set_display_requirement()
/dragonfly/sys/dev/drm/amd/display/dc/bios/
H A Dcommand_table2.c722 !cmd->dc_clock_type_to_atom(bp_params->clock_type, in set_dce_clock_v2_1()
729 if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) { in set_dce_clock_v2_1()
755 bp_params->clock_type); in set_dce_clock_v2_1()
H A Dcommand_table.c2434 !cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type)) in set_dce_clock_v2_1()
2440 if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) { in set_dce_clock_v2_1()
/dragonfly/sys/dev/drm/amd/include/
H A Ddm_pp_interface.h190 enum amd_pp_clock_type clock_type; member
/dragonfly/sys/dev/drm/amd/display/include/
H A Dbios_parser_types.h259 enum bp_dce_clock_type clock_type; member
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_atombios.h158 u8 clock_type,
H A Damdgpu_atombios.c996 u8 clock_type, in amdgpu_atombios_get_clock_dividers() argument
1017 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { in amdgpu_atombios_get_clock_dividers()
1018 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in amdgpu_atombios_get_clock_dividers()
1036 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in amdgpu_atombios_get_clock_dividers()
1066 args.v6_in.ulClock.ulComputeClockFlag = clock_type; in amdgpu_atombios_get_clock_dividers()
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dppatomfwctrl.h218 uint32_t clock_type, uint32_t clock_value,
H A Dppatomfwctrl.c247 uint32_t clock_type, uint32_t clock_value, in pp_atomfwctrl_get_gpu_pll_dividers_vega10() argument
256 pll_parameters.gpu_clock_type = clock_type; in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
H A Dsmu10_hwmgr.c59 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu10_display_clock_voltage_request()
205 clock_req.clock_type = amd_pp_dcf_clock; in smu10_set_clock_limit()
H A Dvega12_hwmgr.c1349 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega12_display_clock_voltage_request()
1405 clock_req.clock_type = amd_pp_dcef_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
H A Dvega10_hwmgr.c3748 enum amd_pp_clock_type clk_type = clock_req->clock_type; in vega10_display_clock_voltage_request()
3833 clock_req.clock_type = amd_pp_dcef_clock; in vega10_notify_smc_display_config_after_ps_adjustment()
/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_clocks.c311 dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK; in dce112_set_clock()
324 dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; in dce112_set_clock()
/dragonfly/sys/dev/drm/radeon/
H A Dradeon_atombios.c2817 u8 clock_type, in radeon_atom_get_clock_dividers() argument
2835 args.v1.ucAction = clock_type; in radeon_atom_get_clock_dividers()
2849 args.v2.ucAction = clock_type; in radeon_atom_get_clock_dividers()
2864 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { in radeon_atom_get_clock_dividers()
2865 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in radeon_atom_get_clock_dividers()
2883 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in radeon_atom_get_clock_dividers()
2914 args.v6_in.ulClock.ulComputeClockFlag = clock_type; in radeon_atom_get_clock_dividers()
H A Dradeon.h298 u8 clock_type,