Home
last modified time | relevance | path

Searched refs:cmd (Results 76 – 100 of 417) sorted by relevance

12345678910>>...17

/qemu/tests/qemu-iotests/
H A D15182 self.vm.cmd('blockdev-mirror',
127 self.vm.cmd('blockdev-mirror',
141 self.vm.cmd('block-job-set-speed', device='mirror', speed=0)
151 self.vm.cmd('blockdev-mirror',
210 self.vm.cmd('object-add', **{
219 self.vm.cmd('blockdev-add', **{
232 self.vm.cmd('blockdev-add', **{
245 self.vm.cmd('nbd-server-start', addr={
252 self.vm.cmd('block-export-add', id='exp0', type='nbd',
306 self.vm.cmd('blockdev-mirror',
[all …]
H A D23662 cmd = "write -P%s %s %s" % p variable
63 log(cmd)
64 log(vm.hmp_qemu_io("drive0", cmd))
100 cmd = "write -P%s %s %s" % p variable
101 log(cmd)
102 log(vm.hmp_qemu_io("drive0", cmd))
H A D12955 def do_test_stop(self, cmd, **args): argument
58 self.vm.cmd(cmd, **args)
60 self.vm.cmd("stop")
88 self.vm.cmd('blockdev-add', {
97 self.vm.cmd('blockdev-snapshot',
H A D13961 self.vm.cmd('blockdev-add', conv_keys = False, **opts)
75 self.vm.cmd('blockdev-add', conv_keys = False, **opts)
90 self.vm.cmd('device_add', id = device,
95 self.vm.cmd('device_del', id = device)
97 self.vm.cmd('system_reset')
124 self.vm.cmd('blockdev-insert-medium',
144 self.vm.cmd('blockdev-snapshot',
158 self.vm.cmd('drive-mirror', conv_keys=False, **opts)
163 self.vm.cmd('block-job-complete', device=id)
179 self.vm.cmd('blockdev-add', conv_keys = False, **opts)
[all …]
H A D040127 self.vm.cmd('quit')
141 self.vm.cmd('quit')
233 self.vm.cmd('device_del', id='scsi0')
468 self.vm.cmd('blockdev-add', **kwargs)
756 self.vm.cmd('blockdev-add', {
814 self.vm.cmd('block-commit',
830 self.vm.cmd('block-commit',
859 self.vm.cmd('block-commit',
881 self.vm.cmd('block-commit',
910 self.vm.cmd('blockdev-add', {
[all …]
/qemu/tests/qtest/
H A Dqmp-cmd-test.c24 static int query_error_class(const char *cmd) in query_error_class() argument
27 const char *cmd; in query_error_class() member
60 for (i = 0; fails[i].cmd; i++) { in query_error_class()
61 if (!strcmp(cmd, fails[i].cmd)) { in query_error_class()
70 const char *cmd = data; in test_query() local
71 int expected_error_class = query_error_class(cmd); in test_query()
78 resp = qtest_qmp(qts, "{ 'execute': %s }", cmd); in test_query()
95 static bool query_is_ignored(const char *cmd) in query_is_ignored() argument
120 if (!strcmp(cmd, ignored[i])) { in query_is_ignored()
H A Dahci-test.c86 AHCICommandHeader cmd; in verify_state() local
913 uint8_t cmd; in ahci_test_max() local
919 cmd = CMD_READ_MAX; in ahci_test_max()
1024 AHCICommand *cmd; in test_dma_fragmented() local
1048 ahci_command_free(cmd); in test_dma_fragmented()
1055 ahci_command_free(cmd); in test_dma_fragmented()
1104 AHCICommand *cmd; in test_flush_retry() local
1216 AHCICommand *cmd; in ahci_halted_io_test() local
1281 AHCICommand *cmd; in ahci_migrate_halted_io() local
1349 AHCICommand *cmd; in test_flush_migrate() local
[all …]
/qemu/include/qapi/qmp/
H A Ddispatch.h53 bool qmp_command_is_enabled(const QmpCommand *cmd);
54 bool qmp_command_available(const QmpCommand *cmd, Error **errp);
55 const char *qmp_command_name(const QmpCommand *cmd);
56 bool qmp_has_success_response(const QmpCommand *cmd);
62 typedef void (*qmp_cmd_callback_fn)(const QmpCommand *cmd, void *opaque);
/qemu/scripts/
H A Drender_block_graph.py46 bds_nodes = qmp.cmd('query-named-block-nodes')
49 job_nodes = qmp.cmd('query-block-jobs')
52 block_graph = qmp.cmd('x-debug-query-block-graph')
97 def cmd(self, cmd): argument
99 m = {'execute': cmd}
H A Dcheck_sparse.py51 for cmd in compile_commands:
52 cmdline = shlex.split(cmd['command'])
53 cmd = cmdline_for_sparse(sparse, cmdline) variable
55 ' '.join((shlex.quote(x) for x in cmd)))
57 r = subprocess.run(cmd, env=sparse_env, cwd=root_path)
/qemu/hw/sd/
H A Dpl181.c38 uint32_t cmd; member
70 VMSTATE_UINT32(cmd, PL181State),
178 request.cmd = s->cmd & PL181_CMD_INDEX; in pl181_do_command()
184 if (s->cmd & PL181_CMD_RESPONSE) { in pl181_do_command()
309 return s->cmd; in pl181_read()
392 s->cmd = value; in pl181_write()
393 if (s->cmd & PL181_CMD_ENABLE) { in pl181_write()
394 if (s->cmd & PL181_CMD_INTERRUPT) { in pl181_write()
397 } if (s->cmd & PL181_CMD_PENDING) { in pl181_write()
405 s->cmd &= ~PL181_CMD_ENABLE; in pl181_write()
[all …]
/qemu/tests/qemu-iotests/tests/
H A Dluks-detached-header282 cmd = 'qemu-io luks-2-payload-raw-format "write -P 41 0 64k"'
285 command_line=cmd
289 cmd = 'qemu-io luks-2-payload-raw-format "read -P 41 0 64k"'
292 command_line=cmd
297 cmd = 'qemu-io luks-3-payload-qcow2-format "write -P 42 0 64k"'
300 command_line=cmd
304 cmd = 'qemu-io luks-3-payload-qcow2-format "read -P 42 0 64k"'
307 command_line=cmd
/qemu/hw/misc/macio/
H A Dmac_dbdma.c78 DBDMA_DPRINTFCH(ch, "dbdma_cmd %p\n", cmd); in dump_dbdma_cmd()
85 le16_to_cpu(cmd->xfer_status)); in dump_dbdma_cmd()
451 uint16_t cmd, key; in channel_run() local
462 cmd = le16_to_cpu(current->command) & COMMAND_MASK; in channel_run()
464 switch (cmd) { in channel_run()
479 printf("command %x, invalid key 4\n", cmd); in channel_run()
484 switch (cmd) { in channel_run()
525 switch (cmd) { in channel_run()
873 uint16_t cmd; in dbdma_unassigned_rw() local
879 if (cmd == OUTPUT_MORE || cmd == OUTPUT_LAST || in dbdma_unassigned_rw()
[all …]
/qemu/tests/vm/
H A Dbasevm.py230 def _ssh_do(self, user, cmd, check): argument
245 assert not isinstance(cmd, str)
253 def ssh(self, *cmd): argument
256 def ssh_root(self, *cmd): argument
259 def ssh_check(self, *cmd): argument
262 def ssh_root_check(self, *cmd): argument
270 cmd.extend(list(args))
271 subprocess.check_call(cmd)
446 elif self.ssh(cmd) == 0:
661 cmd = args.commands
[all …]
/qemu/scripts/simplebench/
H A Dbench_block_job.py33 def bench_block_job(cmd, cmd_args, qemu_args): argument
56 res = vm.qmp(cmd, **cmd_args)
59 return {'error': '"{}" command failed: {}'.format(cmd, str(res))}
97 def bench_block_copy(qemu_binary, cmd, cmd_options, source, target): argument
99 assert cmd in ('blockdev-backup', 'blockdev-mirror')
121 return bench_block_job(cmd, cmd_options,
/qemu/hw/scsi/
H A Dspapr_vscsi.c238 uint8_t sol_not = iu->srp.cmd.sol_not; in vscsi_send_rsp()
298 struct srp_cmd *cmd = &req_iu(req)->srp.cmd; in vscsi_fetch_desc() local
466 uint8_t fmt = cmd->buf_fmt >> 4; in data_out_desc_size()
486 struct srp_cmd *cmd = &req_iu(req)->srp.cmd; in vscsi_preprocess_desc() local
488 req->cdb_offset = cmd->add_cdb_len & ~3; in vscsi_preprocess_desc()
491 req->dma_fmt = cmd->buf_fmt >> 4; in vscsi_preprocess_desc()
786 size_t cdb_len = sizeof (srp->cmd.cdb) + (srp->cmd.add_cdb_len & ~3); in vscsi_queue_cmd()
788 if ((srp->cmd.lun == 0 || be64_to_cpu(srp->cmd.lun) == SRP_REPORT_LUNS_WLUN) in vscsi_queue_cmd()
789 && srp->cmd.cdb[0] == REPORT_LUNS) { in vscsi_queue_cmd()
797 if (srp->cmd.cdb[0] == INQUIRY) { in vscsi_queue_cmd()
[all …]
/qemu/hw/ide/
H A Dahci.c144 val = pr->cmd; in ahci_port_read()
345 pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) | in ahci_port_write()
739 pr->cmd |= PORT_CMD_FIS_ON; in ahci_map_fis_address()
743 pr->cmd &= ~PORT_CMD_FIS_ON; in ahci_map_fis_address()
770 pr->cmd &= ~PORT_CMD_LIST_ON; in ahci_map_clb_address()
1096 switch (ncq_tfs->cmd) { in execute_ncq_command()
1327 cmd->status = 0; in handle_reg_h2d_fis()
1345 AHCICmdHdr *cmd; in handle_cmd() local
1361 s->dev[port].cur_cmd = cmd; in handle_cmd()
1745 if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) { in ahci_state_post_load()
[all …]
/qemu/scsi/
H A Dtrace-events4 pr_manager_execute(int fd, int cmd, int sa) "fd=%d cmd=0x%02x service action=0x%02x"
5 pr_manager_run(int fd, int cmd, int sa) "fd=%d cmd=0x%02x service action=0x%02x"
/qemu/hw/misc/
H A Dauxbus.c103 AUXReply aux_request(AUXBus *bus, AUXCommand cmd, uint32_t address, in aux_request() argument
111 cmd, len); in aux_request()
113 switch (cmd) { in aux_request()
122 cmd == WRITE_AUX)) { in aux_request()
186 (bus->last_transaction != cmd)) { in aux_request()
196 bus->last_transaction = cmd; in aux_request()
217 (bus->last_transaction != cmd)) { in aux_request()
227 bus->last_transaction = cmd; in aux_request()
235 qemu_log_mask(LOG_UNIMP, "AUX cmd=%u not implemented\n", cmd); in aux_request()
/qemu/contrib/vhost-user-gpu/
H A Dvugpu.h168 iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
179 struct virtio_gpu_ctrl_command *cmd,
184 struct virtio_gpu_ctrl_command *cmd,
189 struct virtio_gpu_ctrl_command *cmd,
192 void vg_get_display_info(VuGpu *vg, struct virtio_gpu_ctrl_command *cmd);
193 void vg_get_edid(VuGpu *vg, struct virtio_gpu_ctrl_command *cmd);
/qemu/hw/cxl/
H A Dcxl-mailbox-utils.c129 if (cmd->in < sizeof(*in)) { in cmd_tunnel_management_cmd()
222 if (cmd->in < sizeof(log_type)) { in cmd_events_get_records()
719 static CXLRetCode cmd_logs_get_log(const struct cxl_cmd *cmd, in cmd_logs_get_log() argument
853 static CXLRetCode cmd_ccls_get_lsa(const struct cxl_cmd *cmd, in cmd_ccls_get_lsa() argument
882 static CXLRetCode cmd_ccls_set_lsa(const struct cxl_cmd *cmd, in cmd_ccls_set_lsa() argument
1317 cxl_cmd = &cci->cxl_cmd_set[set][cmd]; in cxl_process_cci_message()
1321 set << 8 | cmd); in cxl_process_cci_message()
1362 cci->bg.opcode = (set << 8) | cmd; in cxl_process_cci_message()
1431 for (int cmd = 0; cmd < 256; cmd++) { in cxl_init_cci() local
1432 if (cci->cxl_cmd_set[set][cmd].handler) { in cxl_init_cci()
[all …]
/qemu/block/
H A Dnvme.c505 q->sq.tail * NVME_SQ_ENTRY_BYTES, cmd, sizeof(*cmd)); in nvme_submit_command()
551 NvmeCmd cmd = { in nvme_identify() local
591 cmd.cdw10 = 0; in nvme_identify()
674 NvmeCmd cmd; in nvme_add_io_queue() local
683 cmd = (NvmeCmd) { in nvme_add_io_queue()
693 cmd = (NvmeCmd) { in nvme_add_io_queue()
937 NvmeCmd cmd = { in nvme_enable_disable_write_cache() local
1196 NvmeCmd cmd = { in nvme_co_prw_aligned() local
1314 NvmeCmd cmd = { in nvme_co_flush() local
1362 NvmeCmd cmd = { in nvme_co_pwrite_zeroes() local
[all …]
/qemu/include/hw/virtio/
H A Dvirtio-gpu.h219 void (*process_cmd)(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
268 iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
295 struct virtio_gpu_ctrl_command *cmd,
299 struct virtio_gpu_ctrl_command *cmd,
302 struct virtio_gpu_ctrl_command *cmd);
304 struct virtio_gpu_ctrl_command *cmd);
307 struct virtio_gpu_ctrl_command *cmd,
317 void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
334 struct virtio_gpu_ctrl_command *cmd);
/qemu/backends/tpm/
H A Dtpm_backend.c33 s->cmd = NULL; in tpm_backend_request_completed()
43 k->handle_request(s, s->cmd, &err); in tpm_backend_worker_thread()
54 while (s->cmd) { in tpm_backend_finish_sync()
101 void tpm_backend_deliver_request(TPMBackend *s, TPMBackendCmd *cmd) in tpm_backend_deliver_request() argument
103 if (s->cmd != NULL) { in tpm_backend_deliver_request()
108 s->cmd = cmd; in tpm_backend_deliver_request()
/qemu/hw/remote/
H A Dmpqemu-link.c74 trace_mpqemu_send_io_error(msg->cmd, msg->size, nfds); in mpqemu_msg_send()
172 trace_mpqemu_recv_io_error(msg->cmd, msg->size, nfds); in mpqemu_msg_recv()
206 if (!mpqemu_msg_valid(&msg_reply) || msg_reply.cmd != MPQEMU_CMD_RET) { in mpqemu_msg_send_and_await_reply()
208 msg->cmd); in mpqemu_msg_send_and_await_reply()
217 if (msg->cmd >= MPQEMU_CMD_MAX || msg->cmd < 0) { in mpqemu_msg_valid()
235 switch (msg->cmd) { in mpqemu_msg_valid()

12345678910>>...17