/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | amdgpu_fence.c | 147 seq = ++ring->fence_drv.sync_seq; in amdgpu_fence_emit() 150 &ring->fence_drv.lock, in amdgpu_fence_emit() 156 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; in amdgpu_fence_emit() 301 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; in amdgpu_fence_wait_empty() 402 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); in amdgpu_fence_driver_start_ring() 427 ring->fence_drv.gpu_addr = 0; in amdgpu_fence_driver_init_ring() 428 ring->fence_drv.sync_seq = 0; in amdgpu_fence_driver_init_ring() 438 if (!ring->fence_drv.fences) in amdgpu_fence_driver_init_ring() 506 if (ring->fence_drv.irq_src) in amdgpu_fence_driver_fini() 544 if (ring->fence_drv.irq_src) in amdgpu_fence_driver_suspend() [all …]
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H A D | amdgpu_job.c | 37 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq), in amdgpu_job_timedout() 38 ring->fence_drv.sync_seq); in amdgpu_job_timedout()
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H A D | uvd_v6_0.c | 1074 uint32_t seq = ring->fence_drv.sync_seq; in uvd_v6_0_ring_emit_pipeline_sync() 1075 uint64_t addr = ring->fence_drv.gpu_addr; in uvd_v6_0_ring_emit_pipeline_sync() 1103 uint32_t seq = ring->fence_drv.sync_seq; in uvd_v6_0_enc_ring_emit_pipeline_sync() 1104 uint64_t addr = ring->fence_drv.gpu_addr; in uvd_v6_0_enc_ring_emit_pipeline_sync()
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H A D | amdgpu_ring.h | 176 struct amdgpu_fence_driver fence_drv; member
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H A D | vce_v3_0.c | 864 uint32_t seq = ring->fence_drv.sync_seq; in vce_v3_0_emit_pipeline_sync() 865 uint64_t addr = ring->fence_drv.gpu_addr; in vce_v3_0_emit_pipeline_sync()
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H A D | sdma_v2_4.c | 829 uint32_t seq = ring->fence_drv.sync_seq; in sdma_v2_4_ring_emit_pipeline_sync() 830 uint64_t addr = ring->fence_drv.gpu_addr; in sdma_v2_4_ring_emit_pipeline_sync()
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H A D | sdma_v3_0.c | 1101 uint32_t seq = ring->fence_drv.sync_seq; in sdma_v3_0_ring_emit_pipeline_sync() 1102 uint64_t addr = ring->fence_drv.gpu_addr; in sdma_v3_0_ring_emit_pipeline_sync()
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H A D | sdma_v4_0.c | 1169 uint32_t seq = ring->fence_drv.sync_seq; in sdma_v4_0_ring_emit_pipeline_sync() 1170 uint64_t addr = ring->fence_drv.gpu_addr; in sdma_v4_0_ring_emit_pipeline_sync()
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H A D | gfx_v9_0.c | 3999 uint32_t seq = ring->fence_drv.sync_seq; in gfx_v9_0_ring_emit_pipeline_sync() 4000 uint64_t addr = ring->fence_drv.gpu_addr; in gfx_v9_0_ring_emit_pipeline_sync()
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H A D | gfx_v8_0.c | 6444 uint32_t seq = ring->fence_drv.sync_seq; in gfx_v8_0_ring_emit_pipeline_sync() 6445 uint64_t addr = ring->fence_drv.gpu_addr; in gfx_v8_0_ring_emit_pipeline_sync()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | radeon_fence.c | 114 &rdev->fence_drv[ring].lockup_work, in radeon_fence_schedule_check() 270 struct radeon_fence_driver *fence_drv; in radeon_fence_check_lockup() local 276 rdev = fence_drv->rdev; in radeon_fence_check_lockup() 277 ring = fence_drv - &rdev->fence_drv[0]; in radeon_fence_check_lockup() 288 fence_drv->delayed_irq = false; in radeon_fence_check_lockup() 303 fence_drv->sync_seq[ring], ring); in radeon_fence_check_lockup() 854 rdev->fence_drv[ring].scratch_reg - in radeon_fence_driver_start_ring() 862 ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr); in radeon_fence_driver_start_ring() 882 rdev->fence_drv[ring].gpu_addr = 0; in radeon_fence_driver_init_ring() 889 rdev->fence_drv[ring].rdev = rdev; in radeon_fence_driver_init_ring() [all …]
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H A D | uvd_v2_2.c | 43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
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H A D | evergreen_dma.c | 43 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
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H A D | uvd_v1_0.c | 85 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v1_0_fence_emit()
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H A D | r600_dma.c | 289 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_dma_fence_ring_emit()
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H A D | radeon_vce.c | 739 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in radeon_vce_fence_emit()
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H A D | cik_sdma.c | 202 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_sdma_fence_ring_emit()
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H A D | r300.c | 232 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r300_fence_ring_emit()
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H A D | ni.c | 1415 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cayman_fence_ring_emit()
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H A D | r600.c | 2887 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_fence_ring_emit() 2916 …radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET… in r600_fence_ring_emit()
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H A D | radeon.h | 2383 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; member
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H A D | cik.c | 3584 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_fence_gfx_ring_emit() 3625 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_fence_compute_ring_emit()
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H A D | r100.c | 868 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r100_fence_ring_emit()
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H A D | si.c | 3364 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in si_fence_ring_emit()
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