| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/MIR/Hexagon/ |
| H A D | target-flags.mir | 8 ; CHECK: target-flags(hexagon-pcrel)
10 ; CHECK: target-flags(hexagon-got)
12 ; CHECK: target-flags(hexagon-lo16)
14 ; CHECK: target-flags(hexagon-hi16)
16 ; CHECK: target-flags(hexagon-gprel)
22 ; CHECK: target-flags(hexagon-ie)
29 ; CHECK: target-flags(hexagon-ext)
31 ; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
32 $r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
33 ; CHECK: target-flags(hexagon-ie, hexagon-ext)
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/Hexagon/intrinsics/ |
| H A D | xtype_bit.ll | 1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
8 declare i32 @llvm.hexagon.S2.clbp(i64)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
29 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
50 declare i32 @llvm.hexagon.S2.cl0(i32)
57 declare i32 @llvm.hexagon.S2.cl1(i32)
80 declare i32 @llvm.hexagon.S2.ct0p(i64)
87 declare i32 @llvm.hexagon.S2.ct1p(i64)
94 declare i32 @llvm.hexagon.S2.ct0(i32)
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/Hexagon/intrinsics/ |
| H A D | xtype_bit.ll | 1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
8 declare i32 @llvm.hexagon.S2.clbp(i64)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
29 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
50 declare i32 @llvm.hexagon.S2.cl0(i32)
57 declare i32 @llvm.hexagon.S2.cl1(i32)
80 declare i32 @llvm.hexagon.S2.ct0p(i64)
87 declare i32 @llvm.hexagon.S2.ct1p(i64)
94 declare i32 @llvm.hexagon.S2.ct0(i32)
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/Hexagon/intrinsics/ |
| H A D | xtype_bit.ll | 1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
8 declare i32 @llvm.hexagon.S2.clbp(i64)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
29 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
50 declare i32 @llvm.hexagon.S2.cl0(i32)
57 declare i32 @llvm.hexagon.S2.cl1(i32)
80 declare i32 @llvm.hexagon.S2.ct0p(i64)
87 declare i32 @llvm.hexagon.S2.ct1p(i64)
94 declare i32 @llvm.hexagon.S2.ct0(i32)
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/Hexagon/intrinsics/ |
| H A D | xtype_bit.ll | 1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
8 declare i32 @llvm.hexagon.S2.clbp(i64)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
29 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
50 declare i32 @llvm.hexagon.S2.cl0(i32)
57 declare i32 @llvm.hexagon.S2.cl1(i32)
80 declare i32 @llvm.hexagon.S2.ct0p(i64)
87 declare i32 @llvm.hexagon.S2.ct1p(i64)
94 declare i32 @llvm.hexagon.S2.ct0(i32)
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/intrinsics/ |
| H A D | xtype_bit.ll | 1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
8 declare i32 @llvm.hexagon.S2.clbp(i64)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
29 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
50 declare i32 @llvm.hexagon.S2.cl0(i32)
57 declare i32 @llvm.hexagon.S2.cl1(i32)
80 declare i32 @llvm.hexagon.S2.ct0p(i64)
87 declare i32 @llvm.hexagon.S2.ct1p(i64)
94 declare i32 @llvm.hexagon.S2.ct0(i32)
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Hexagon/intrinsics/ |
| H A D | xtype_bit.ll | 1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
8 declare i32 @llvm.hexagon.S2.clbp(i64)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
29 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
50 declare i32 @llvm.hexagon.S2.cl0(i32)
57 declare i32 @llvm.hexagon.S2.cl1(i32)
80 declare i32 @llvm.hexagon.S2.ct0p(i64)
87 declare i32 @llvm.hexagon.S2.ct1p(i64)
94 declare i32 @llvm.hexagon.S2.ct0(i32)
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/Hexagon/intrinsics/ |
| H A D | xtype_bit.ll | 1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
8 declare i32 @llvm.hexagon.S2.clbp(i64)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
29 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
50 declare i32 @llvm.hexagon.S2.cl0(i32)
57 declare i32 @llvm.hexagon.S2.cl1(i32)
80 declare i32 @llvm.hexagon.S2.ct0p(i64)
87 declare i32 @llvm.hexagon.S2.ct1p(i64)
94 declare i32 @llvm.hexagon.S2.ct0(i32)
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/Hexagon/intrinsics/ |
| H A D | xtype_bit.ll | 1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
8 declare i32 @llvm.hexagon.S2.clbp(i64)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
29 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
50 declare i32 @llvm.hexagon.S2.cl0(i32)
57 declare i32 @llvm.hexagon.S2.cl1(i32)
80 declare i32 @llvm.hexagon.S2.ct0p(i64)
87 declare i32 @llvm.hexagon.S2.ct1p(i64)
94 declare i32 @llvm.hexagon.S2.ct0(i32)
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Hexagon/intrinsics/ |
| H A D | xtype_bit.ll | 1 ; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
8 declare i32 @llvm.hexagon.S2.clbp(i64)
15 declare i32 @llvm.hexagon.S2.cl0p(i64)
22 declare i32 @llvm.hexagon.S2.cl1p(i64)
29 declare i32 @llvm.hexagon.S4.clbpnorm(i64)
50 declare i32 @llvm.hexagon.S2.cl0(i32)
57 declare i32 @llvm.hexagon.S2.cl1(i32)
80 declare i32 @llvm.hexagon.S2.ct0p(i64)
87 declare i32 @llvm.hexagon.S2.ct1p(i64)
94 declare i32 @llvm.hexagon.S2.ct0(i32)
[all …]
|