/dports/science/isaac-cfd/isaac-4.2_16/main/ |
H A D | main.F | 2134 CALL xCMGFF (idim(iblk,ilvl), 2135 1 jdim(iblk,ilvl), kdim(iblk,ilvl), 2139 CALL xCRESFF (idim(iblk,ilvl), 2140 1 jdim(iblk,ilvl), kdim(iblk,ilvl),
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/dports/math/py-yt/yt-4.0.1/yt/frontends/ramses/ |
H A D | particle_handlers.py | 263 for ilvl in range(self.ds.max_level + 1):
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/dports/emulators/simh/simh-3.9.0_5/PDP11/ |
H A D | pdp11_io_lib.c | 242 int32 i, idx, vec, ilvl, ibit; in build_ubus_tab() local 251 ilvl = idx / 32; in build_ubus_tab() 253 if ((int_ack[ilvl][ibit] && dibp->ack[i] && /* conflict? */ in build_ubus_tab() 254 (int_ack[ilvl][ibit] != dibp->ack[i])) || in build_ubus_tab() 255 (int_vec[ilvl][ibit] && vec && in build_ubus_tab() 256 (int_vec[ilvl][ibit] != vec))) { in build_ubus_tab() 265 int_ack[ilvl][ibit] = dibp->ack[i]; in build_ubus_tab() 267 int_vec[ilvl][ibit] = vec; in build_ubus_tab()
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/dports/deskutils/calibre/calibre-src-5.34.0/src/calibre/ebooks/docx/writer/ |
H A D | lists.py | 66 for ilvl, items in iteritems(self.level_map): 68 items_for_level[ilvl].append(list_tag) 69 container_for_level[ilvl] = container 70 type_for_level[ilvl] = list_type 72 Level(type_for_level[ilvl], container_for_level[ilvl], items_for_level[ilvl], ilvl=ilvl) 73 for ilvl in sorted(self.level_map) 80 for ilvl, items in iteritems(self.level_map): 82 block.numbering_id = (self.num_id + 1, ilvl) 96 self.ilvl = ilvl 110 self.lvl_text = '%{}.'.format(self.ilvl + 1) [all …]
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/dports/deskutils/calibre/calibre-src-5.34.0/src/calibre/ebooks/docx/ |
H A D | block_styles.py | 242 for ilvl in XPath('./w:ilvl[@w:val]')(np): 244 lvl = int(get(ilvl, 'w:val'))
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H A D | numbering.py | 73 if x > ilvl or x not in counter: 167 ilvl = 0 213 ilvl = None 223 ilvl = nilvl if ilvl is None else ilvl 265 return ilvl 275 for ilvl, lvl in iteritems(levels): 278 counter[ilvl] = lvl.start 282 for p, num_id, ilvl in items: 290 counter[ilvl] = self.starts[num_id][ilvl] 314 ilvl = int(start.get('list-lvl')) [all …]
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/dports/editors/libreoffice/libreoffice-7.2.6.2/ |
H A D | ChangeLog | 186122 tdf#133605: docx import: use ilvl value for list level import 186124 Previous implementation was not aware about ilvl value which 186128 we just override only one some random level (for example ilvl=2 241198 in DOCX export of MSO 2003, 2007 and 2010, where ilvl and outlinelvl 1212937 writerfilter: sprm:PI{lvl,lfo} -> ooxml:CT_NumPr_{ilvl,numId}
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/msa/ |
H A D | shuffle.ll | 891 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R1]] 906 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R1]] 921 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 936 ; ilvl.d and ilvod.d are equivalent for v2i64 952 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R2]] 966 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R2]] 980 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R2]] 994 ; ilvl.d and splati.d are equivalent for v2i64 1010 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R1]], [[R1]] 1024 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R1]], [[R1]] [all …]
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H A D | 3r-i.ll | 103 %2 = tail call <16 x i8> @llvm.mips.ilvl.b(<16 x i8> %0, <16 x i8> %1) 108 declare <16 x i8> @llvm.mips.ilvl.b(<16 x i8>, <16 x i8>) nounwind 113 ; CHECK: ilvl.b 125 %2 = tail call <8 x i16> @llvm.mips.ilvl.h(<8 x i16> %0, <8 x i16> %1) 130 declare <8 x i16> @llvm.mips.ilvl.h(<8 x i16>, <8 x i16>) nounwind 135 ; CHECK: ilvl.h 147 %2 = tail call <4 x i32> @llvm.mips.ilvl.w(<4 x i32> %0, <4 x i32> %1) 152 declare <4 x i32> @llvm.mips.ilvl.w(<4 x i32>, <4 x i32>) nounwind 157 ; CHECK: ilvl.w 174 declare <2 x i64> @llvm.mips.ilvl.d(<2 x i64>, <2 x i64>) nounwind [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Mips/ |
H A D | MipsMSAInstrInfo.td | 2245 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2246 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2247 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2248 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Mips/ |
H A D | MipsMSAInstrInfo.td | 2245 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2246 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2247 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2248 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/Mips/msa/ |
H A D | test_3r.s | 129 # CHECK: ilvl.b $w29, $w3, $w21 # encoding: [0x7a,0x15,0x1f,0x54] 130 # CHECK: ilvl.h $w27, $w10, $w17 # encoding: [0x7a,0x31,0x56,0xd4] 131 # CHECK: ilvl.w $w6, $w1, $w0 # encoding: [0x7a,0x40,0x09,0x94] 132 # CHECK: ilvl.d $w3, $w16, $w24 # encoding: [0x7a,0x78,0x80,0xd4] 372 ilvl.b $w29, $w3, $w21 373 ilvl.h $w27, $w10, $w17 374 ilvl.w $w6, $w1, $w0 375 ilvl.d $w3, $w16, $w24
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/msa/ |
H A D | shuffle.ll | 891 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R1]] 906 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R1]] 921 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 936 ; ilvl.d and ilvod.d are equivalent for v2i64 952 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R2]] 966 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R2]] 980 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R2]] 994 ; ilvl.d and splati.d are equivalent for v2i64 1010 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R1]], [[R1]] 1024 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R1]], [[R1]] [all …]
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H A D | 3r-i.ll | 103 %2 = tail call <16 x i8> @llvm.mips.ilvl.b(<16 x i8> %0, <16 x i8> %1) 108 declare <16 x i8> @llvm.mips.ilvl.b(<16 x i8>, <16 x i8>) nounwind 113 ; CHECK: ilvl.b 125 %2 = tail call <8 x i16> @llvm.mips.ilvl.h(<8 x i16> %0, <8 x i16> %1) 130 declare <8 x i16> @llvm.mips.ilvl.h(<8 x i16>, <8 x i16>) nounwind 135 ; CHECK: ilvl.h 147 %2 = tail call <4 x i32> @llvm.mips.ilvl.w(<4 x i32> %0, <4 x i32> %1) 152 declare <4 x i32> @llvm.mips.ilvl.w(<4 x i32>, <4 x i32>) nounwind 157 ; CHECK: ilvl.w 174 declare <2 x i64> @llvm.mips.ilvl.d(<2 x i64>, <2 x i64>) nounwind [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Mips/ |
H A D | MipsMSAInstrInfo.td | 2245 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2246 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2247 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2248 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/Mips/msa/ |
H A D | test_3r.s | 129 # CHECK: ilvl.b $w29, $w3, $w21 # encoding: [0x7a,0x15,0x1f,0x54] 130 # CHECK: ilvl.h $w27, $w10, $w17 # encoding: [0x7a,0x31,0x56,0xd4] 131 # CHECK: ilvl.w $w6, $w1, $w0 # encoding: [0x7a,0x40,0x09,0x94] 132 # CHECK: ilvl.d $w3, $w16, $w24 # encoding: [0x7a,0x78,0x80,0xd4] 372 ilvl.b $w29, $w3, $w21 373 ilvl.h $w27, $w10, $w17 374 ilvl.w $w6, $w1, $w0 375 ilvl.d $w3, $w16, $w24
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Mips/ |
H A D | MipsMSAInstrInfo.td | 2245 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2246 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2247 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2248 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/Mips/msa/ |
H A D | 3r-i.ll | 103 %2 = tail call <16 x i8> @llvm.mips.ilvl.b(<16 x i8> %0, <16 x i8> %1) 108 declare <16 x i8> @llvm.mips.ilvl.b(<16 x i8>, <16 x i8>) nounwind 113 ; CHECK: ilvl.b 125 %2 = tail call <8 x i16> @llvm.mips.ilvl.h(<8 x i16> %0, <8 x i16> %1) 130 declare <8 x i16> @llvm.mips.ilvl.h(<8 x i16>, <8 x i16>) nounwind 135 ; CHECK: ilvl.h 147 %2 = tail call <4 x i32> @llvm.mips.ilvl.w(<4 x i32> %0, <4 x i32> %1) 152 declare <4 x i32> @llvm.mips.ilvl.w(<4 x i32>, <4 x i32>) nounwind 157 ; CHECK: ilvl.w 174 declare <2 x i64> @llvm.mips.ilvl.d(<2 x i64>, <2 x i64>) nounwind [all …]
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H A D | shuffle.ll | 891 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R1]] 906 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R1]] 921 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 936 ; ilvl.d and ilvod.d are equivalent for v2i64 952 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R2]] 966 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R2]] 980 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R2]] 994 ; ilvl.d and splati.d are equivalent for v2i64 1010 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R1]], [[R1]] 1024 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R1]], [[R1]] [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/Mips/msa/ |
H A D | test_3r.s | 129 # CHECK: ilvl.b $w29, $w3, $w21 # encoding: [0x7a,0x15,0x1f,0x54] 130 # CHECK: ilvl.h $w27, $w10, $w17 # encoding: [0x7a,0x31,0x56,0xd4] 131 # CHECK: ilvl.w $w6, $w1, $w0 # encoding: [0x7a,0x40,0x09,0x94] 132 # CHECK: ilvl.d $w3, $w16, $w24 # encoding: [0x7a,0x78,0x80,0xd4] 372 ilvl.b $w29, $w3, $w21 373 ilvl.h $w27, $w10, $w17 374 ilvl.w $w6, $w1, $w0 375 ilvl.d $w3, $w16, $w24
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/Mips/msa/ |
H A D | test_3r.s | 129 # CHECK: ilvl.b $w29, $w3, $w21 # encoding: [0x7a,0x15,0x1f,0x54] 130 # CHECK: ilvl.h $w27, $w10, $w17 # encoding: [0x7a,0x31,0x56,0xd4] 131 # CHECK: ilvl.w $w6, $w1, $w0 # encoding: [0x7a,0x40,0x09,0x94] 132 # CHECK: ilvl.d $w3, $w16, $w24 # encoding: [0x7a,0x78,0x80,0xd4] 372 ilvl.b $w29, $w3, $w21 373 ilvl.h $w27, $w10, $w17 374 ilvl.w $w6, $w1, $w0 375 ilvl.d $w3, $w16, $w24
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/Mips/msa/ |
H A D | 3r-i.ll | 103 %2 = tail call <16 x i8> @llvm.mips.ilvl.b(<16 x i8> %0, <16 x i8> %1) 108 declare <16 x i8> @llvm.mips.ilvl.b(<16 x i8>, <16 x i8>) nounwind 113 ; CHECK: ilvl.b 125 %2 = tail call <8 x i16> @llvm.mips.ilvl.h(<8 x i16> %0, <8 x i16> %1) 130 declare <8 x i16> @llvm.mips.ilvl.h(<8 x i16>, <8 x i16>) nounwind 135 ; CHECK: ilvl.h 147 %2 = tail call <4 x i32> @llvm.mips.ilvl.w(<4 x i32> %0, <4 x i32> %1) 152 declare <4 x i32> @llvm.mips.ilvl.w(<4 x i32>, <4 x i32>) nounwind 157 ; CHECK: ilvl.w 174 declare <2 x i64> @llvm.mips.ilvl.d(<2 x i64>, <2 x i64>) nounwind [all …]
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H A D | shuffle.ll | 891 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R1]] 906 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R1]] 921 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R1]] 936 ; ilvl.d and ilvod.d are equivalent for v2i64 952 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R2]], [[R2]] 966 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R2]], [[R2]] 980 ; CHECK-DAG: ilvl.w [[R3:\$w[0-9]+]], [[R2]], [[R2]] 994 ; ilvl.d and splati.d are equivalent for v2i64 1010 ; CHECK-DAG: ilvl.b [[R3:\$w[0-9]+]], [[R1]], [[R1]] 1024 ; CHECK-DAG: ilvl.h [[R3:\$w[0-9]+]], [[R1]], [[R1]] [all …]
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/dports/lang/rust/rustc-1.58.1-src/library/stdarch/crates/core_arch/src/mips/ |
H A D | msa.rs | 5401 #[cfg_attr(test, assert_instr(ilvl.b))] 5415 #[cfg_attr(test, assert_instr(ilvl.h))] 5429 #[cfg_attr(test, assert_instr(ilvl.w))] 5443 #[cfg_attr(test, assert_instr(ilvl.d))]
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/dports/editors/neovim/neovim-0.6.1/src/nvim/ |
H A D | marktree.c | 334 int ilvl = itr->lvl-1; in marktree_del_itr() local 338 if (ilvl < 0) { in marktree_del_itr() 341 const int i = itr->s[ilvl].i; in marktree_del_itr() 347 ilvl--; in marktree_del_itr()
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