Searched refs:initial_state (Results 1 – 6 of 6) sorted by relevance
/dragonfly/sys/dev/drm/radeon/ |
H A D | rv730_dpm.c | 323 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); in rv730_populate_smc_initial_state() local 343 cpu_to_be32(initial_state->low.mclk); in rv730_populate_smc_initial_state() 357 cpu_to_be32(initial_state->low.sclk); in rv730_populate_smc_initial_state() 362 rv770_get_seq_value(rdev, &initial_state->low); in rv730_populate_smc_initial_state() 365 initial_state->low.vddc, in rv730_populate_smc_initial_state() 380 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in rv730_populate_smc_initial_state()
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H A D | cypress_dpm.c | 1238 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state); in cypress_populate_smc_initial_state() local 1262 cpu_to_be32(initial_state->low.mclk); in cypress_populate_smc_initial_state() 1276 cpu_to_be32(initial_state->low.sclk); in cypress_populate_smc_initial_state() 1284 initial_state->low.vddc, in cypress_populate_smc_initial_state() 1290 initial_state->low.vddci, in cypress_populate_smc_initial_state() 1306 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in cypress_populate_smc_initial_state() 1314 initial_state->low.mclk); in cypress_populate_smc_initial_state() 1316 if (initial_state->low.mclk > pi->mclk_edc_enable_threshold) in cypress_populate_smc_initial_state()
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H A D | rv770_dpm.c | 1031 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); in rv770_populate_smc_initial_state() local 1054 cpu_to_be32(initial_state->low.mclk); in rv770_populate_smc_initial_state() 1068 cpu_to_be32(initial_state->low.sclk); in rv770_populate_smc_initial_state() 1073 rv770_get_seq_value(rdev, &initial_state->low); in rv770_populate_smc_initial_state() 1076 initial_state->low.vddc, in rv770_populate_smc_initial_state() 1090 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) in rv770_populate_smc_initial_state() 1097 if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold) in rv770_populate_smc_initial_state() 1099 rv740_get_mclk_frequency_ratio(initial_state->low.mclk) | 0x10; in rv770_populate_smc_initial_state() 1103 if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold) in rv770_populate_smc_initial_state()
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H A D | ni_dpm.c | 1683 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); in ni_populate_smc_initial_state() local 1707 cpu_to_be32(initial_state->performance_levels[0].mclk); in ni_populate_smc_initial_state() 1722 cpu_to_be32(initial_state->performance_levels[0].sclk); in ni_populate_smc_initial_state() 1729 initial_state->performance_levels[0].vddc, in ni_populate_smc_initial_state() 1746 initial_state->performance_levels[0].vddci, in ni_populate_smc_initial_state() 1764 initial_state->performance_levels[0].mclk); in ni_populate_smc_initial_state() 1766 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in ni_populate_smc_initial_state()
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H A D | si_dpm.c | 4368 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); in si_populate_smc_initial_state() local 4395 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state() 4411 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state() 4419 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state() 4437 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state() 4443 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state() 4444 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state() 4445 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state() 4460 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state() 4462 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | si_dpm.c | 4833 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); in si_populate_smc_initial_state() local 4860 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state() 4876 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state() 4884 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state() 4902 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state() 4908 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state() 4909 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state() 4910 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state() 4923 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state() 4925 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
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