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/dports/java/openjdk16/jdk16u-jdk-16.0.2-7-1/test/jdk/jdk/incubator/vector/templates/
H A DKernel-Get-op.template11 r[i]=av.lane(0);
13 r[i]=av.lane(0);
14 r[i+1]=av.lane(1);
16 r[i]=av.lane(0);
17 r[i+1]=av.lane(1);
18 r[i+2]=av.lane(2);
19 r[i+3]=av.lane(3);
21 r[i]=av.lane(0);
22 r[i+1]=av.lane(1);
30 r[i]=av.lane(0);
[all …]
/dports/java/openjdk17/jdk17u-jdk-17.0.1-12-1/test/jdk/jdk/incubator/vector/templates/
H A DKernel-Get-op.template11 r[i]=av.lane(0);
13 r[i]=av.lane(0);
14 r[i+1]=av.lane(1);
16 r[i]=av.lane(0);
17 r[i+1]=av.lane(1);
18 r[i+2]=av.lane(2);
19 r[i+3]=av.lane(3);
21 r[i]=av.lane(0);
22 r[i+1]=av.lane(1);
30 r[i]=av.lane(0);
[all …]
/dports/devel/simde/simde-0.7.2/simde/arm/neon/
H A Ddup_lane.h52 #define simde_vdup_lane_f32(vec, lane) vdup_lane_f32(vec, lane) argument
56 #define vdup_lane_f32(vec, lane) simde_vdup_lane_f32((vec), (lane)) argument
63 (void) lane; in simde_vdup_lane_f64()
68 #define vdup_lane_f64(vec, lane) simde_vdup_lane_f64((vec), (lane)) argument
87 #define simde_vdup_lane_s8(vec, lane) vdup_lane_s8(vec, lane) argument
91 #define vdup_lane_s8(vec, lane) simde_vdup_lane_s8((vec), (lane)) argument
110 #define simde_vdup_lane_s16(vec, lane) vdup_lane_s16(vec, lane) argument
133 #define simde_vdup_lane_s32(vec, lane) vdup_lane_s32(vec, lane) argument
156 #define simde_vdup_lane_s64(vec, lane) vdup_lane_s64(vec, lane) argument
179 #define simde_vdup_lane_u8(vec, lane) vdup_lane_u8(vec, lane) argument
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H A Dget_lane.h55 #define vget_lane_f32(v, lane) simde_vget_lane_f32((v), (lane)) argument
65 (void) lane; in simde_vget_lane_f64()
77 #define vget_lane_f64(v, lane) simde_vget_lane_f64((v), (lane)) argument
98 #define vget_lane_s8(v, lane) simde_vget_lane_s8((v), (lane)) argument
119 #define vget_lane_s16(v, lane) simde_vget_lane_s16((v), (lane)) argument
140 #define vget_lane_s32(v, lane) simde_vget_lane_s32((v), (lane)) argument
150 (void) lane; in simde_vget_lane_s64()
162 #define vget_lane_s64(v, lane) simde_vget_lane_s64((v), (lane)) argument
183 #define vget_lane_u8(v, lane) simde_vget_lane_u8((v), (lane)) argument
204 #define vget_lane_u16(v, lane) simde_vget_lane_u16((v), (lane)) argument
[all …]
H A Dmul_lane.h54 #define simde_vmul_lane_f32(a, b, lane) vmul_lane_f32((a), (b), (lane)) argument
58 #define vmul_lane_f32(a, b, lane) simde_vmul_lane_f32((a), (b), (lane)) argument
78 #define simde_vmul_lane_f64(a, b, lane) vmul_lane_f64((a), (b), (lane)) argument
82 #define vmul_lane_f64(a, b, lane) simde_vmul_lane_f64((a), (b), (lane)) argument
102 #define simde_vmul_lane_s16(a, b, lane) vmul_lane_s16((a), (b), (lane)) argument
106 #define vmul_lane_s16(a, b, lane) simde_vmul_lane_s16((a), (b), (lane)) argument
126 #define simde_vmul_lane_s32(a, b, lane) vmul_lane_s32((a), (b), (lane)) argument
130 #define vmul_lane_s32(a, b, lane) simde_vmul_lane_s32((a), (b), (lane)) argument
150 #define simde_vmul_lane_u16(a, b, lane) vmul_lane_u16((a), (b), (lane)) argument
154 #define vmul_lane_u16(a, b, lane) simde_vmul_lane_u16((a), (b), (lane)) argument
[all …]
H A Dst1_lane.h44 *ptr = val_.values[lane]; in simde_vst1_lane_f32()
57 (void) lane; in simde_vst1_lane_f64()
61 *ptr = val_.values[lane]; in simde_vst1_lane_f64()
77 *ptr = val_.values[lane]; in simde_vst1_lane_s8()
93 *ptr = val_.values[lane]; in simde_vst1_lane_s16()
109 *ptr = val_.values[lane]; in simde_vst1_lane_s32()
122 (void) lane; in simde_vst1_lane_s64()
126 *ptr = val_.values[lane]; in simde_vst1_lane_s64()
142 *ptr = val_.values[lane]; in simde_vst1_lane_u8()
158 *ptr = val_.values[lane]; in simde_vst1_lane_u16()
[all …]
/dports/biology/bowtie2/simde-no-tests-f6a0b3b/arm/neon/
H A Ddup_lane.h52 #define simde_vdup_lane_f32(vec, lane) vdup_lane_f32(vec, lane) argument
56 #define vdup_lane_f32(vec, lane) simde_vdup_lane_f32((vec), (lane)) argument
63 (void) lane; in simde_vdup_lane_f64()
68 #define vdup_lane_f64(vec, lane) simde_vdup_lane_f64((vec), (lane)) argument
87 #define simde_vdup_lane_s8(vec, lane) vdup_lane_s8(vec, lane) argument
91 #define vdup_lane_s8(vec, lane) simde_vdup_lane_s8((vec), (lane)) argument
110 #define simde_vdup_lane_s16(vec, lane) vdup_lane_s16(vec, lane) argument
133 #define simde_vdup_lane_s32(vec, lane) vdup_lane_s32(vec, lane) argument
156 #define simde_vdup_lane_s64(vec, lane) vdup_lane_s64(vec, lane) argument
179 #define simde_vdup_lane_u8(vec, lane) vdup_lane_u8(vec, lane) argument
[all …]
H A Dget_lane.h55 #define vget_lane_f32(v, lane) simde_vget_lane_f32((v), (lane)) argument
65 (void) lane; in simde_vget_lane_f64()
77 #define vget_lane_f64(v, lane) simde_vget_lane_f64((v), (lane)) argument
98 #define vget_lane_s8(v, lane) simde_vget_lane_s8((v), (lane)) argument
119 #define vget_lane_s16(v, lane) simde_vget_lane_s16((v), (lane)) argument
140 #define vget_lane_s32(v, lane) simde_vget_lane_s32((v), (lane)) argument
150 (void) lane; in simde_vget_lane_s64()
162 #define vget_lane_s64(v, lane) simde_vget_lane_s64((v), (lane)) argument
183 #define vget_lane_u8(v, lane) simde_vget_lane_u8((v), (lane)) argument
204 #define vget_lane_u16(v, lane) simde_vget_lane_u16((v), (lane)) argument
[all …]
H A Dmul_lane.h54 #define simde_vmul_lane_f32(a, b, lane) vmul_lane_f32((a), (b), (lane)) argument
58 #define vmul_lane_f32(a, b, lane) simde_vmul_lane_f32((a), (b), (lane)) argument
78 #define simde_vmul_lane_f64(a, b, lane) vmul_lane_f64((a), (b), (lane)) argument
82 #define vmul_lane_f64(a, b, lane) simde_vmul_lane_f64((a), (b), (lane)) argument
102 #define simde_vmul_lane_s16(a, b, lane) vmul_lane_s16((a), (b), (lane)) argument
106 #define vmul_lane_s16(a, b, lane) simde_vmul_lane_s16((a), (b), (lane)) argument
126 #define simde_vmul_lane_s32(a, b, lane) vmul_lane_s32((a), (b), (lane)) argument
130 #define vmul_lane_s32(a, b, lane) simde_vmul_lane_s32((a), (b), (lane)) argument
150 #define simde_vmul_lane_u16(a, b, lane) vmul_lane_u16((a), (b), (lane)) argument
154 #define vmul_lane_u16(a, b, lane) simde_vmul_lane_u16((a), (b), (lane)) argument
[all …]
H A Dst1_lane.h44 *ptr = val_.values[lane]; in simde_vst1_lane_f32()
57 (void) lane; in simde_vst1_lane_f64()
61 *ptr = val_.values[lane]; in simde_vst1_lane_f64()
77 *ptr = val_.values[lane]; in simde_vst1_lane_s8()
93 *ptr = val_.values[lane]; in simde_vst1_lane_s16()
109 *ptr = val_.values[lane]; in simde_vst1_lane_s32()
122 (void) lane; in simde_vst1_lane_s64()
126 *ptr = val_.values[lane]; in simde_vst1_lane_s64()
142 *ptr = val_.values[lane]; in simde_vst1_lane_u8()
158 *ptr = val_.values[lane]; in simde_vst1_lane_u16()
[all …]
/dports/biology/mmseqs2/MMseqs2-13-45111/lib/simde/simde/arm/neon/
H A Ddup_lane.h52 #define simde_vdup_lane_f32(vec, lane) vdup_lane_f32(vec, lane) argument
56 #define vdup_lane_f32(vec, lane) simde_vdup_lane_f32((vec), (lane)) argument
63 (void) lane; in simde_vdup_lane_f64()
68 #define vdup_lane_f64(vec, lane) simde_vdup_lane_f64((vec), (lane)) argument
87 #define simde_vdup_lane_s8(vec, lane) vdup_lane_s8(vec, lane) argument
91 #define vdup_lane_s8(vec, lane) simde_vdup_lane_s8((vec), (lane)) argument
110 #define simde_vdup_lane_s16(vec, lane) vdup_lane_s16(vec, lane) argument
133 #define simde_vdup_lane_s32(vec, lane) vdup_lane_s32(vec, lane) argument
156 #define simde_vdup_lane_s64(vec, lane) vdup_lane_s64(vec, lane) argument
179 #define simde_vdup_lane_u8(vec, lane) vdup_lane_u8(vec, lane) argument
[all …]
H A Dget_lane.h55 #define vget_lane_f32(v, lane) simde_vget_lane_f32((v), (lane)) argument
65 (void) lane; in simde_vget_lane_f64()
77 #define vget_lane_f64(v, lane) simde_vget_lane_f64((v), (lane)) argument
98 #define vget_lane_s8(v, lane) simde_vget_lane_s8((v), (lane)) argument
119 #define vget_lane_s16(v, lane) simde_vget_lane_s16((v), (lane)) argument
140 #define vget_lane_s32(v, lane) simde_vget_lane_s32((v), (lane)) argument
150 (void) lane; in simde_vget_lane_s64()
162 #define vget_lane_s64(v, lane) simde_vget_lane_s64((v), (lane)) argument
183 #define vget_lane_u8(v, lane) simde_vget_lane_u8((v), (lane)) argument
204 #define vget_lane_u16(v, lane) simde_vget_lane_u16((v), (lane)) argument
[all …]
H A Dmul_lane.h54 #define simde_vmul_lane_f32(a, b, lane) vmul_lane_f32((a), (b), (lane)) argument
58 #define vmul_lane_f32(a, b, lane) simde_vmul_lane_f32((a), (b), (lane)) argument
78 #define simde_vmul_lane_f64(a, b, lane) vmul_lane_f64((a), (b), (lane)) argument
82 #define vmul_lane_f64(a, b, lane) simde_vmul_lane_f64((a), (b), (lane)) argument
102 #define simde_vmul_lane_s16(a, b, lane) vmul_lane_s16((a), (b), (lane)) argument
106 #define vmul_lane_s16(a, b, lane) simde_vmul_lane_s16((a), (b), (lane)) argument
126 #define simde_vmul_lane_s32(a, b, lane) vmul_lane_s32((a), (b), (lane)) argument
130 #define vmul_lane_s32(a, b, lane) simde_vmul_lane_s32((a), (b), (lane)) argument
150 #define simde_vmul_lane_u16(a, b, lane) vmul_lane_u16((a), (b), (lane)) argument
154 #define vmul_lane_u16(a, b, lane) simde_vmul_lane_u16((a), (b), (lane)) argument
[all …]
H A Dst1_lane.h44 *ptr = val_.values[lane]; in simde_vst1_lane_f32()
57 (void) lane; in simde_vst1_lane_f64()
61 *ptr = val_.values[lane]; in simde_vst1_lane_f64()
77 *ptr = val_.values[lane]; in simde_vst1_lane_s8()
93 *ptr = val_.values[lane]; in simde_vst1_lane_s16()
109 *ptr = val_.values[lane]; in simde_vst1_lane_s32()
122 (void) lane; in simde_vst1_lane_s64()
126 *ptr = val_.values[lane]; in simde_vst1_lane_s64()
142 *ptr = val_.values[lane]; in simde_vst1_lane_u8()
158 *ptr = val_.values[lane]; in simde_vst1_lane_u16()
[all …]
/dports/biology/vcflib/vcflib-1.0.2/src/simde/arm/neon/
H A Dget_lane.h55 #define vget_lane_f32(v, lane) simde_vget_lane_f32((v), (lane)) argument
65 (void) lane; in simde_vget_lane_f64()
77 #define vget_lane_f64(v, lane) simde_vget_lane_f64((v), (lane)) argument
98 #define vget_lane_s8(v, lane) simde_vget_lane_s8((v), (lane)) argument
119 #define vget_lane_s16(v, lane) simde_vget_lane_s16((v), (lane)) argument
140 #define vget_lane_s32(v, lane) simde_vget_lane_s32((v), (lane)) argument
150 (void) lane; in simde_vget_lane_s64()
162 #define vget_lane_s64(v, lane) simde_vget_lane_s64((v), (lane)) argument
183 #define vget_lane_u8(v, lane) simde_vget_lane_u8((v), (lane)) argument
204 #define vget_lane_u16(v, lane) simde_vget_lane_u16((v), (lane)) argument
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/dports/biology/freebayes/freebayes-1.3.5/vcflib/src/simde/arm/neon/
H A Dget_lane.h55 #define vget_lane_f32(v, lane) simde_vget_lane_f32((v), (lane)) argument
65 (void) lane; in simde_vget_lane_f64()
77 #define vget_lane_f64(v, lane) simde_vget_lane_f64((v), (lane)) argument
98 #define vget_lane_s8(v, lane) simde_vget_lane_s8((v), (lane)) argument
119 #define vget_lane_s16(v, lane) simde_vget_lane_s16((v), (lane)) argument
140 #define vget_lane_s32(v, lane) simde_vget_lane_s32((v), (lane)) argument
150 (void) lane; in simde_vget_lane_s64()
162 #define vget_lane_s64(v, lane) simde_vget_lane_s64((v), (lane)) argument
183 #define vget_lane_u8(v, lane) simde_vget_lane_u8((v), (lane)) argument
204 #define vget_lane_u16(v, lane) simde_vget_lane_u16((v), (lane)) argument
[all …]
/dports/biology/hhsuite/hh-suite-3.3.0/lib/simde/simde/arm/neon/
H A Dget_lane.h55 #define vget_lane_f32(v, lane) simde_vget_lane_f32((v), (lane)) argument
65 (void) lane; in simde_vget_lane_f64()
77 #define vget_lane_f64(v, lane) simde_vget_lane_f64((v), (lane)) argument
98 #define vget_lane_s8(v, lane) simde_vget_lane_s8((v), (lane)) argument
119 #define vget_lane_s16(v, lane) simde_vget_lane_s16((v), (lane)) argument
140 #define vget_lane_s32(v, lane) simde_vget_lane_s32((v), (lane)) argument
150 (void) lane; in simde_vget_lane_s64()
162 #define vget_lane_s64(v, lane) simde_vget_lane_s64((v), (lane)) argument
183 #define vget_lane_u8(v, lane) simde_vget_lane_u8((v), (lane)) argument
204 #define vget_lane_u16(v, lane) simde_vget_lane_u16((v), (lane)) argument
[all …]
/dports/graphics/openshadinglanguage/OpenShadingLanguage-Release-1.11.15.0/src/include/OSL/
H A Dwide.h208 get(int lane) const in alignas()
214 operator[](int lane) in alignas()
329 get(int lane) const
346 operator[](int lane)
465 get(int lane) const
480 operator[](int lane)
586 get(int lane) const
701 get(int lane) const
860 get(int lane) const
936 get(int lane) const
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/dports/graphics/py-openshadinglanguage/OpenShadingLanguage-Release-1.11.15.0/src/include/OSL/
H A Dwide.h208 get(int lane) const in alignas()
214 operator[](int lane) in alignas()
329 get(int lane) const
346 operator[](int lane)
465 get(int lane) const
480 operator[](int lane)
586 get(int lane) const
701 get(int lane) const
860 get(int lane) const
936 get(int lane) const
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c180 unsigned lane; member
304 if (conf->lane == lane && in mvebu_comphy_get_mode()
376 lane->id); in mvebu_comphy_ethernet_init_reset()
397 lane->id); in mvebu_comphy_ethernet_init_reset()
724 mux = mvebu_comphy_get_mux(lane->id, lane->port, in mvebu_comphy_power_on_legacy()
725 lane->mode, lane->submode); in mvebu_comphy_power_on_legacy()
769 fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port, in mvebu_comphy_power_on()
770 lane->mode, lane->submode); in mvebu_comphy_power_on()
780 lane->id); in mvebu_comphy_power_on()
785 lane->id); in mvebu_comphy_power_on()
[all …]
H A Dphy-mvebu-a3700-comphy.c58 unsigned int lane; member
140 if (mvebu_a3700_comphy_modes[i].lane == lane && in mvebu_a3700_comphy_get_fw_mode()
183 fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, in mvebu_a3700_comphy_power_on()
184 lane->mode, lane->submode); in mvebu_a3700_comphy_power_on()
196 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); in mvebu_a3700_comphy_power_on()
203 lane->id); in mvebu_a3700_comphy_power_on()
209 lane->id); in mvebu_a3700_comphy_power_on()
220 dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id); in mvebu_a3700_comphy_power_on()
226 dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode); in mvebu_a3700_comphy_power_on()
294 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); in mvebu_a3700_comphy_probe()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c180 unsigned lane; member
304 if (conf->lane == lane && in mvebu_comphy_get_mode()
376 lane->id); in mvebu_comphy_ethernet_init_reset()
397 lane->id); in mvebu_comphy_ethernet_init_reset()
724 mux = mvebu_comphy_get_mux(lane->id, lane->port, in mvebu_comphy_power_on_legacy()
725 lane->mode, lane->submode); in mvebu_comphy_power_on_legacy()
769 fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port, in mvebu_comphy_power_on()
770 lane->mode, lane->submode); in mvebu_comphy_power_on()
780 lane->id); in mvebu_comphy_power_on()
785 lane->id); in mvebu_comphy_power_on()
[all …]
H A Dphy-mvebu-a3700-comphy.c58 unsigned int lane; member
140 if (mvebu_a3700_comphy_modes[i].lane == lane && in mvebu_a3700_comphy_get_fw_mode()
183 fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, in mvebu_a3700_comphy_power_on()
184 lane->mode, lane->submode); in mvebu_a3700_comphy_power_on()
196 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); in mvebu_a3700_comphy_power_on()
203 lane->id); in mvebu_a3700_comphy_power_on()
209 lane->id); in mvebu_a3700_comphy_power_on()
220 dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id); in mvebu_a3700_comphy_power_on()
226 dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode); in mvebu_a3700_comphy_power_on()
294 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); in mvebu_a3700_comphy_probe()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c180 unsigned lane; member
304 if (conf->lane == lane && in mvebu_comphy_get_mode()
376 lane->id); in mvebu_comphy_ethernet_init_reset()
397 lane->id); in mvebu_comphy_ethernet_init_reset()
724 mux = mvebu_comphy_get_mux(lane->id, lane->port, in mvebu_comphy_power_on_legacy()
725 lane->mode, lane->submode); in mvebu_comphy_power_on_legacy()
769 fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port, in mvebu_comphy_power_on()
770 lane->mode, lane->submode); in mvebu_comphy_power_on()
780 lane->id); in mvebu_comphy_power_on()
785 lane->id); in mvebu_comphy_power_on()
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dvectorize-free-extracts-inserts.ll37 %a.lane.0 = fmul double %v1.lane.0, %v2.lane.2
38 %a.lane.1 = fmul double %v1.lane.1, %v2.lane.3
79 %a.lane.0 = fmul double %v1.lane.0, %v2.lane.2
80 %a.lane.1 = fmul double %v3.lane.1, %v2.lane.2
121 %a.lane.0 = fmul double %v1.lane.2, %v2.lane.2
122 %a.lane.1 = fmul double %v1.lane.3, %v2.lane.2
160 %a.lane.0 = fmul double %v1.lane.1, %v2.lane.2
161 %a.lane.1 = fmul double %v1.lane.0, %v2.lane.2
201 %a.lane.0 = fmul double %v1.lane.1, %v2.lane.2
202 %a.lane.1 = fmul double %v1.lane.2, %v2.lane.2
[all …]

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