/qemu/target/tricore/ |
H A D | tricore-opcodes.h | 34 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7) argument 92 #define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op) argument 156 #define MASK_OP_RC_D(op) MASK_OP_META_D(op) argument 160 #define MASK_OP_RC_S1(op) MASK_OP_META_S1(op) argument 164 #define MASK_OP_RCPW_D(op) MASK_OP_META_D(op) argument 173 #define MASK_OP_RCR_D(op) MASK_OP_META_D(op) argument 178 #define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op) argument 182 #define MASK_OP_RCRR_D(op) MASK_OP_META_D(op) argument 190 #define MASK_OP_RCRW_D(op) MASK_OP_META_D(op) argument 199 #define MASK_OP_RLC_D(op) MASK_OP_META_D(op) argument [all …]
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/qemu/tcg/ |
H A D | optimize.c | 1037 swap_commutative(op->args[0], &op->args[1], &op->args[2]); in fold_commutative() 1043 swap_commutative(op->args[0], &op->args[1], &op->args[2]); in fold_const2_commutative() 1072 return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); in fold_masks() 1145 return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); in fold_xi_to_x() 1172 return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); in fold_xx_to_x() 1275 swap_commutative(op->args[0], &op->args[2], &op->args[4]); in fold_add2() 1276 swap_commutative(op->args[1], &op->args[3], &op->args[5]); in fold_add2() 1353 op->args[0] = op->args[3]; in fold_brcond() 1426 op->args[1] = op->args[2]; in fold_brcond2() 1847 return tcg_opt_gen_mov(ctx, op, op->args[0], op->args[1]); in fold_mov() [all …]
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H A D | tcg-internal.h | 42 static inline void *tcg_call_func(TCGOp *op) in tcg_call_func() argument 44 return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op)]; in tcg_call_func() 47 static inline const TCGHelperInfo *tcg_call_info(TCGOp *op) in tcg_call_info() argument 49 return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1]; in tcg_call_info() 52 static inline unsigned tcg_call_flags(TCGOp *op) in tcg_call_flags() argument 54 return tcg_call_info(op)->flags; in tcg_call_flags()
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H A D | tcg.c | 1324 for(op = 0; op < NB_OPS; op++) { in tcg_context_init() 1332 for(op = 0; op < NB_OPS; op++) { in tcg_context_init() 2965 for (op = 0; op < NB_OPS; op++) { in process_op_defs() 3174 if (use->op == op) { in remove_label_use() 3281 TCGOp *op = u->op; in move_label_uses() local 3781 op->args[1] = op->args[2]; in liveness_pass_1() 3782 op->args[2] = op->args[4]; in liveness_pass_1() 3819 op->args[1] = op->args[2]; in liveness_pass_1() 3820 op->args[2] = op->args[3]; in liveness_pass_1() 3824 op->args[0] = op->args[1]; in liveness_pass_1() [all …]
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/qemu/disas/ |
H A D | riscv-xthead.c | 275 dec->op = op; in decode_xtheadba() 331 dec->op = op; in decode_xtheadbb() 357 dec->op = op; in decode_xtheadbs() 435 dec->op = op; in decode_xtheadcmo() 462 dec->op = op; in decode_xtheadcondmov() 499 dec->op = op; in decode_xtheadfmemidx() 534 dec->op = op; in decode_xtheadfmv() 565 dec->op = op; in decode_xtheadmac() 639 dec->op = op; in decode_xtheadmemidx() 673 dec->op = op; in decode_xtheadmempair() [all …]
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H A D | riscv.c | 2320 rv_opcode op = rv_op_illegal; in decode_inst_opcode() local 2327 op = rv_op_c_lq; in decode_inst_opcode() 2337 op = rv_op_c_ld; in decode_inst_opcode() 2360 op = rv_op_c_sq; in decode_inst_opcode() 2370 op = rv_op_c_sd; in decode_inst_opcode() 2437 op = rv_op_c_slli; in decode_inst_opcode() 3853 dec->op = op; in decode_inst_opcode() 5039 dec->op = comp_data->op; in decode_inst_lift_pseudo() 5058 dec->op = decomp_op; in decode_inst_decompress_rv32() 5073 dec->op = decomp_op; in decode_inst_decompress_rv64() [all …]
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/qemu/hw/i386/kvm/ |
H A D | xenstore_impl.c | 298 if (!op->mutating || op->in_transaction) { in fire_watches() 306 w = g_hash_table_lookup(op->s->watches, op->path); in fire_watches() 625 err = op->op_fn(n, op); in xs_node_walk() 687 op->watches = g_list_append(op->watches, watch); in xs_node_walk() 697 op->watches = g_list_remove(op->watches, watch); in xs_node_walk() 756 if (op->s->root_tx != op->s->last_tx) { in xs_node_walk() 757 op->s->root_tx = next_tx(op->s); in xs_node_walk() 759 op->s->nr_nodes = op->new_nr_nodes; in xs_node_walk() 841 op->path[strlen(op->path) + 1] = '\0'; in init_walk_op() 995 op->watches = g_list_append(op->watches, watch); in tx_commit_walk() [all …]
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/qemu/target/riscv/ |
H A D | instmap.h | 22 #define MASK_OP_MAJOR(op) (op & 0x7F) argument 56 #define MASK_OP_ARITH(op) (MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | \ argument 83 #define MASK_OP_ARITH_IMM(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) argument 96 #define MASK_OP_BRANCH(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) argument 129 #define MASK_OP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) argument 140 #define MASK_OP_STORE(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) argument 148 #define MASK_OP_JALR(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) argument 170 #define MASK_OP_SYSTEM(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) argument 191 #define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) argument 197 #define MASK_OP_FP_STORE(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) argument [all …]
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/qemu/tests/tcg/aarch64/ |
H A D | float_madds.ref | 2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) 4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) 6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) 170 op : f32(inf:0x7f800000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) 172 op : f32(nan:0x7fc00000) * f32(nan:0x7fa00000) + f32(inf:0x7f800000) 174 op : f32(nan:0x7fa00000) * f32(inf:0x7f800000) + f32(nan:0x7fc00000) 176 op : f32(nan:0x7fc00000) * f32(nan:0x7fa00000) + f32(-nan:0xffa00000) 178 op : f32(nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(nan:0x7fc00000) 180 op : f32(-nan:0xffa00000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) 362 op : f32(inf:0x7f800000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) [all …]
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/qemu/tests/tcg/ppc64le/ |
H A D | float_madds.ref | 2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) 4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) 6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) 170 op : f32(inf:0x7f800000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) 172 op : f32(nan:0x7fc00000) * f32(nan:0x7fa00000) + f32(inf:0x7f800000) 174 op : f32(nan:0x7fa00000) * f32(inf:0x7f800000) + f32(nan:0x7fc00000) 176 op : f32(nan:0x7fc00000) * f32(nan:0x7fa00000) + f32(-nan:0xffa00000) 178 op : f32(nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(nan:0x7fc00000) 180 op : f32(-nan:0xffa00000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) 362 op : f32(inf:0x7f800000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) [all …]
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/qemu/tests/tcg/hexagon/ |
H A D | float_madds.ref | 2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) 4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) 6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) 170 op : f32(inf:0x7f800000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) 172 op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(inf:0x7f800000) 174 op : f32(-nan:0x7fa00000) * f32(inf:0x7f800000) + f32(-nan:0x7fc00000) 176 op : f32(-nan:0x7fc00000) * f32(-nan:0x7fa00000) + f32(-nan:0xffa00000) 178 op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0x7fc00000) 180 op : f32(-nan:0xffa00000) * f32(-nan:0x7fc00000) + f32(-nan:0x7fa00000) 182 op : f32(-nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) [all …]
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/qemu/tests/tcg/arm/ |
H A D | float_madds.ref | 2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) 4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) 6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) 170 op : f32(inf:0x7f800000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) 172 op : f32(nan:0x7fc00000) * f32(nan:0x7fa00000) + f32(inf:0x7f800000) 174 op : f32(nan:0x7fa00000) * f32(inf:0x7f800000) + f32(nan:0x7fc00000) 176 op : f32(nan:0x7fc00000) * f32(nan:0x7fa00000) + f32(-nan:0xffa00000) 178 op : f32(nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(nan:0x7fc00000) 180 op : f32(-nan:0xffa00000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) 362 op : f32(inf:0x7f800000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) [all …]
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/qemu/tests/tcg/loongarch64/ |
H A D | float_madds.ref | 2 op : f32(-nan:0xffa00000) * f32(-nan:0xffc00000) + f32(-inf:0xff800000) 4 op : f32(-nan:0xffc00000) * f32(-inf:0xff800000) + f32(-nan:0xffa00000) 6 op : f32(-inf:0xff800000) * f32(-nan:0xffa00000) + f32(-nan:0xffc00000) 170 op : f32(inf:0x7f800000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) 172 op : f32(nan:0x7fc00000) * f32(nan:0x7fa00000) + f32(inf:0x7f800000) 174 op : f32(nan:0x7fa00000) * f32(inf:0x7f800000) + f32(nan:0x7fc00000) 176 op : f32(nan:0x7fc00000) * f32(nan:0x7fa00000) + f32(-nan:0xffa00000) 178 op : f32(nan:0x7fa00000) * f32(-nan:0xffa00000) + f32(nan:0x7fc00000) 180 op : f32(-nan:0xffa00000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) 362 op : f32(inf:0x7f800000) * f32(nan:0x7fc00000) + f32(nan:0x7fa00000) [all …]
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/qemu/tests/tcg/xtensa/ |
H A D | fpu.h | 49 .macro test_op1_rm op, fr0, fr1, v0, r, sr 53 \op \fr1, \fr0 57 .macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r, sr 62 \op \fr2, \fr0, \fr1 72 \op \fr0, \fr1, \fr2 76 .macro test_op1_ex op, fr0, fr1, v0, rm, r, sr 79 test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr 82 test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr 104 test_op1_ex \op, \fr0, \fr1, \v0, 0, \r0, \sr0 124 .macro test_op2_cpe op [all …]
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H A D | test_fp1.S | 13 .macro test_ord_ex op, br, fr0, fr1, v0, v1, r, sr 18 \op \br, \fr0, \fr1 32 .macro test_ord op, br, fr0, fr1, v0, v1, r, sr 35 test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr 38 test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr 41 .macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI, qnan_sr 42 test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa, FSR__ /* ord == ord */ 43 test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab, FSR__ /* ord < ord */ 44 test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba, FSR__ /* ord > ord */ 90 .macro test_cond op, fr0, fr1, cr, v0, v1, r [all …]
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/qemu/target/arm/tcg/ |
H A D | mve.decode | 41 &1op qd qm size 42 &2op qd qm qn size 44 &1imm qd imm cmode op 75 @1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm 77 @2op .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn 137 @2op_fp .... .... .... .... .... .... .... .... &2op \ 145 @vmaxnma .... .... .... .... .... .... .... .... &2op \ 210 # Vector 2-op 589 # The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but 592 # VORR: op=0, (cmode & 1) && cmode < 12 [all …]
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/qemu/target/i386/hvf/ |
H A D | x86_emu.c | 237 decode->op[i].val = read_val_from_reg(decode->op[i].ptr, in fetch_operands() 244 decode->op[i].val = read_val_ext(env, decode->op[i].ptr, in fetch_operands() 253 decode->op[i].val = read_val_ext(env, decode->op[i].ptr, in fetch_operands() 266 write_val_ext(env, decode->op[0].ptr, decode->op[1].val, in exec_mov() 372 write_val_ext(env, decode->op[0].ptr, ~decode->op[0].val, in exec_not() 392 write_val_ext(env, decode->op[0].ptr, decode->op[1].val, op_size); in exec_movzx() 889 decode->op[0].val = read_val_ext(env, decode->op[0].ptr, in do_bt() 907 write_val_ext(env, decode->op[0].ptr, decode->op[0].val, in do_bt() 1347 write_val_ext(env, decode->op[0].ptr, decode->op[1].val, in exec_xchg() 1349 write_val_ext(env, decode->op[1].ptr, decode->op[0].val, in exec_xchg() [all …]
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H A D | x86_decode.c | 114 op->ptr = get_reg_ref(env, op->reg, decode->rex.rex, decode->rex.r, in decode_modrm_reg() 122 op->reg = R_EAX; in decode_rax() 124 op->ptr = get_reg_ref(env, op->reg, false, 0, in decode_rax() 162 op->val = sign(op->val, 1); in decode_imm8_signed() 179 op->val = sign(op->val, decode->operand_size); in decode_imm() 190 op->val = sign(op->val, decode->operand_size); in decode_imm_signed() 198 op->val = 1; in decode_imm_1() 205 op->val = 0; in decode_imm_0() 214 switch (op) { in decode_pushseg() 241 switch (op) { in decode_popseg() [all …]
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/qemu/block/ |
H A D | mirror.c | 267 ret = blk_co_pwritev(s->target, op->offset, op->qiov.size, &op->qiov, 0); in mirror_read_complete() 330 if (!op->is_pseudo_op && op->is_in_flight && !op->is_active_write) { in mirror_wait_for_free_in_flight_slot() 360 *op->bytes_handled = op->bytes; in mirror_co_read() 363 *op->bytes_handled += mirror_cow_align(s, &op->offset, &op->bytes); in mirror_co_read() 387 size_t remaining = op->bytes - op->qiov.size; in mirror_co_read() 413 op->s->bytes_in_flight += op->bytes; in mirror_co_zero() 414 *op->bytes_handled = op->bytes; in mirror_co_zero() 417 ret = blk_co_pwrite_zeroes(op->s->target, op->offset, op->bytes, in mirror_co_zero() 428 op->s->bytes_in_flight += op->bytes; in mirror_co_discard() 429 *op->bytes_handled = op->bytes; in mirror_co_discard() [all …]
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/qemu/hw/ppc/ |
H A D | spapr_pci_vfio.c | 67 .op = op, in vfio_eeh_container_op() 163 uint32_t op; in spapr_phb_vfio_eeh_set_option() local 168 op = VFIO_EEH_PE_DISABLE; in spapr_phb_vfio_eeh_set_option() 202 op = VFIO_EEH_PE_ENABLE; in spapr_phb_vfio_eeh_set_option() 206 op = VFIO_EEH_PE_UNFREEZE_IO; in spapr_phb_vfio_eeh_set_option() 209 op = VFIO_EEH_PE_UNFREEZE_DMA; in spapr_phb_vfio_eeh_set_option() 215 ret = vfio_eeh_as_op(&sphb->iommu_as, op); in spapr_phb_vfio_eeh_set_option() 281 uint32_t op; in spapr_phb_vfio_eeh_reset() local 286 op = VFIO_EEH_PE_RESET_DEACTIVATE; in spapr_phb_vfio_eeh_reset() 290 op = VFIO_EEH_PE_RESET_HOT; in spapr_phb_vfio_eeh_reset() [all …]
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/qemu/tests/tcg/i386/ |
H A D | test-avx.py | 118 def match(op, pattern): argument 120 return fnmatch(op, pattern[1:]) or fnmatch(op, 'V'+pattern[1:]) 121 return fnmatch(op, pattern) 138 def __init__(self, op): argument 140 if match(op, k): 183 def ArgGenerator(arg, op): argument 201 return ArgImm8u(op); 226 self.op = op 228 if op[-1] == 'H': 254 yield self.op [all …]
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H A D | test-mmx.py | 71 def match(op, pattern): argument 72 return fnmatch(op, pattern) 77 def __init__(self, op): argument 79 if match(op, k): 122 def ArgGenerator(arg, op): argument 132 return ArgImm8u(op); 152 def __init__(self, op, args): argument 153 self.op = op 154 if op[0:2] == "PF": 174 yield self.op [all …]
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/qemu/tests/unit/ |
H A D | test-util-filemonitor.c | 475 if (op->filedst) { in test_file_monitor_events() 479 switch (op->type) { in test_file_monitor_events() 483 dir, op->filesrc); in test_file_monitor_events() 485 if (op->filesrc && strchr(op->filesrc, '/')) { in test_file_monitor_events() 495 watchfile = op->filesrc; in test_file_monitor_events() 497 *op->watchid = in test_file_monitor_events() 505 if (*op->watchid < 0) { in test_file_monitor_events() 524 if (op->filesrc && strchr(op->filesrc, '/')) { in test_file_monitor_events() 540 *op->watchid, op->eventid, op->filesrc); in test_file_monitor_events() 543 op->eventid, op->filesrc, in test_file_monitor_events() [all …]
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/qemu/target/i386/tcg/ |
H A D | emit.c.inc | 102 assert(op->unit == X86_OP_MMX || op->unit == X86_OP_SSE); 105 return op->offset - mmx_offset(op->ot); 107 return op->offset - xmm_offset(op->ot); 153 op->offset = offsetof(CPUX86State, fpregs[op->n].mmx) + mmx_offset(op->ot); 162 op->offset = ZMM_OFFSET(op->n) + xmm_offset(op->ot); 218 X86DecodedOp *op = &decode->op[opn]; 254 tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot); 285 X86DecodedOp *op = &decode->op[opn]; 302 X86DecodedOp *op = &decode->op[opn]; 314 gen_op_mov_reg_v(s, op->ot, op->n, v); [all …]
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/qemu/tests/tcg/s390x/ |
H A D | vfminmax.c | 26 insn[5] = op; in vfminmax() 120 int op; member 126 .op = VFMIN, 142 .op = VFMIN, 158 .op = VFMIN, 174 .op = VFMIN, 190 .op = VFMIN, 207 .op = VFMAX, 223 .op = VFMAX, 239 .op = VFMAX, [all …]
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