/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/gas/testsuite/gas/d10v/ |
H A D | instruction_packing.d | 13 4: 30 23 24 02 ld r2, @r3 || sra r0, r1 17 c: 30 23 24 02 ld r2, @r3 || sra r0, r1 25 1c: 01 45 24 02 add r4, r5 || sra r0, r1 33 2c: 01 45 24 02 add r4, r5 || sra r0, r1 37 34: b0 23 24 02 ld r2, @r3 <- sra r0, r1 41 3c: 70 23 24 02 ld r2, @r3 -> sra r0, r1 49 4c: 41 45 24 02 add r4, r5 -> sra r0, r1 57 5c: 81 45 24 02 add r4, r5 <- sra r0, r1 61 64: 70 23 24 02 ld r2, @r3 -> sra r0, r1 65 6c: b0 23 24 02 ld r2, @r3 <- sra r0, r1 [all …]
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/dports/devel/gnulibiberty/binutils-2.37/gas/testsuite/gas/d10v/ |
H A D | instruction_packing.d | 13 4: 30 23 24 02 ld r2, @r3 || sra r0, r1 17 c: 30 23 24 02 ld r2, @r3 || sra r0, r1 25 1c: 01 45 24 02 add r4, r5 || sra r0, r1 33 2c: 01 45 24 02 add r4, r5 || sra r0, r1 37 34: b0 23 24 02 ld r2, @r3 <- sra r0, r1 41 3c: 70 23 24 02 ld r2, @r3 -> sra r0, r1 49 4c: 41 45 24 02 add r4, r5 -> sra r0, r1 57 5c: 81 45 24 02 add r4, r5 <- sra r0, r1 61 64: 70 23 24 02 ld r2, @r3 -> sra r0, r1 65 6c: b0 23 24 02 ld r2, @r3 <- sra r0, r1 [all …]
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/dports/lang/gnatdroid-binutils/binutils-2.27/gas/testsuite/gas/d10v/ |
H A D | instruction_packing.d | 13 4: 30 23 24 02 ld r2, @r3 || sra r0, r1 17 c: 30 23 24 02 ld r2, @r3 || sra r0, r1 25 1c: 01 45 24 02 add r4, r5 || sra r0, r1 33 2c: 01 45 24 02 add r4, r5 || sra r0, r1 37 34: b0 23 24 02 ld r2, @r3 <- sra r0, r1 41 3c: 70 23 24 02 ld r2, @r3 -> sra r0, r1 49 4c: 41 45 24 02 add r4, r5 -> sra r0, r1 57 5c: 81 45 24 02 add r4, r5 <- sra r0, r1 61 64: 70 23 24 02 ld r2, @r3 -> sra r0, r1 65 6c: b0 23 24 02 ld r2, @r3 <- sra r0, r1 [all …]
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/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/gas/testsuite/gas/d10v/ |
H A D | instruction_packing.d | 13 4: 30 23 24 02 ld r2, @r3 || sra r0, r1 17 c: 30 23 24 02 ld r2, @r3 || sra r0, r1 25 1c: 01 45 24 02 add r4, r5 || sra r0, r1 33 2c: 01 45 24 02 add r4, r5 || sra r0, r1 37 34: b0 23 24 02 ld r2, @r3 <- sra r0, r1 41 3c: 70 23 24 02 ld r2, @r3 -> sra r0, r1 49 4c: 41 45 24 02 add r4, r5 -> sra r0, r1 57 5c: 81 45 24 02 add r4, r5 <- sra r0, r1 61 64: 70 23 24 02 ld r2, @r3 -> sra r0, r1 65 6c: b0 23 24 02 ld r2, @r3 <- sra r0, r1 [all …]
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/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/gas/testsuite/gas/d10v/ |
H A D | instruction_packing.d | 13 4: 30 23 24 02 ld r2, @r3 || sra r0, r1 17 c: 30 23 24 02 ld r2, @r3 || sra r0, r1 25 1c: 01 45 24 02 add r4, r5 || sra r0, r1 33 2c: 01 45 24 02 add r4, r5 || sra r0, r1 37 34: b0 23 24 02 ld r2, @r3 <- sra r0, r1 41 3c: 70 23 24 02 ld r2, @r3 -> sra r0, r1 49 4c: 41 45 24 02 add r4, r5 -> sra r0, r1 57 5c: 81 45 24 02 add r4, r5 <- sra r0, r1 61 64: 70 23 24 02 ld r2, @r3 -> sra r0, r1 65 6c: b0 23 24 02 ld r2, @r3 <- sra r0, r1 [all …]
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/dports/devel/djgpp-binutils/binutils-2.17/gas/testsuite/gas/d10v/ |
H A D | instruction_packing.d | 13 4: 30 23 24 02 ld r2, @r3 || sra r0, r1 17 c: 30 23 24 02 ld r2, @r3 || sra r0, r1 25 1c: 01 45 24 02 add r4, r5 || sra r0, r1 33 2c: 01 45 24 02 add r4, r5 || sra r0, r1 37 34: b0 23 24 02 ld r2, @r3 <- sra r0, r1 41 3c: 70 23 24 02 ld r2, @r3 -> sra r0, r1 49 4c: 41 45 24 02 add r4, r5 -> sra r0, r1 57 5c: 81 45 24 02 add r4, r5 <- sra r0, r1 61 64: 70 23 24 02 ld r2, @r3 -> sra r0, r1 65 6c: b0 23 24 02 ld r2, @r3 <- sra r0, r1 [all …]
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/dports/devel/binutils/binutils-2.37/gas/testsuite/gas/d10v/ |
H A D | instruction_packing.d | 13 4: 30 23 24 02 ld r2, @r3 || sra r0, r1 17 c: 30 23 24 02 ld r2, @r3 || sra r0, r1 25 1c: 01 45 24 02 add r4, r5 || sra r0, r1 33 2c: 01 45 24 02 add r4, r5 || sra r0, r1 37 34: b0 23 24 02 ld r2, @r3 <- sra r0, r1 41 3c: 70 23 24 02 ld r2, @r3 -> sra r0, r1 49 4c: 41 45 24 02 add r4, r5 -> sra r0, r1 57 5c: 81 45 24 02 add r4, r5 <- sra r0, r1 61 64: 70 23 24 02 ld r2, @r3 -> sra r0, r1 65 6c: b0 23 24 02 ld r2, @r3 <- sra r0, r1 [all …]
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/dports/emulators/mess/mame-mame0226/src/devices/cpu/h8/ |
H A D | h8_dtc.cpp | 128 uint32_t sra = state->sra; in vector_done() local 135 state->incs = sra & 0x80000000 ? in vector_done() 136 sra & 0x40000000 ? sra & 0x01000000 ? -2 : -1 : in vector_done() 137 sra & 0x01000000 ? 2 : 1 : in vector_done() 139 state->incd = sra & 0x20000000 ? in vector_done() 140 sra & 0x10000000 ? sra & 0x01000000 ? -2 : -1 : in vector_done() 141 sra & 0x01000000 ? 2 : 1 : in vector_done() 245 if(state->sra & 0x02000000) in count_done() 246 state->sra = (state->sra & 0xff000000) | ((state->sra - cnt*state->incs) & 0xffffff); in count_done() 257 if(state->sra & 0x02000000) in count_done() [all …]
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/dports/emulators/mame/mame-mame0226/src/devices/cpu/h8/ |
H A D | h8_dtc.cpp | 128 uint32_t sra = state->sra; in vector_done() local 135 state->incs = sra & 0x80000000 ? in vector_done() 136 sra & 0x40000000 ? sra & 0x01000000 ? -2 : -1 : in vector_done() 137 sra & 0x01000000 ? 2 : 1 : in vector_done() 139 state->incd = sra & 0x20000000 ? in vector_done() 140 sra & 0x10000000 ? sra & 0x01000000 ? -2 : -1 : in vector_done() 141 sra & 0x01000000 ? 2 : 1 : in vector_done() 245 if(state->sra & 0x02000000) in count_done() 246 state->sra = (state->sra & 0xff000000) | ((state->sra - cnt*state->incs) & 0xffffff); in count_done() 257 if(state->sra & 0x02000000) in count_done() [all …]
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/dports/biology/sra-tools/sra-tools-2.11.0/tools/sra-toolkit/ |
H A D | Makefile | 29 MODULE = tools/sra-toolkit 34 sra-toolkit 79 $(BINDIR)/sra-toolkit: 80 $(QMAKE_BIN) $(SRCDIR)/sra-toolkit.pro CONFIG+=$(QT_CONF) CONFIG+=make 82 cp $(OBJDIR)/sra-toolkit $(BINDIR)/sra-toolkit$(VERSION_EXEX) 83 ln -s sra-toolkit$(VERSION_EXEX) $(BINDIR)/sra-toolkit$(MAJVERS_EXEX) 84 ln -s sra-toolkit$(MAJVERS_EXEX) $(BINDIR)/sra-toolkit
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/dports/biology/sra-tools/sra-tools-2.11.0/tools/build-sra-toolkit-Desktop_Qt_5_10_0_clang_64bit-Debug/ |
H A D | Makefile | 38 DISTDIR = /Users/rodarme1/devel/sra-tools/tools/build-sra-toolkit-Desktop_Qt_5_10_0_clang_64bit-Deb… 287 ../sra-toolkit/sra-toolkit.pro ../sra-toolkit/sratoolkit.h \ 515 ../sra-toolkit/sra-toolkit.pro \ 701 ../sra-toolkit/sra-toolkit.pro: 771 …sra-toolkit/.moc/moc_sratoolkit.cpp obj/sra-toolkit/.moc/moc_sratoolkitpreferences.cpp obj/sra-too… 867 obj/sra-toolkit/main.o: ../sra-toolkit/main.cpp ../sra-toolkit/sratoolkit.h \ 1006 obj/sra-toolkit/sratoolkit.o: ../sra-toolkit/sratoolkit.cpp ../sra-toolkit/sratoolkit.h \ 1172 obj/sra-toolkit/sraworkspace.o: ../sra-toolkit/sraworkspace.cpp ../sra-toolkit/sraworkspace.h \ 1177 obj/sra-toolkit/sratoolbar.o: ../sra-toolkit/sratoolbar.cpp ../sra-toolkit/sratoolbar.h \ 1316 obj/sra-toolkit/sratoolview.o: ../sra-toolkit/sratoolview.cpp ../sra-toolkit/sratoolview.h \ [all …]
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/dports/devel/binutils/binutils-2.37/gas/testsuite/gas/z80/ |
H A D | rotate.s | 55 sra a 56 sra b 57 sra c 58 sra d 59 sra e 60 sra h 61 sra l 62 sra (hl) 63 sra (ix+5) 64 sra (iy+5)
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/dports/lang/gnatdroid-binutils-x86/binutils-2.27/gas/testsuite/gas/z80/ |
H A D | rotate.s | 55 sra a 56 sra b 57 sra c 58 sra d 59 sra e 60 sra h 61 sra l 62 sra (hl) 63 sra (ix+5) 64 sra (iy+5)
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/dports/devel/arm-elf-binutils/binutils-2.37/gas/testsuite/gas/z80/ |
H A D | rotate.s | 55 sra a 56 sra b 57 sra c 58 sra d 59 sra e 60 sra h 61 sra l 62 sra (hl) 63 sra (ix+5) 64 sra (iy+5)
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/dports/devel/gnulibiberty/binutils-2.37/gas/testsuite/gas/z80/ |
H A D | rotate.s | 55 sra a 56 sra b 57 sra c 58 sra d 59 sra e 60 sra h 61 sra l 62 sra (hl) 63 sra (ix+5) 64 sra (iy+5)
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/dports/lang/gnatdroid-binutils/binutils-2.27/gas/testsuite/gas/z80/ |
H A D | rotate.s | 55 sra a 56 sra b 57 sra c 58 sra d 59 sra e 60 sra h 61 sra l 62 sra (hl) 63 sra (ix+5) 64 sra (iy+5)
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/dports/biology/sra-tools/sra-tools-2.11.0/build/docker/ |
H A D | Makefile | 10 …docker build --build-arg VDB_BRANCH=${BRANCH} -t ncbi/sra-tools:${VERSION} -f Dockerfile.build-alp… 11 docker tag ncbi/sra-tools:${VERSION} ncbi/sra-tools:latest 14 docker scan --file Dockerfile.build-alpine ncbi/sra-tools:${VERSION} 17 docker push ncbi/sra-tools:${VERSION} 18 docker push ncbi/sra-tools:latest 21 docker image rm ncbi/sra-tools ncbi/sra-tools:${VERSION}
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/dports/biology/ncbi-cxx-toolkit/ncbi_cxx--25_2_0/src/sra/readers/sra/test/ |
H A D | sra_test.cpp | 133 string sra = args["sra"].AsString(); in Run() local 136 mgr.GetSpotEntry(sra); in Run() 138 "GetSpotEntry("<<sra<<") unexpectedly succeeded"); in Run() 144 sra<<": "<<exc); in Run() 147 NcbiCout << "Correctly detected missing SRA acc: " << sra in Run() 152 string acc = sra; in Run() 164 CRef<CSeq_entry> entry = mgr.GetSpotEntry(sra); in Run() 170 string sra = args["sra_all"].AsString(); in Run() local 171 CSeq_id_Handle idh = CSeq_id_Handle::GetHandle("gnl|SRA|"+sra); in Run() 183 string sar = sra.substr(0, sra.rfind('.')); in Run() [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/ |
H A D | mad_int24.ll | 34 %sra.0 = ashr i32 %shl.0, 8 36 %sra.1 = ashr i32 %shl.1, 8 38 %mul0 = mul nsw i32 %sra.0, %sra.1 42 %sra.2 = ashr i32 %shl.2, 8 44 %shl.3 = shl i32 %sra.0, 8 45 %sra.3 = ashr i32 %shl.3, 8 47 %mul1 = mul nsw i32 %sra.2, %sra.3 58 %sra.0 = ashr i32 %shl.0, 8 62 %mul0 = call i32 @llvm.amdgcn.mul.i24(i32 %sra.0, i32 %sra.1) 68 %shl.3 = shl i32 %sra.0, 8 [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/ |
H A D | mad_int24.ll | 34 %sra.0 = ashr i32 %shl.0, 8 36 %sra.1 = ashr i32 %shl.1, 8 38 %mul0 = mul nsw i32 %sra.0, %sra.1 42 %sra.2 = ashr i32 %shl.2, 8 44 %shl.3 = shl i32 %sra.0, 8 45 %sra.3 = ashr i32 %shl.3, 8 47 %mul1 = mul nsw i32 %sra.2, %sra.3 58 %sra.0 = ashr i32 %shl.0, 8 62 %mul0 = call i32 @llvm.amdgcn.mul.i24(i32 %sra.0, i32 %sra.1) 68 %shl.3 = shl i32 %sra.0, 8 [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/ |
H A D | mad_int24.ll | 34 %sra.0 = ashr i32 %shl.0, 8 36 %sra.1 = ashr i32 %shl.1, 8 38 %mul0 = mul nsw i32 %sra.0, %sra.1 42 %sra.2 = ashr i32 %shl.2, 8 44 %shl.3 = shl i32 %sra.0, 8 45 %sra.3 = ashr i32 %shl.3, 8 47 %mul1 = mul nsw i32 %sra.2, %sra.3 58 %sra.0 = ashr i32 %shl.0, 8 62 %mul0 = call i32 @llvm.amdgcn.mul.i24(i32 %sra.0, i32 %sra.1) 68 %shl.3 = shl i32 %sra.0, 8 [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/ |
H A D | mad_int24.ll | 34 %sra.0 = ashr i32 %shl.0, 8 36 %sra.1 = ashr i32 %shl.1, 8 38 %mul0 = mul nsw i32 %sra.0, %sra.1 42 %sra.2 = ashr i32 %shl.2, 8 44 %shl.3 = shl i32 %sra.0, 8 45 %sra.3 = ashr i32 %shl.3, 8 47 %mul1 = mul nsw i32 %sra.2, %sra.3 58 %sra.0 = ashr i32 %shl.0, 8 62 %mul0 = call i32 @llvm.amdgcn.mul.i24(i32 %sra.0, i32 %sra.1) 68 %shl.3 = shl i32 %sra.0, 8 [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | mad_int24.ll | 34 %sra.0 = ashr i32 %shl.0, 8 36 %sra.1 = ashr i32 %shl.1, 8 38 %mul0 = mul nsw i32 %sra.0, %sra.1 42 %sra.2 = ashr i32 %shl.2, 8 44 %shl.3 = shl i32 %sra.0, 8 45 %sra.3 = ashr i32 %shl.3, 8 47 %mul1 = mul nsw i32 %sra.2, %sra.3 58 %sra.0 = ashr i32 %shl.0, 8 62 %mul0 = call i32 @llvm.amdgcn.mul.i24(i32 %sra.0, i32 %sra.1) 68 %shl.3 = shl i32 %sra.0, 8 [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/ |
H A D | mad_int24.ll | 34 %sra.0 = ashr i32 %shl.0, 8 36 %sra.1 = ashr i32 %shl.1, 8 38 %mul0 = mul nsw i32 %sra.0, %sra.1 42 %sra.2 = ashr i32 %shl.2, 8 44 %shl.3 = shl i32 %sra.0, 8 45 %sra.3 = ashr i32 %shl.3, 8 47 %mul1 = mul nsw i32 %sra.2, %sra.3 58 %sra.0 = ashr i32 %shl.0, 8 62 %mul0 = call i32 @llvm.amdgcn.mul.i24(i32 %sra.0, i32 %sra.1) 68 %shl.3 = shl i32 %sra.0, 8 [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | mad_int24.ll | 34 %sra.0 = ashr i32 %shl.0, 8 36 %sra.1 = ashr i32 %shl.1, 8 38 %mul0 = mul nsw i32 %sra.0, %sra.1 42 %sra.2 = ashr i32 %shl.2, 8 44 %shl.3 = shl i32 %sra.0, 8 45 %sra.3 = ashr i32 %shl.3, 8 47 %mul1 = mul nsw i32 %sra.2, %sra.3 58 %sra.0 = ashr i32 %shl.0, 8 62 %mul0 = call i32 @llvm.amdgcn.mul.i24(i32 %sra.0, i32 %sra.1) 68 %shl.3 = shl i32 %sra.0, 8 [all …]
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