/qemu/target/mips/tcg/ |
H A D | mxu_translate.c | 1026 tcg_gen_mul_tl(t2, t0, t2); in gen_mxu_d16mul() 1030 tcg_gen_mul_tl(t2, t0, t2); in gen_mxu_d16mul() 1034 tcg_gen_mul_tl(t2, t1, t2); in gen_mxu_d16mul() 1038 tcg_gen_mul_tl(t2, t1, t2); in gen_mxu_d16mul() 1046 tcg_gen_shli_tl(t2, t2, 1); in gen_mxu_d16mul() 1126 tcg_gen_mul_tl(t2, t0, t2); in gen_mxu_d16mac() 1130 tcg_gen_mul_tl(t2, t0, t2); in gen_mxu_d16mac() 1406 tcg_gen_mul_tl(t2, t2, t6); in gen_mxu_q8mul_mac() 1479 tcg_gen_mul_tl(t2, t2, t6); in gen_mxu_q8madl() 3718 tcg_gen_sub_tl(t2, t4, t2); in gen_mxu_s32extrv() [all …]
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H A D | translate.c | 1273 tcg_gen_andi_i32(t2, t2, 0xf); in gen_load_srsgpr() 1293 tcg_gen_andi_i32(t2, t2, 0xf); in gen_store_srsgpr() 2589 tcg_gen_xor_tl(t2, t0, t2); in gen_arith() 2621 tcg_gen_xor_tl(t2, t1, t2); in gen_arith() 3063 tcg_gen_or_tl(t2, t2, t3); in gen_r6_muldiv() 3080 tcg_gen_or_tl(t2, t2, t3); in gen_r6_muldiv() 3158 tcg_gen_or_tl(t2, t2, t3); in gen_r6_muldiv() 3172 tcg_gen_or_tl(t2, t2, t3); in gen_r6_muldiv() 3242 tcg_gen_or_tl(t2, t2, t3); in gen_div1_tx79() 3298 tcg_gen_or_tl(t2, t2, t3); in gen_muldiv() [all …]
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/qemu/crypto/ |
H A D | aes.c | 1451 u32 s0, s1, s2, s3, t0, t1, t2, t3; in AES_encrypt() local 1556 t2 = in AES_encrypt() 1577 AES_Te2[(t2 >> 8) & 0xff] ^ in AES_encrypt() 1582 AES_Te1[(t2 >> 16) & 0xff] ^ in AES_encrypt() 1587 AES_Te0[(t2 >> 24) ] ^ in AES_encrypt() 1596 AES_Te3[(t2 ) & 0xff] ^ in AES_encrypt() 1747 t2 = in AES_decrypt() 1768 AES_Td2[(t2 >> 8) & 0xff] ^ in AES_decrypt() 1775 AES_Td3[(t2 ) & 0xff] ^ in AES_decrypt() 1778 AES_Td0[(t2 >> 24) ] ^ in AES_decrypt() [all …]
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/qemu/include/exec/ |
H A D | helper-gen.h.inc | 31 #define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ 34 dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ 38 dh_arg(t1, 1), dh_arg(t2, 2)); \ 41 #define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ 44 dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ 48 dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3)); \ 51 #define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ 54 dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ 59 dh_arg(t1, 1), dh_arg(t2, 2), \ 63 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ [all …]
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H A D | helper-proto.h.inc | 29 #define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ 30 dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2)) DEF_HELPER_ATTR; 32 #define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ 33 dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), \ 36 #define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ 37 dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ 40 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ 41 dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ 44 #define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ 45 dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ [all …]
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H A D | helper-head.h.inc | 120 #define DEF_HELPER_2(name, ret, t1, t2) \ 121 DEF_HELPER_FLAGS_2(name, 0, ret, t1, t2) 122 #define DEF_HELPER_3(name, ret, t1, t2, t3) \ 123 DEF_HELPER_FLAGS_3(name, 0, ret, t1, t2, t3) 124 #define DEF_HELPER_4(name, ret, t1, t2, t3, t4) \ 125 DEF_HELPER_FLAGS_4(name, 0, ret, t1, t2, t3, t4) 126 #define DEF_HELPER_5(name, ret, t1, t2, t3, t4, t5) \ 127 DEF_HELPER_FLAGS_5(name, 0, ret, t1, t2, t3, t4, t5) 128 #define DEF_HELPER_6(name, ret, t1, t2, t3, t4, t5, t6) \ 129 DEF_HELPER_FLAGS_6(name, 0, ret, t1, t2, t3, t4, t5, t6) [all …]
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/qemu/docs/devel/ |
H A D | tcg-ops.rst | 62 add_i32 t0, t1, t2 /* (t0 <- t1 + t2) */ 207 add_i32 t0, t1, t2 266 - | *t0* = *t1* + *t2* 270 - | *t0* = *t1* - *t2* 278 - | *t0* = *t1* * *t2* 328 - | *t0* = ~(*t1* ^ *t2*), or equivalently, *t0* = *t1* ^ ~\ *t2* 366 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64) 371 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64) 376 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64) 381 | Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64) [all …]
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/qemu/target/riscv/insn_trans/ |
H A D | trans_rvk.c.inc | 158 tcg_gen_xor_i32(t1, t1, t2); 159 func(t2, t0, num3); 160 tcg_gen_xor_i32(t1, t1, t2); 205 func2(t2, t0, num2); 206 tcg_gen_xor_i64(t1, t1, t2); 208 tcg_gen_xor_i64(t1, t1, t2); 260 tcg_gen_ext32u_i64(t2, t0); 261 tcg_gen_shri_i64(t2, t2, num2); 262 tcg_gen_xor_i64(t1, t1, t2); 264 tcg_gen_xor_i64(t1, t1, t2); [all …]
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/qemu/util/ |
H A D | bufferiszero.c | 212 uint32x4_t t0, t1, t2, t3; in buffer_is_zero_simd() local 223 t2 = e[-5] | e[-4]; in buffer_is_zero_simd() 227 REASSOC_BARRIER(t2, t3); in buffer_is_zero_simd() 229 t2 |= t3; in buffer_is_zero_simd() 230 REASSOC_BARRIER(t0, t2); in buffer_is_zero_simd() 231 t0 |= t2; in buffer_is_zero_simd() 249 t2 = p[4] | p[5]; in buffer_is_zero_simd() 252 REASSOC_BARRIER(t2, t3); in buffer_is_zero_simd() 254 t2 |= t3; in buffer_is_zero_simd() 255 REASSOC_BARRIER(t0, t2); in buffer_is_zero_simd() [all …]
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/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_vec.c.inc | 508 TCGv_vec t1, t2; 521 tcg_gen_sari_vec(vece, t2, t2, halfbits); 528 TCGv_i32 t1, t2; 539 TCGv_i64 t1, t2; 595 TCGv_i32 t1, t2; 692 tcg_gen_sari_vec(vece, t2, t2, halfbits); 1186 tcg_gen_sari_vec(vece, t2, t2, halfbits); 2062 tcg_gen_sari_vec(vece, t2, t2, halfbits); 2419 tcg_gen_sari_vec(vece, t2, t2, halfbits); 2723 tcg_gen_sari_vec(vece, t2, t2, halfbits); [all …]
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/qemu/tcg/ |
H A D | tcg-op-gvec.c | 779 fni(t2, t0, t1); in expand_3_i32() 782 tcg_temp_free_i32(t2); in expand_3_i32() 802 fni(t2, t0, t1, c); in expand_3i_i32() 807 tcg_temp_free_i32(t2); in expand_3i_i32() 832 tcg_temp_free_i32(t2); in expand_4_i32() 856 tcg_temp_free_i32(t2); in expand_4i_i32() 938 fni(t2, t0, t1); in expand_3_i64() 941 tcg_temp_free_i64(t2); in expand_3_i64() 966 tcg_temp_free_i64(t2); in expand_3i_i64() 991 tcg_temp_free_i64(t2); in expand_4_i64() [all …]
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H A D | tcg-op-ldst.c | 835 tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); in tcg_gen_nonatomic_cmpxchg_i32_int() 837 tcg_temp_free_i32(t2); in tcg_gen_nonatomic_cmpxchg_i32_int() 898 TCGv_i64 t1, t2; in tcg_gen_nonatomic_cmpxchg_i64_int() local 912 t2 = tcg_temp_ebb_new_i64(); in tcg_gen_nonatomic_cmpxchg_i64_int() 917 tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); in tcg_gen_nonatomic_cmpxchg_i64_int() 919 tcg_temp_free_i64(t2); in tcg_gen_nonatomic_cmpxchg_i64_int() 1114 tcg_gen_ext_i32(t2, val, memop); in do_nonatomic_op_i32() 1115 gen(t2, t1, t2); in do_nonatomic_op_i32() 1120 tcg_temp_free_i32(t2); in do_nonatomic_op_i32() 1156 gen(t2, t1, t2); in do_nonatomic_op_i64() [all …]
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H A D | tcg-op.c | 710 tcg_gen_addi_i64(t2, t2, 32); in tcg_gen_clz_i32() 714 tcg_temp_free_i64(t2); in tcg_gen_clz_i32() 738 tcg_temp_free_i64(t2); in tcg_gen_ctz_i32() 1217 tcg_gen_and_i32(t2, t2, arg2); in tcg_gen_muls2_i32() 1224 tcg_temp_free_i32(t2); in tcg_gen_muls2_i32() 1247 tcg_gen_and_i32(t2, t2, arg2); in tcg_gen_mulsu2_i32() 1252 tcg_temp_free_i32(t2); in tcg_gen_mulsu2_i32() 2321 tcg_temp_free_i64(t2); in tcg_gen_bswap64_i64() 3080 tcg_gen_and_i64(t2, t2, arg2); in tcg_gen_muls2_i64() 3106 tcg_gen_and_i64(t2, t2, arg2); in tcg_gen_mulsu2_i64() [all …]
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/qemu/target/tricore/ |
H A D | op_helper.c | 600 if (t2 == 0) { in helper_sha_ssov() 602 } else if (t2 > 0) { in helper_sha_ssov() 637 if (t1 > t2) { in helper_absdif_ssov() 638 result = t1 - t2; in helper_absdif_ssov() 640 result = t2 - t1; in helper_absdif_ssov() 648 int32_t t1, t2; in helper_absdif_h_ssov() local 653 if (t1 > t2) { in helper_absdif_h_ssov() 661 if (t1 > t2) { in helper_absdif_h_ssov() 899 result = t2 - mul; in helper_msub32_suov() 906 if (mul > t2) { in helper_msub32_suov() [all …]
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H A D | translate.c | 509 tcg_gen_or_i64(t2, t2, t3); in gen_madd32_d() 568 tcg_gen_add_i64(t2, t2, t1); in gen_maddu64_d() 998 tcg_gen_mul_i64(t2, t2, t3); in gen_madd32_q() 999 tcg_gen_shli_i64(t2, t2, n); in gen_madd32_q() 1088 tcg_gen_shli_i64(t2, t2, 16); in gen_m16add64_q() 1135 tcg_gen_mul_i64(t2, t2, t3); in gen_madd64_q() 1142 tcg_gen_xor_i64(t2, t1, t2); in gen_madd64_q() 1181 tcg_gen_mul_i64(t2, t2, t3); in gen_madds32_q() 1219 tcg_gen_or_i64(t2, t2, t3); in gen_msub32_d() 1739 tcg_gen_mul_i64(t2, t2, t3); in gen_msub32_q() [all …]
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/qemu/ |
H A D | qemu-io-cmds.c | 269 t1.tv_sec -= t2.tv_sec; in tsub() 710 struct timespec t1, t2; in read_f() local 865 t2 = tsub(t2, t1); in read_f() 999 t2 = tsub(t2, t1); in readv_f() 1218 t2 = tsub(t2, t1); in write_f() 1337 t2 = tsub(t2, t1); in writev_f() 1364 struct timespec t2; in aio_write_done() local 1382 t2 = tsub(t2, ctx->t1); in aio_write_done() 1397 struct timespec t2; in aio_read_done() local 1429 t2 = tsub(t2, ctx->t1); in aio_read_done() [all …]
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/qemu/tests/qtest/ |
H A D | rtas-test.c | 14 time_t t1, t2; in run_test_rtas_get_time_of_day() local 21 t2 = mktimegm(&tm); in run_test_rtas_get_time_of_day() 22 g_assert(t2 - t1 < 5); /* 5 sec max to run the test */ in run_test_rtas_get_time_of_day()
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/qemu/host/include/aarch64/host/ |
H A D | atomic128-ldst.h | 63 uint64_t t1, t2; in atomic16_set() local 74 : [mem] "+m"(*ptr), [t1] "=&r"(t1), [t2] "=&r"(t2) in atomic16_set()
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/qemu/target/ppc/translate/ |
H A D | fp-impl.c.inc | 210 TCGv_i64 t0, t1, t2; 217 t2 = tcg_temp_new_i64(); 221 get_fpr(t2, a->frc); 223 gen_helper_FSEL(t0, t0, t1, t2); 462 TCGv_i64 t2; 469 t2 = tcg_temp_new_i64(); 472 tcg_gen_deposit_i64(t2, t0, t1, 0, 63); 473 set_fpr(rD(ctx->opcode), t2); 502 TCGv_i64 t2; 509 t2 = tcg_temp_new_i64(); [all …]
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/qemu/target/openrisc/ |
H A D | translate.c | 301 tcg_gen_ext_tl_i64(t2, srcb); in gen_muld() 344 tcg_gen_ext_tl_i64(t2, srcb); in gen_mac() 345 tcg_gen_mul_i64(t1, t1, t2); in gen_mac() 351 tcg_gen_andc_i64(t1, t1, t2); in gen_mac() 369 tcg_gen_mul_i64(t1, t1, t2); in gen_macu() 385 tcg_gen_ext_tl_i64(t2, srcb); in gen_msb() 386 tcg_gen_mul_i64(t1, t1, t2); in gen_msb() 392 tcg_gen_and_i64(t1, t1, t2); in gen_msb() 410 tcg_gen_mul_i64(t1, t1, t2); in gen_msbu() 1442 TCGv_i64 t0, t1, t2; in trans_lf_madd_d() local [all …]
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/qemu/linux-user/riscv/ |
H A D | vdso.S | 54 lw t2, 8(sp) /* timespec.tv_nsec.low */ 63 divu t2, t2, t3 /* nsec -> usec */ 65 sw t2, 4(a1) /* tz->tv_usec */
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/qemu/target/ppc/ |
H A D | translate.c | 1754 tcg_gen_and_i32(t2, t2, t3); in gen_op_arith_divw() 1756 tcg_gen_or_i32(t2, t2, t3); in gen_op_arith_divw() 1758 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); in gen_op_arith_divw() 1764 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); in gen_op_arith_divw() 1826 tcg_gen_and_i64(t2, t2, t3); in gen_op_arith_divd() 1828 tcg_gen_or_i64(t2, t2, t3); in gen_op_arith_divd() 1884 tcg_gen_and_i32(t2, t2, t3); in gen_op_arith_modw() 1886 tcg_gen_or_i32(t2, t2, t3); in gen_op_arith_modw() 1925 tcg_gen_and_i64(t2, t2, t3); in gen_op_arith_modd() 1927 tcg_gen_or_i64(t2, t2, t3); in gen_op_arith_modd() [all …]
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/qemu/common-user/host/riscv/ |
H A D | safe-syscall.inc.S | 66 li t2, -4096 67 bgtu a0, t2, 0f
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/qemu/common-user/host/loongarch64/ |
H A D | safe-syscall.inc.S | 78 li.w $t2, -4096 79 bgtu $a0, $t2, 0f
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/qemu/tests/tcg/loongarch64/system/ |
H A D | boot.S | 38 lu12i.w t2, 0x1fe00 39 ori t0, t2, 0x1e5
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