Home
last modified time | relevance | path

Searched refs:tail (Results 51 – 75 of 27221) sorted by relevance

12345678910>>...1089

/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
H A Dloop-prefetch.ll27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
58 tail call void @llvm.amdgcn.s.sleep(i32 0)
59 tail call void @llvm.amdgcn.s.sleep(i32 0)
60 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
H A Dloop-prefetch.ll27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
58 tail call void @llvm.amdgcn.s.sleep(i32 0)
59 tail call void @llvm.amdgcn.s.sleep(i32 0)
60 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
H A Dloop-prefetch.ll27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
58 tail call void @llvm.amdgcn.s.sleep(i32 0)
59 tail call void @llvm.amdgcn.s.sleep(i32 0)
60 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
H A Dloop-prefetch.ll27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
58 tail call void @llvm.amdgcn.s.sleep(i32 0)
59 tail call void @llvm.amdgcn.s.sleep(i32 0)
60 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
H A Dloop-prefetch.ll27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
58 tail call void @llvm.amdgcn.s.sleep(i32 0)
59 tail call void @llvm.amdgcn.s.sleep(i32 0)
60 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
H A Dloop-prefetch.ll27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
58 tail call void @llvm.amdgcn.s.sleep(i32 0)
59 tail call void @llvm.amdgcn.s.sleep(i32 0)
60 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
H A Dloop-prefetch.ll27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
58 tail call void @llvm.amdgcn.s.sleep(i32 0)
59 tail call void @llvm.amdgcn.s.sleep(i32 0)
60 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
H A Dloop-prefetch.ll27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
58 tail call void @llvm.amdgcn.s.sleep(i32 0)
59 tail call void @llvm.amdgcn.s.sleep(i32 0)
60 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
H A Dloop-prefetch.ll27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
58 tail call void @llvm.amdgcn.s.sleep(i32 0)
59 tail call void @llvm.amdgcn.s.sleep(i32 0)
60 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dbranch-relax-spill.ll10 %sgpr0 = tail call i32 asm sideeffect "s_mov_b32 s0, 0", "={s0}"() #0
11 %sgpr1 = tail call i32 asm sideeffect "s_mov_b32 s1, 0", "={s1}"() #0
12 %sgpr2 = tail call i32 asm sideeffect "s_mov_b32 s2, 0", "={s2}"() #0
13 %sgpr3 = tail call i32 asm sideeffect "s_mov_b32 s3, 0", "={s3}"() #0
14 %sgpr4 = tail call i32 asm sideeffect "s_mov_b32 s4, 0", "={s4}"() #0
15 %sgpr5 = tail call i32 asm sideeffect "s_mov_b32 s5, 0", "={s5}"() #0
16 %sgpr6 = tail call i32 asm sideeffect "s_mov_b32 s6, 0", "={s6}"() #0
17 %sgpr7 = tail call i32 asm sideeffect "s_mov_b32 s7, 0", "={s7}"() #0
18 %sgpr8 = tail call i32 asm sideeffect "s_mov_b32 s8, 0", "={s8}"() #0
19 %sgpr9 = tail call i32 asm sideeffect "s_mov_b32 s9, 0", "={s9}"() #0
[all …]
H A Dloop-prefetch.ll27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
58 tail call void @llvm.amdgcn.s.sleep(i32 0)
59 tail call void @llvm.amdgcn.s.sleep(i32 0)
60 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
/dports/mail/enma/enma-1.2.0/libsauth/include/
H A Dxskip.h75 extern int XSkip_casestring(const char *head, const char *tail, const char *str,
84 extern int XSkip_atom(const char *head, const char *tail, const char **nextp);
86 extern int XSkip_ctext(const char *head, const char *tail, const char **nextp);
94 extern int XSkip_word(const char *head, const char *tail, const char **nextp);
95 extern int XSkip_phrase(const char *head, const char *tail, const char **nextp);
100 extern int XSkip_cfws(const char *head, const char *tail, const char **nextp);
102 extern int XSkip_fws(const char *head, const char *tail, const char **nextp);
106 extern int XSkip_wsp(const char *head, const char *tail, const char **nextp);
109 extern int XSkip_alpha(const char *head, const char *tail, const char **nextp);
110 extern int XSkip_crlf(const char *head, const char *tail, const char **nextp);
[all …]

12345678910>>...1089