| /dragonfly/sys/dev/netif/ath/ath_hal/ar5210/ |
| H A D | ar5210_misc.c | 441 u_int clks = OS_REG_READ(ah, AR_IFS0) & 0x7ff; in ar5210GetSifsTime() local
466 u_int clks = OS_REG_READ(ah, AR_SLOT_TIME) & 0xffff; in ar5210GetSlotTime() local
492 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); in ar5210GetAckTimeout() local
539 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); in ar5210GetCTSTimeout() local
|
| /dragonfly/sys/dev/netif/ath/ath_hal/ar5211/ |
| H A D | ar5211_misc.c | 443 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff; in ar5211GetSifsTime() local
468 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff; in ar5211GetSlotTime() local
494 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); in ar5211GetAckTimeout() local
541 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); in ar5211GetCTSTimeout() local
|
| /dragonfly/sys/dev/drm/amd/display/dc/inc/hw/ |
| H A D | display_clock.h | 45 struct dc_clocks clks; member
|
| /dragonfly/sys/dev/netif/ath/ath_hal/ar5212/ |
| H A D | ar5212_misc.c | 468 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff; in ar5212GetSifsTime() local
493 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff; in ar5212GetSlotTime() local
519 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); in ar5212GetAckTimeout() local
566 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); in ar5212GetCTSTimeout() local
|
| /dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_freebsd.c | 56 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff; in ar9300GetSlotTime() local
96 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); in ar9300_freebsd_get_cts_timeout() local
|
| H A D | ar9300_misc.c | 65 ar9300_mac_to_usec(struct ath_hal *ah, u_int clks) in ar9300_mac_to_usec()
606 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); in ar9300_get_ack_timeout() local
|
| /dragonfly/sys/dev/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_pp_smu.c | 123 struct dm_pp_clock_levels *clks) in get_default_clock_levels()
|
| H A D | amdgpu_dm_helpers.c | 550 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) in dm_set_dcn_clocks()
|
| /dragonfly/sys/dev/netif/ath/ath_hal/ |
| H A D | ah.c | 509 u_int clks; in ath_hal_mac_clks() local
534 ath_hal_mac_usec(struct ath_hal *ah, u_int clks) in ath_hal_mac_usec()
|
| /dragonfly/sys/dev/drm/amd/display/dc/calcs/ |
| H A D | dcn_calcs.c | 1330 static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) in verify_clock_values()
|
| /dragonfly/sys/dev/drm/amd/display/dc/dce112/ |
| H A D | dce112_resource.c | 943 struct dm_pp_clock_levels clks = {0}; in bw_calcs_data_update_from_pplib() local
|
| /dragonfly/sys/dev/drm/amd/display/dc/dce110/ |
| H A D | dce110_resource.c | 1089 struct dm_pp_clock_levels clks = {0}; in bw_calcs_data_update_from_pplib() local
|
| /dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
| H A D | smu8_hwmgr.c | 752 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold() local
|
| /dragonfly/sys/dev/drm/amd/powerplay/smumgr/ |
| H A D | iceland_smumgr.c | 1132 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; in iceland_calculate_mclk_params() local
|
| H A D | tonga_smumgr.c | 874 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; in tonga_calculate_mclk_params() local
|
| H A D | ci_smumgr.c | 1085 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; in ci_calculate_mclk_params() local
|
| /dragonfly/sys/dev/drm/radeon/ |
| H A D | ci_dpm.c | 2876 u32 clks = reference_clock * 5 / ss.rate; in ci_calculate_mclk_params() local
|
| H A D | si_dpm.c | 4927 u32 clks = reference_clock * 5 / ss.rate; in si_populate_mclk_value() local
|
| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | si_dpm.c | 5390 u32 clks = reference_clock * 5 / ss.rate; in si_populate_mclk_value() local
|