| /dports/sysutils/u-boot-rock64/u-boot-2021.07/board/ti/ks2_evm/ |
| H A D | board_k2g.c | 64 int speeds[DEVSPEED_NUMSPDS] = { variable
|
| /dports/math/wcalc/wcalc-2.5/src/common/ |
| H A D | conversion.c | 700 const struct conversion speeds[] = { variable
|
| /dports/net/measurement-kit/measurement-kit-0.10.14/src/libmeasurement_kit/ndt/ |
| H A D | utils.cpp | 55 std::vector<double> speeds; in compute_speed_throws() local
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|