/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | MachineCopyPropagation.cpp | 215 if (MO.clobbersPhysReg(AvailSrc) || MO.clobbersPhysReg(AvailDef)) in findAvailBackwardCopy() 240 if (MO.clobbersPhysReg(AvailSrc) || MO.clobbersPhysReg(AvailDef)) in findAvailCopy() 615 if (!MO.isReg() || !MO.readsReg()) in ForwardCopyPropagateBlock() 638 if (!MO.isReg() || !MO.isDef()) in ForwardCopyPropagateBlock() 653 if (MO.isReg() && MO.isEarlyClobber()) { in ForwardCopyPropagateBlock() 670 RegMask = &MO; in ForwardCopyPropagateBlock() 671 if (!MO.isReg()) in ForwardCopyPropagateBlock() 680 if (MO.isDef() && !MO.isEarlyClobber()) { in ForwardCopyPropagateBlock() 855 if (MO.isReg() && MO.isEarlyClobber()) { in BackwardCopyPropagateBlock() 864 if (!MO.isReg()) in BackwardCopyPropagateBlock() [all …]
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H A D | RenameIndependentSubregs.cpp | 180 if (!MO.isDef() && !MO.readsReg()) in findComponents() 190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in findComponents() 218 MachineOperand &MO = *I++; in rewriteOperands() local 219 if (!MO.isDef() && !MO.readsReg()) in rewriteOperands() 224 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in rewriteOperands() 246 MO.setReg(VReg); in rewriteOperands() 346 if (!MO.isDef()) in computeMainRangesFixFlags() 354 if (!MO.isUndef()) { in computeMainRangesFixFlags() 357 MO.setIsUndef(); in computeMainRangesFixFlags() 359 if (!MO.isDead()) { in computeMainRangesFixFlags() [all …]
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H A D | MachineCSE.cpp | 170 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY() 204 MO.setReg(SrcReg); in INITIALIZE_PASS_DEPENDENCY() 236 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) in isPhysDefTriviallyDead() 238 if (!MO.isReg() || !MO.getReg()) in isPhysDefTriviallyDead() 242 if (MO.isUse()) in isPhysDefTriviallyDead() 284 if (!MO.isReg() || MO.isDef()) in hasLivePhysRegDefUses() 303 if (!MO.isReg() || !MO.isDef()) in hasLivePhysRegDefUses() 380 if (!MO.isReg() || !MO.isDef()) in PhysRegDefsReach() 467 if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) { in isProfitableToCSE() 614 if (!MO.isReg() || !MO.isDef()) in ProcessBlockCSE() [all …]
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H A D | MachineSink.cpp | 405 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) in FindLoopSinkCandidates() 571 if (MO.isReg() && MO.getReg().isVirtual()) in ProcessDbgInst() 602 if (!MO.isReg() || !MO.isUse()) in isWorthBreakingCriticalEdge() 800 if (!MO.isReg()) in isProfitableToSinkTo() 811 if (MO.isDef()) { in isProfitableToSinkTo() 1406 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual()) in SinkInstruction() 1441 if (MO.isReg() && MO.isUse()) in SinkInstruction() 1460 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual()) in SalvageUnsunkDebugUsersOfCopy() 1663 if (!MO.isReg()) in hasRegisterDependency() 1736 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) { in tryToSinkCopy() [all …]
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H A D | TwoAddressInstructionPass.cpp | 363 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse() 771 if (!MO.isReg()) in rescheduleMIBelowKill() 776 if (MO.isDef()) in rescheduleMIBelowKill() 952 if (!MO.isReg()) in rescheduleKillAboveMI() 955 if (MO.isUse()) { in rescheduleKillAboveMI() 1255 if (MO.isReg() && MO.getReg().isVirtual()) { in tryInstructionTransform() 1444 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs() 1454 MO.setReg(RegA); in processTiedPairs() 1458 MO.setSubReg(0); in processTiedPairs() 1469 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs() [all …]
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H A D | MIRCanonicalizerPass.cpp | 165 if (!MO.isReg()) in rescheduleCanonically() 171 if (!MO.isDef()) in rescheduleCanonically() 185 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg())) in rescheduleCanonically() 187 if (!MO.isDef()) in rescheduleCanonically() 337 for (auto *MO : Uses) in propagateLocalCopies() local 338 MO->setReg(Src); in propagateLocalCopies() 352 if (!MO.isReg()) in doDefKillClear() 354 if (!MO.isDef() && MO.isKill()) { in doDefKillClear() 356 MO.setIsKill(false); in doDefKillClear() 359 if (MO.isDef() && MO.isDead()) { in doDefKillClear() [all …]
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H A D | ProcessImplicitDefs.cpp | 69 for (const MachineOperand &MO : MI->operands()) in canTurnIntoImplicitDef() local 70 if (MO.isReg() && MO.isUse() && MO.readsReg()) in canTurnIntoImplicitDef() 82 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { in processImplicitDef() 83 MO.setIsUndef(); in processImplicitDef() 84 MachineInstr *UserMI = MO.getParent(); in processImplicitDef() 101 for (MachineOperand &MO : UserMI->operands()) { in processImplicitDef() 102 if (!MO.isReg()) in processImplicitDef() 104 Register UserReg = MO.getReg(); in processImplicitDef() 110 if (MO.isUse()) in processImplicitDef() 111 MO.setIsUndef(); in processImplicitDef()
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H A D | MachineVerifier.cpp | 497 assert(MO); in report() 832 if (!MO.isImm()) in verifyInlineAsm() 847 if (!MO.isReg() || !MO.isImplicit()) in verifyInlineAsm() 935 if (MO->isReg() && Register::isPhysicalRegister(MO->getReg())) in verifyPreISelGenericInstruction() 1790 if (!MO->isReg()) in visitMachineOperand() 1811 !MO->isReg() && !MO->isFI()) in visitMachineOperand() 1837 } else if (MO->isReg() && MO->isTied()) in visitMachineOperand() 1841 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg()) in visitMachineOperand() 1913 if (MI->isDebugValue() && MO->isUse() && !MO->isDebug()) { in visitMachineOperand() 2139 if (MO->isDead()) { in checkLivenessAtDef() [all …]
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H A D | LivePhysRegs.cpp | 31 void LivePhysRegs::removeRegsInMask(const MachineOperand &MO, in removeRegsInMask() argument 35 if (MO.clobbersPhysReg(*LRI)) { in removeRegsInMask() 37 Clobbers->push_back(std::make_pair(*LRI, &MO)); in removeRegsInMask() 288 for (MIBundleOperands MO(MI); MO.isValid(); ++MO) { in recomputeLivenessFlags() local 289 if (!MO->isReg() || !MO->isDef() || MO->isDebug()) in recomputeLivenessFlags() 292 Register Reg = MO->getReg(); in recomputeLivenessFlags() 310 MO->setIsDead(IsNotLive); in recomputeLivenessFlags() 317 for (MIBundleOperands MO(MI); MO.isValid(); ++MO) { in recomputeLivenessFlags() local 318 if (!MO->isReg() || !MO->readsReg() || MO->isDebug()) in recomputeLivenessFlags() 321 Register Reg = MO->getReg(); in recomputeLivenessFlags() [all …]
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H A D | VirtRegMap.cpp | 369 if (MO.isUndef()) in readsUndefSubreg() 372 Register Reg = MO.getReg(); in readsUndefSubreg() 538 if (MO.isRegMask()) in rewrite() 541 if (!MO.isReg() || !MO.getReg().isVirtual()) in rewrite() 560 if ((MO.readsReg() && (MO.isDef() || MO.isKill())) || in rewrite() 564 if (MO.isDef()) { in rewrite() 566 if (MO.isDead()) in rewrite() 572 if (MO.isUse()) { in rewrite() 587 if (MO.isDef()) { in rewrite() 595 MO.setSubReg(0); in rewrite() [all …]
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H A D | ScheduleDAGInstrs.cpp | 210 if (!MO.isReg() || MO.isDef()) continue; in addSchedBarrierDeps() 328 if (!MO.isDef()) { in addPhysRegDeps() 343 if (!MO.isDead()) in addPhysRegDeps() 403 bool IsKill = MO.getSubReg() == 0 || MO.isUndef(); in addVRegDefDeps() 409 if (MO.getSubReg() != 0 && MO.isUndef()) { in addVRegDefDeps() 423 MO.setIsUndef(false); in addVRegDefDeps() 429 if (MO.isDead()) { in addVRegDefDeps() 851 if (!MO.isReg() || !MO.isDef()) in buildSchedGraph() 868 if (!MO.isReg() || !MO.isUse()) in buildSchedGraph() 1101 if (!MO.isReg() || !MO.readsReg()) in toggleKills() [all …]
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H A D | BreakFalseDeps.cpp | 114 MachineOperand &MO = MI->getOperand(OpIdx); in pickBestRegisterForUndef() local 115 assert(MO.isUndef() && "Expected undef machine operand"); in pickBestRegisterForUndef() 118 if (!MO.isRenamable()) in pickBestRegisterForUndef() 121 MCRegister OriginalReg = MO.getReg().asMCReg(); in pickBestRegisterForUndef() 145 MO.setReg(CurrMO.getReg()); in pickBestRegisterForUndef() 167 MO.setReg(MaxClearanceReg); in pickBestRegisterForUndef() 194 MachineOperand &MO = MI->getOperand(i); in processDefs() local 195 if (!MO.isReg() || !MO.getReg() || !MO.isUse() || !MO.isUndef()) in processDefs() 217 MachineOperand &MO = MI->getOperand(i); in processDefs() local 218 if (!MO.isReg() || !MO.getReg()) in processDefs() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVAsmPrinter.cpp | 65 return LowerRISCVMachineOperandToMCOperand(MO, MCOp, *this); in lowerOperand() 106 const MachineOperand &MO = MI->getOperand(OpNo); in PrintAsmOperand() local 115 if (MO.isImm() && MO.getImm() == 0) { in PrintAsmOperand() 121 if (!MO.isReg()) in PrintAsmOperand() 127 switch (MO.getType()) { in PrintAsmOperand() 129 OS << MO.getImm(); in PrintAsmOperand() 132 OS << RISCVInstPrinter::getRegisterName(MO.getReg()); in PrintAsmOperand() 135 PrintSymbolOperand(MO, OS); in PrintAsmOperand() 138 MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress()); in PrintAsmOperand() 154 const MachineOperand &MO = MI->getOperand(OpNo); in PrintAsmMemoryOperand() local [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 217 if (MO.isExpr()) { in getLitEncoding() 225 assert(!MO.isDFPImm()); in getLitEncoding() 227 if (!MO.isImm()) in getLitEncoding() 230 Imm = MO.getImm(); in getLitEncoding() 382 if (MO.isExpr()) { in getSOPPBrEncoding() 411 if (MO.isReg()) { in getSDWASrcEncoding() 441 unsigned Reg = MO.getReg(); in getSDWAVopcDstEncoding() 500 if (MO.isReg()) in getMachineOpValue() 503 if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) { in getMachineOpValue() 542 } else if (MO.isImm()) in getMachineOpValue() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUMCInstLower.cpp | 100 const MachineOperand &MO) const { in getLongBranchBlockExpr() 102 = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx); in getLongBranchBlockExpr() 126 switch (MO.getType()) { in lowerOperand() 130 MCOp = MCOperand::createImm(MO.getImm()); in lowerOperand() 136 if (MO.getTargetFlags() != 0) { in lowerOperand() 138 getLongBranchBlockExpr(*MO.getParent()->getParent(), MO)); in lowerOperand() 147 const GlobalValue *GV = MO.getGlobal(); in lowerOperand() 153 int64_t Offset = MO.getOffset(); in lowerOperand() 209 lowerOperand(MO, MCOp); in lower() 222 return MCInstLowering.lowerOperand(MO, MCOp); in lowerOperand() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/ |
H A D | WebAssemblyUtilities.cpp | 32 const MachineOperand &MO = MI.getOperand(0); in isChild() local 33 if (!MO.isReg() || MO.isImplicit() || !MO.isDef()) in isChild() 35 Register Reg = MO.getReg(); in isChild() 52 const MachineOperand &MO = getCalleeOp(MI); in mayThrow() local 53 assert(MO.isGlobal() || MO.isSymbol()); in mayThrow() 55 if (MO.isSymbol()) { in mayThrow() 61 const char *Name = MO.getSymbolName(); in mayThrow() 68 const auto *F = dyn_cast<Function>(MO.getGlobal()); in mayThrow()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonVLIWPacketizer.cpp | 151 if (!MO.isReg() || !MO.isDef()) in hasWriteToReadDep() 321 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit()) in isCallDependent() 438 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur() 586 if (MO.isReg() && MO.isDef()) in getPostIncrementOperand() 590 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand() 787 if (MO.isReg() && MO.getReg() == DepReg) in canPromoteToNewValueStore() 799 if (!MO.isReg() || !MO.isDef() || !MO.isImplicit()) in canPromoteToNewValueStore() 812 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg) in canPromoteToNewValueStore() 842 if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit()) in isImplicitDependency() 1212 if (!MO.isReg() || !MO.isDef() || !MO.isDead()) in hasDeadDependence() [all …]
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H A D | HexagonAsmPrinter.cpp | 79 switch (MO.getType()) { in printOperand() 86 O << MO.getImm(); in printOperand() 95 PrintSymbolOperand(MO, O); in printOperand() 131 if (!MO.isReg()) in PrintAsmOperand() 217 assert(MO.isGlobal() || MO.isCPI() || MO.isJTI()); in smallData() 219 if (MO.isGlobal()) in smallData() 221 else if (MO.isCPI()) in smallData() 223 else if (MO.isJTI()) in smallData() 542 MO.setReg(High); in HexagonProcessInstruction() 554 MO.setReg(High); in HexagonProcessInstruction() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
H A D | LanaiAsmPrinter.cpp | 66 const MachineOperand &MO = MI->getOperand(OpNum); in printOperand() local 68 switch (MO.getType()) { in printOperand() 70 O << LanaiInstPrinter::getRegisterName(MO.getReg()); in printOperand() 74 O << MO.getImm(); in printOperand() 78 O << *MO.getMBB()->getSymbol(); in printOperand() 82 O << *getSymbol(MO.getGlobal()); in printOperand() 92 O << *GetExternalSymbolSymbol(MO.getSymbolName()); in printOperand() 97 << MO.getIndex(); in printOperand() 102 << MO.getIndex(); in printOperand() 134 if (!MO.isReg()) in PrintAsmOperand() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegBankSelect.cpp | 149 Register Src = MO.getReg(); in repairReg() 154 if (MO.isDef()) in repairReg() 175 if (MO.isDef()) { in repairReg() 195 .addDef(MO.getReg()); in repairReg() 238 const MachineOperand &MO, in getRepairCost() argument 266 if (MO.isDef()) in getRepairCost() 342 if (!MO.isDef()) { in tryAvoidingSplit() 401 Register Reg = MO.getReg(); in tryAvoidingSplit() 470 if (!MO.isReg()) in computeMapping() 472 Register Reg = MO.getReg(); in computeMapping() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/CSKY/MCTargetDesc/ |
H A D | CSKYInstPrinter.cpp | 79 const MCOperand &MO = MI->getOperand(OpNo); in printOperand() local 81 if (MO.isReg()) { in printOperand() 82 if (MO.getReg() == CSKY::C) in printOperand() 85 printRegName(O, MO.getReg()); in printOperand() 89 if (MO.isImm()) { in printOperand() 90 O << formatImm(MO.getImm()); in printOperand() 94 assert(MO.isExpr() && "Unknown operand kind in printOperand"); in printOperand() 95 MO.getExpr()->print(O, &MAI); in printOperand()
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H A D | CSKYMCCodeEmitter.cpp | 29 const MCOperand &MO = MI.getOperand(Idx); in getOImmOpValue() local 30 assert(MO.isImm() && "Unexpected MO type."); in getOImmOpValue() 31 return MO.getImm() - 1; in getOImmOpValue() 52 CSKYMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() argument 55 if (MO.isReg()) in getMachineOpValue() 56 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue() 58 if (MO.isImm()) in getMachineOpValue() 59 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonInstPrinter.cpp | 67 MCOperand const &MO = MI->getOperand(OpNo); in printOperand() local 68 if (MO.isReg()) { in printOperand() 69 O << getRegisterName(MO.getReg()); in printOperand() 70 } else if (MO.isExpr()) { in printOperand() 72 if (MO.getExpr()->evaluateAsAbsolute(Value)) in printOperand() 75 O << *MO.getExpr(); in printOperand() 83 MCOperand const &MO = MI->getOperand(OpNo); in printBrtarget() local 84 assert (MO.isExpr()); in printBrtarget() 85 MCExpr const &Expr = *MO.getExpr(); in printBrtarget()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Transforms/Instrumentation/ |
H A D | PGOMemOPSizeOpt.cpp | 235 for (auto &MO : WorkList) { in perform() local 237 if (perform(MO)) { in perform() 273 bool perform(MemOp MO); 295 assert(MO.I); in perform() 296 if (MO.isMemmove()) in perform() 298 if (!MemOPOptMemcmpBcmp && (MO.isMemcmp(TLI) || MO.isBcmp(TLI))) in perform() 425 BasicBlock::iterator It(*MO.I); in perform() 437 Value *SizeVar = MO.getLength(); in perform() 439 Type *MemOpTy = MO.I->getType(); in perform() 445 MO.I->replaceAllUsesWith(PHI); in perform() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 301 if (!MO.isReg() || MO.isUndef() || MO.isUse()) in canAddPseudoFlagDep() 310 if (!MO.isReg() || MO.isUndef() || MO.isDef()) in canAddPseudoFlagDep() 381 if (!MO.isReg() || MO.isImplicit()) in VerifyLowRegs() 880 if (MO.isReg()) { in ReduceToNarrow() 962 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) in ReduceToNarrow() 966 MIB.add(MO); in ReduceToNarrow() 985 if (!MO.isReg() || MO.isUndef() || MO.isUse()) in UpdateCPSRDef() 991 if (!MO.isDead()) in UpdateCPSRDef() 1000 if (!MO.isReg() || MO.isUndef() || MO.isDef()) in UpdateCPSRUse() 1101 if (MO && !MO->isDead()) in ReduceMBB() [all …]
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