Home
last modified time | relevance | path

Searched refs:ICR (Results 1 – 25 of 825) sorted by relevance

12345678910>>...33

/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/cpu/pxa/
H A Di2c.c96 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
99 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
108 ICR |= ICR_IUE; /* enable unit */ in i2c_reset()
162 ICR &= ~ICR_START; in i2c_transfer()
163 ICR &= ~ICR_STOP; in i2c_transfer()
169 ICR &= ~ICR_ALDIE; in i2c_transfer()
170 ICR |= ICR_TB; in i2c_transfer()
192 ICR &= ~ICR_START; in i2c_transfer()
193 ICR &= ~ICR_STOP; in i2c_transfer()
198 ICR &= ~ICR_ALDIE; in i2c_transfer()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/arm/cpu/pxa/
H A Di2c.c96 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
99 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
108 ICR |= ICR_IUE; /* enable unit */ in i2c_reset()
162 ICR &= ~ICR_START; in i2c_transfer()
163 ICR &= ~ICR_STOP; in i2c_transfer()
169 ICR &= ~ICR_ALDIE; in i2c_transfer()
170 ICR |= ICR_TB; in i2c_transfer()
192 ICR &= ~ICR_START; in i2c_transfer()
193 ICR &= ~ICR_STOP; in i2c_transfer()
198 ICR &= ~ICR_ALDIE; in i2c_transfer()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/arm/cpu/pxa/
H A Di2c.c96 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
99 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
108 ICR |= ICR_IUE; /* enable unit */ in i2c_reset()
162 ICR &= ~ICR_START; in i2c_transfer()
163 ICR &= ~ICR_STOP; in i2c_transfer()
169 ICR &= ~ICR_ALDIE; in i2c_transfer()
170 ICR |= ICR_TB; in i2c_transfer()
192 ICR &= ~ICR_START; in i2c_transfer()
193 ICR &= ~ICR_STOP; in i2c_transfer()
198 ICR &= ~ICR_ALDIE; in i2c_transfer()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/arm/cpu/pxa/
H A Di2c.c96 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
99 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
108 ICR |= ICR_IUE; /* enable unit */ in i2c_reset()
162 ICR &= ~ICR_START; in i2c_transfer()
163 ICR &= ~ICR_STOP; in i2c_transfer()
169 ICR &= ~ICR_ALDIE; in i2c_transfer()
170 ICR |= ICR_TB; in i2c_transfer()
192 ICR &= ~ICR_START; in i2c_transfer()
193 ICR &= ~ICR_STOP; in i2c_transfer()
198 ICR &= ~ICR_ALDIE; in i2c_transfer()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/cpu/pxa/
H A Di2c.c96 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
99 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
108 ICR |= ICR_IUE; /* enable unit */ in i2c_reset()
162 ICR &= ~ICR_START; in i2c_transfer()
163 ICR &= ~ICR_STOP; in i2c_transfer()
169 ICR &= ~ICR_ALDIE; in i2c_transfer()
170 ICR |= ICR_TB; in i2c_transfer()
192 ICR &= ~ICR_START; in i2c_transfer()
193 ICR &= ~ICR_STOP; in i2c_transfer()
198 ICR &= ~ICR_ALDIE; in i2c_transfer()
[all …]
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/arm/cpu/pxa/
H A Di2c.c96 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
99 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
108 ICR |= ICR_IUE; /* enable unit */ in i2c_reset()
162 ICR &= ~ICR_START; in i2c_transfer()
163 ICR &= ~ICR_STOP; in i2c_transfer()
169 ICR &= ~ICR_ALDIE; in i2c_transfer()
170 ICR |= ICR_TB; in i2c_transfer()
192 ICR &= ~ICR_START; in i2c_transfer()
193 ICR &= ~ICR_STOP; in i2c_transfer()
198 ICR &= ~ICR_ALDIE; in i2c_transfer()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/arm/cpu/pxa/
H A Di2c.c96 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
99 ICR &= ~ICR_IUE; /* disable unit */ in i2c_reset()
108 ICR |= ICR_IUE; /* enable unit */ in i2c_reset()
162 ICR &= ~ICR_START; in i2c_transfer()
163 ICR &= ~ICR_STOP; in i2c_transfer()
169 ICR &= ~ICR_ALDIE; in i2c_transfer()
170 ICR |= ICR_TB; in i2c_transfer()
192 ICR &= ~ICR_START; in i2c_transfer()
193 ICR &= ~ICR_STOP; in i2c_transfer()
198 ICR &= ~ICR_ALDIE; in i2c_transfer()
[all …]
/dports/net-mgmt/observium/observium/mibs/redback/
H A DRBN-ICR-MIB2 -- RBN-ICR-MIB Ericsson Inter Chassis Resilience(ICR) MIB
9 RBN-ICR-MIB DEFINITIONS ::= BEGIN
41 Resilience(ICR)."
53 -- Inter Chassis Resilience(ICR) Table
60 "This table consists of ICR management objects."
94 "The unique identifier of the ICR node."
153 to send/receive ICR messages."
206 "The current ICR state:
265 -- ICR Notifications
436 "Conformance group for ICR objects."
[all …]
/dports/devel/asl/asl-current/include/avr/
H A Dregtn28.inc48 ICR port 0x06 ; Interrupt Control Register
49 LLIE avrbit ICR,5 ; Port B Low Level Interrupt Enable
64 ISC00 avrbit ICR,0 ; Interrupt Sense Control 0
65 ISC01 avrbit ICR,1
66 ISC10 avrbit ICR,2 ; Interrupt Sense Control 1
67 ISC11 avrbit ICR,3
68 INT0 avrbit ICR,6 ; Enable External Interrupt 0
69 INT1 avrbit ICR,7 ; Enable External Interrupt 1
97 TOIE0 avrbit ICR,3 ; Timer/Counter 0 Overflow Interrupt Enable
/dports/devel/asl/asl-current/include/stm8/stm8l/
H A Dspi01.inc32 {__NS}ICR label Base+$02 ; interrupt control register
33 {__NS}TXIE bit {__NS}ICR,7 ; Tx buffer empty interrupt enable
34 {__NS}RXIE bit {__NS}ICR,6 ; RX buffer not empty interrupt enable
35 {__NS}ERRIE bit {__NS}ICR,5 ; Error interrupt enable
36 {__NS}WKIE bit {__NS}ICR,4 ; Wakeup interrupt enable
37 {__NS}TXDMAEN bit {__NS}ICR,1 ; Tx Buffer DMA Enable
38 {__NS}RXDMAEN bit {__NS}ICR,0 ; Rx Buffer DMA Enable
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/wireless/ath/wil6210/
H A Dinterrupt.c295 offsetof(struct RGF_ICR, ICR)); in wil6210_irq_rx()
688 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
696 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
705 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
713 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
722 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
845 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
847 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
849 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
851 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/wireless/ath/wil6210/
H A Dinterrupt.c295 offsetof(struct RGF_ICR, ICR)); in wil6210_irq_rx()
688 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
696 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
705 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
713 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
722 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
845 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
847 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
849 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
851 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/wireless/ath/wil6210/
H A Dinterrupt.c295 offsetof(struct RGF_ICR, ICR)); in wil6210_irq_rx()
688 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
696 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
705 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
713 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
722 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
845 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
847 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
849 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
851 offsetof(struct RGF_ICR, ICR)); in wil6210_clear_irq()
[all …]
/dports/games/libretro-mame2003/mame2003-libretro-4358db4/src/machine/
H A Dtmp68301.c34 data16_t ICR = tmp68301_regs[0x8e/2+i]; // Interrupt Controller Register (ICR7..9) in tmp68301_timer_callback() local
43 int level = ICR & 0x0007; in tmp68301_timer_callback()
138 data16_t ICR = tmp68301_regs[0x80/2+i]; // Interrupt Controller Register (ICR0..2) in update_irq_state() local
141 int level = ICR & 0x0007; in update_irq_state()
/dports/games/libretro-mame2003_plus/mame2003-plus-libretro-17e9889/src/machine/
H A Dtmp68301.c34 data16_t ICR = tmp68301_regs[0x8e/2+i]; /* Interrupt Controller Register (ICR7..9)*/ in tmp68301_timer_callback() local
43 int level = ICR & 0x0007; in tmp68301_timer_callback()
138 data16_t ICR = tmp68301_regs[0x80/2+i]; /* Interrupt Controller Register (ICR0..2)*/ in update_irq_state() local
141 int level = ICR & 0x0007; in update_irq_state()
/dports/security/py-pyvex/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_hal.h614 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
615 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
616 MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
634 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
635 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
636 MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
654 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
655 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
656 MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
674 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
[all …]
/dports/devel/py-cle/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_hal.h614 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
615 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
616 MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
634 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
635 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
636 MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
654 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
655 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
656 MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
674 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
[all …]
/dports/security/py-ailment/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_hal.h614 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
615 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
616 MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
634 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
635 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
636 MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
654 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
655 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
656 MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
674 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
[all …]
/dports/security/py-angr/binaries-9.0.5405/tests_src/i2c_master_read-nucleol152re/mbed/TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/
H A Dstm32l1xx_hal.h614 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
615 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
616 MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
634 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
635 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
636 MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
654 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
655 SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
656 MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
674 MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
[all …]
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F0xx_StdPeriph_Driver/src/
H A Dstm32f0xx_crs.c394 CRS->ICR |= CRS_ICR_ERRC; in CRS_ClearFlag()
398 CRS->ICR |= CRS_FLAG; in CRS_ClearFlag()
443 CRS->ICR |= CRS_ICR_ERRC; in CRS_ClearITPendingBit()
447 CRS->ICR |= CRS_IT; in CRS_ClearITPendingBit()
/dports/emulators/mess/mame-mame0226/src/devices/cpu/dsp56156/
H A Ddsp56mem.cpp194 ICR &= ~(0x10); in HF1_bit_host_set()
195 ICR |= (value << 4); in HF1_bit_host_set()
202 ICR &= ~(0x08); in HF0_bit_host_set()
203 ICR |= (value << 3); in HF0_bit_host_set()
210 ICR &= ~(0x02); in TREQ_bit_set()
211 ICR |= (value << 1); in TREQ_bit_set()
216 ICR &= ~(0x01); in RREQ_bit_set()
217 ICR |= (value << 0); in RREQ_bit_set()
891 return ICR; in host_interface_read()
/dports/emulators/mame/mame-mame0226/src/devices/cpu/dsp56156/
H A Ddsp56mem.cpp194 ICR &= ~(0x10); in HF1_bit_host_set()
195 ICR |= (value << 4); in HF1_bit_host_set()
202 ICR &= ~(0x08); in HF0_bit_host_set()
203 ICR |= (value << 3); in HF0_bit_host_set()
210 ICR &= ~(0x02); in TREQ_bit_set()
211 ICR |= (value << 1); in TREQ_bit_set()
216 ICR &= ~(0x01); in RREQ_bit_set()
217 ICR |= (value << 0); in RREQ_bit_set()
891 return ICR; in host_interface_read()
/dports/games/libretro-mu/Mu-ff746b8/src/pxa260/
H A Dpxa260I2c.c16 #define ICR 0x1690 macro
55 case ICR: in pxa260I2cReadWord()
82 case ICR: in pxa260I2cWriteWord()
/dports/math/slatec/src/
H A Ddsoseq.f95 INTEGER IC, ICR, IFLAG, IPRINT, IS(*), ISJ, ISV, IT, ITEM, ITRY,
115 ICR = 0
405 ICR = ICR + 1
406 IF (ICR .GE. NSRRC) GO TO 280
416 ICR = 0
/dports/multimedia/v4l_compat/linux-5.13-rc2/sound/pcmcia/vx/
H A Dvxp_ops.c153 vx_outb(chip, ICR, 0); in vxp_load_xilinx_binary()
161 vx_outb(chip, ICR, ICR_HF1); in vxp_load_xilinx_binary()
177 vx_outb(chip, ICR, 0); in vxp_load_xilinx_binary()
193 vx_outb(chip, ICR, ICR_HF0); in vxp_load_xilinx_binary()
316 vx_outb(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ); in vx_setup_pseudo_dma()
341 vx_outb(chip, ICR, 0); in vx_release_pseudo_dma()
425 vx_outb(chip, ICR, 0); in vxp_dma_read()

12345678910>>...33