/netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 2398 { ISD::CTTZ, MVT::v8i64, 10 }, in getTypeBasedIntrinsicInstrCost() 2399 { ISD::CTTZ, MVT::v16i32, 14 }, in getTypeBasedIntrinsicInstrCost() 2400 { ISD::CTTZ, MVT::v32i16, 12 }, in getTypeBasedIntrinsicInstrCost() 2401 { ISD::CTTZ, MVT::v64i8, 9 }, in getTypeBasedIntrinsicInstrCost() 2438 { ISD::CTTZ, MVT::v8i64, 20 }, in getTypeBasedIntrinsicInstrCost() 2439 { ISD::CTTZ, MVT::v16i32, 28 }, in getTypeBasedIntrinsicInstrCost() 2440 { ISD::CTTZ, MVT::v32i16, 24 }, in getTypeBasedIntrinsicInstrCost() 2441 { ISD::CTTZ, MVT::v64i8, 18 }, in getTypeBasedIntrinsicInstrCost() 2525 { ISD::CTTZ, MVT::v4i64, 10 }, in getTypeBasedIntrinsicInstrCost() 2670 { ISD::CTTZ, MVT::v16i8, 9 } in getTypeBasedIntrinsicInstrCost() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 657 CTTZ, enumerator
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H A D | BasicTTIImpl.h | 1836 ISDs.push_back(ISD::CTTZ); in getTypeBasedIntrinsicInstrCost()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 112 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering() 172 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering() 2073 case ISD::CTTZ: in LowerHvxOperation() 2110 case ISD::CTTZ: return LowerHvxCttz(Op, DAG); in LowerHvxOperation()
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H A D | HexagonISelLowering.cpp | 1564 setOperationAction(ISD::CTTZ, MVT::i8, Promote); in HexagonTargetLowering() 1565 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in HexagonTargetLowering() 1635 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, in HexagonTargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 393 case ISD::CTTZ: in LegalizeOp() 797 case ISD::CTTZ: in Expand()
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H A D | SelectionDAGDumper.cpp | 425 case ISD::CTTZ: return "cttz"; in getOperationName()
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H A D | LegalizeDAG.cpp | 2686 case ISD::CTTZ: in ExpandNode() 4394 case ISD::CTTZ: in PromoteNode() 4400 if (Node->getOpcode() == ISD::CTTZ || in PromoteNode() 4406 if (Node->getOpcode() == ISD::CTTZ) { in PromoteNode()
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H A D | LegalizeIntegerTypes.cpp | 68 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; in PromoteIntegerResult() 549 if (N->getOpcode() == ISD::CTTZ) { in PromoteIntRes_CTTZ() 2082 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; in ExpandIntegerResult()
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H A D | LegalizeVectorTypes.cpp | 79 case ISD::CTTZ: in ScalarizeVectorResult() 970 case ISD::CTTZ: in SplitVectorResult() 3145 case ISD::CTTZ: in WidenVectorResult()
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H A D | TargetLowering.cpp | 7066 isOperationLegalOrCustom(ISD::CTTZ, VT)) { in expandCTTZ() 7067 Result = DAG.getNode(ISD::CTTZ, dl, VT, Op); in expandCTTZ() 7075 SDValue CTTZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, VT, Op); in expandCTTZ() local 7079 DAG.getConstant(NumBitsPerElt, dl, VT), CTTZ); in expandCTTZ()
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H A D | SelectionDAG.cpp | 3163 case ISD::CTTZ: in computeKnownBits() 4653 case ISD::CTTZ: in getNode() 4771 case ISD::CTTZ: in getNode() 5007 case ISD::CTTZ: in getNode()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 104 setOperationAction(ISD::CTTZ, MVT::i8, Expand); in MSP430TargetLowering() 105 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in MSP430TargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 129 setOperationAction(ISD::CTTZ, MVT::i64, Custom); in BPFTargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 374 setOperationAction(ISD::CTTZ, VT, Expand); in AMDGPUTargetLowering() 409 setOperationAction(ISD::CTTZ, MVT::i64, Custom); in AMDGPUTargetLowering() 450 setOperationAction(ISD::CTTZ, VT, Expand); in AMDGPUTargetLowering() 1263 case ISD::CTTZ: in LowerOperation() 2322 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF; in isCttzOpc()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 490 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in NVPTXTargetLowering() 491 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in NVPTXTargetLowering() 492 setOperationAction(ISD::CTTZ, MVT::i64, Expand); in NVPTXTargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 128 setOperationAction(ISD::CTTZ, MVT::i32, Legal); in LanaiTargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 277 setOperationAction(ISD::CTTZ, VT, Custom); in addMVEVectorTypes() 933 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom); in ARMTargetLowering() 934 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom); in ARMTargetLowering() 935 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom); in ARMTargetLowering() 936 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); in ARMTargetLowering() 938 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom); in ARMTargetLowering() 939 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom); in ARMTargetLowering() 940 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom); in ARMTargetLowering() 941 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom); in ARMTargetLowering() 1158 setOperationAction(ISD::CTTZ, MVT::i32, Custom); in ARMTargetLowering() [all …]
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1576 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SparcTargetLowering() 1640 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SparcTargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 185 setOperationAction(ISD::CTTZ, VT, Expand); in AVRTargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 274 setOperationAction(ISD::CTTZ, MVT::i32, Custom); in RISCVTargetLowering() 280 setOperationAction(ISD::CTTZ, XLenVT, Expand); in RISCVTargetLowering() 4733 case ISD::CTTZ: in ReplaceNodeResults() 4743 N->getOpcode() == ISD::CTTZ || N->getOpcode() == ISD::CTTZ_ZERO_UNDEF; in ReplaceNodeResults()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 199 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV, in WebAssemblyTargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 428 setOperationAction(ISD::CTTZ , MVT::i32 , Legal); in PPCTargetLowering() 429 setOperationAction(ISD::CTTZ , MVT::i64 , Legal); in PPCTargetLowering() 431 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); in PPCTargetLowering() 432 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); in PPCTargetLowering() 760 setOperationAction(ISD::CTTZ, VT, Legal); in PPCTargetLowering() 762 setOperationAction(ISD::CTTZ, VT, Expand); in PPCTargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 420 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in MipsTargetLowering() 421 setOperationAction(ISD::CTTZ, MVT::i64, Expand); in MipsTargetLowering()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
H A D | VEISelLowering.cpp | 178 setOperationAction(ISD::CTTZ, IntVT, Expand); in initSPUActions()
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