Searched refs:MAX_NUM_DPM_LVL (Results 1 – 11 of 11) sorted by relevance
80 #define MAX_NUM_DPM_LVL 8 macro112 struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];
223 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { in dcn302_fpu_update_bw_bounding_box()312 if (num_states > MAX_NUM_DPM_LVL) { in dcn302_fpu_update_bw_bounding_box()
219 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { in dcn303_fpu_update_bw_bounding_box()307 if (num_states > MAX_NUM_DPM_LVL) { in dcn303_fpu_update_bw_bounding_box()
364 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { in build_synthetic_soc_states()707 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { in dcn321_update_bw_bounding_box_fpu()797 if (num_states > MAX_NUM_DPM_LVL) { in dcn321_update_bw_bounding_box_fpu()
635 if (i > MAX_NUM_DPM_LVL - 1) in dcn314_clk_mgr_helper_populate_bw_params()636 i = MAX_NUM_DPM_LVL - 1; in dcn314_clk_mgr_helper_populate_bw_params()
488 ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL); in dcn316_clk_mgr_helper_populate_bw_params()
567 ASSERT(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL); in vg_clk_mgr_helper_populate_bw_params()
646 ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL); in rn_clk_mgr_helper_populate_bw_params()
565 ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL); in dcn31_clk_mgr_helper_populate_bw_params()
2323 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { in dcn32_patch_dpm_table()2469 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { in build_synthetic_soc_states()2799 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { in dcn32_update_bw_bounding_box_fpu()2894 if (num_states > MAX_NUM_DPM_LVL) { in dcn32_update_bw_bounding_box_fpu()
2119 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { in dcn30_update_bw_bounding_box()