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Searched refs:PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK (Results 1 – 13 of 13) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h6462 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L macro
H A Dgfx_7_2_sh_mask.h6245 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000 macro
H A Dgfx_8_0_sh_mask.h7033 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000 macro
H A Dgfx_8_1_sh_mask.h7569 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h17349 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h18660 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h18550 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h20678 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h10795 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h22454 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h24864 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h24792 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h23061 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK … macro