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Searched refs:PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK (Results 1 – 8 of 8) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_sh_mask.h54948 #define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK … macro
H A Ddpcs_4_2_0_sh_mask.h163 #define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK … macro
H A Ddpcs_4_2_2_sh_mask.h150 #define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK … macro
H A Ddpcs_4_2_3_sh_mask.h167 #define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_2_sh_mask.h46347 #define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK … macro
H A Ddcn_3_1_5_sh_mask.h44624 #define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK … macro
H A Ddcn_3_1_4_sh_mask.h48652 #define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK … macro
H A Ddcn_3_1_6_sh_mask.h47970 #define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK … macro