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Searched refs:RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK (Results 1 – 13 of 13) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7128 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003fL macro
H A Dgfx_7_2_sh_mask.h7833 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f macro
H A Dgfx_8_0_sh_mask.h8735 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f macro
H A Dgfx_8_1_sh_mask.h9287 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h23043 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK … macro
H A Dgc_9_1_sh_mask.h24334 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK … macro
H A Dgc_9_2_1_sh_mask.h24385 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK … macro
H A Dgc_9_4_3_sh_mask.h26640 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK … macro
H A Dgc_9_4_2_sh_mask.h21838 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK … macro
H A Dgc_11_0_0_sh_mask.h34335 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK … macro
H A Dgc_10_1_0_sh_mask.h33494 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK … macro
H A Dgc_11_0_3_sh_mask.h37578 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK … macro
H A Dgc_10_3_0_sh_mask.h32515 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK … macro