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Searched refs:RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT (Results 1 – 10 of 10) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h9396 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h27304 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT … macro
H A Dgc_9_1_sh_mask.h28591 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h28932 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h30689 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h14505 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h38159 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h39855 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h36512 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h36572 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT … macro