UMIN (reference) in projects: openbsd - OpenGrok search results

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Searched refs:UMIN (Results 1 – 25 of 74) sorted by relevance

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/openbsd/gnu/llvm/llvm/lib/Target/X86/
H A D	X86TargetTransformInfo.cpp	4022 ISD = ISD::UMIN; in getIntrinsicInstrCost() 5203 {ISD::UMIN, MVT::v16i8, 1}, in getMinMaxCost() 5208 {ISD::UMIN, MVT::v4i32, 1}, in getMinMaxCost() 5209 {ISD::UMIN, MVT::v8i16, 1}, in getMinMaxCost() 5221 {ISD::UMIN, MVT::v8i32, 3}, in getMinMaxCost() 5223 {ISD::UMIN, MVT::v16i16, 3}, in getMinMaxCost() 5225 {ISD::UMIN, MVT::v32i8, 3}, in getMinMaxCost() 5230 {ISD::UMIN, MVT::v8i32, 1}, in getMinMaxCost() 5232 {ISD::UMIN, MVT::v16i16, 1}, in getMinMaxCost() 5356 {ISD::UMIN, MVT::v32i8, 8}, in getMinMaxReductionCost() [all …]
/openbsd/gnu/usr.bin/gcc/gcc/config/cris/
H A D	cris.h	`1767 {PLUS, MINUS, IOR, AND, UMIN}}, \ 1769 {PLUS, IOR, AND, UMIN}}, \ 1771 {PLUS, MINUS, UMIN}}, \ 1777 {PLUS, UMIN}}, \`
H A D	cris.c	`294 \|\| code == IOR \|\| code == AND \|\| code == UMIN)); 312 \|\| code == IOR \|\| code == AND \|\| code == UMIN)); 331 && (code == PLUS \|\| code == MINUS \|\| code == UMIN)); 380 (GET_MODE (x) == mode && (code == UMIN \|\| code == PLUS)); 541 case UMIN:`
H A D	cris.md	1926 "(GET_CODE (operands[6]) != UMIN \|\| GET_CODE (operands[7]) == ZERO_EXTEND) 1949 "(GET_CODE (operands[6]) != UMIN \|\| GET_CODE (operands[7]) == ZERO_EXTEND) 2005 "(GET_CODE (operands[5]) != UMIN \|\| GET_CODE (operands[6]) == ZERO_EXTEND) 2035 "(GET_CODE (operands[5]) != UMIN \|\| GET_CODE (operands[6]) == ZERO_EXTEND) 2094 "(GET_CODE (operands[7]) != UMIN \|\| GET_CODE (operands[6]) == ZERO_EXTEND) 2116 "(GET_CODE (operands[7]) != UMIN \|\| GET_CODE (operands[6]) == ZERO_EXTEND) 2168 "(GET_CODE (operands[6]) != UMIN \|\| GET_CODE (operands[5]) == ZERO_EXTEND) 2197 "(GET_CODE (operands[6]) != UMIN \|\| GET_CODE (operands[5]) == ZERO_EXTEND) 2245 "(GET_CODE (operands[3]) != UMIN \|\| GET_CODE (operands[4]) == ZERO_EXTEND) 2265 "(GET_CODE (operands[3]) != UMIN \|\| GET_CODE (operands[4]) == ZERO_EXTEND) [all …]
/openbsd/gnu/llvm/llvm/include/llvm/CodeGen/
H A D	ISDOpcodes.h	`662 UMIN, enumerator`
/openbsd/gnu/gcc/gcc/
H A D	sched-vis.c	`154 case UMIN: in print_exp()`
H A D	simplify-rtx.c	`2508 case UMIN: in simplify_binary_operation_1() 2959 case UMIN: in simplify_const_binary_operation() 3144 case UMIN: in simplify_const_binary_operation()`
H A D	rtlanal.c	`3592 case UMIN: case UMAX: case SMIN: case SMAX: in nonzero_bits1() 4101 case SMIN: case SMAX: case UMIN: case UMAX: in num_sign_bit_copies1()`
/openbsd/gnu/usr.bin/gcc/gcc/
H A D	simplify-rtx.c	`901 case UMIN: 1421 case UMIN: 1608 case UMIN:`
H A D	sched-vis.c	`285 case UMIN:`
H A D	combine.c	`3866 \|\| code == SMAX \|\| code == SMIN \|\| code == UMAX \|\| code == UMIN) 4951 return gen_binary (UMIN, mode, true_rtx, false_rtx); 7515 && (code == MULT \|\| code == AND \|\| code == UMIN) 7679 \|\| code == UMIN \|\| code == UMAX) 7681 int unsignedp = (code == UMIN \|\| code == UMAX); 8472 case UMIN: case UMAX: case SMIN: case SMAX: 8941 case SMIN: case SMAX: case UMIN: case UMAX:`
/openbsd/gnu/usr.bin/gcc/gcc/config/xtensa/
H A D	xtensa.h	`1421 case UMIN: \`
/openbsd/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A D	LegalizeVectorOps.cpp	`394 case ISD::UMIN: in LegalizeOp() 862 case ISD::UMIN: in Expand()`
H A D	SelectionDAGDumper.cpp	`283 case ISD::UMIN: return "umin"; in getOperationName()`
H A D	LegalizeIntegerTypes.cpp	`91 case ISD::UMIN: in PromoteIntegerResult() 891 return DAG.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax); in PromoteIntRes_ADDSUBSHLSAT() 991 return DAG.getNode(ISD::UMIN, dl, VT, V, in SaturateWidenedDIVFIX() 2503 case ISD::UMIN: in ExpandIntegerResult() 2868 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps() 2869 case ISD::UMIN: in getExpandedMinMaxOps() 2870 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()`
H A D	TargetLowering.cpp	2079 case ISD::UMIN: { in SimplifyDemandedBits() 8571 isOperationLegal(ISD::UMIN, VT)) { in expandABS() 8574 return DAG.getNode(ISD::UMIN, dl, VT, Op, in expandABS() 9373 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, Sub); in clampDynamicVectorIndex() 9381 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, in clampDynamicVectorIndex() 9498 if (Opcode == ISD::UMIN && isOperationLegal(ISD::SUB, VT) && in expandIntMINMAX() 9518 case ISD::UMIN: CC = ISD::SETULT; break; in expandIntMINMAX() 9548 if (Opcode == ISD::UADDSAT && isOperationLegal(ISD::UMIN, VT)) { in expandAddSubSat() 9550 SDValue Min = DAG.getNode(ISD::UMIN, dl, VT, LHS, InvRHS); in expandAddSubSat() 10367 TrailingBytes = DAG.getNode(ISD::UMIN, DL, PtrVT, TrailingBytes, VLBytes); in expandVectorSplice()
/openbsd/gnu/llvm/llvm/lib/Target/AArch64/
H A D	AArch64SchedA64FX.td	`2139 (instregex "^(AND\|EOR\|OR\|SADD\|SMAX\|SMIN\|UADD\|UMAX\|UMIN)V_VPZ_B")>; 2147 (instregex "^(AND\|EOR\|OR\|SADD\|SMAX\|SMIN\|UADD\|UMAX\|UMIN)V_VPZ_H")>; 2155 (instregex "^(AND\|EOR\|OR\|SADD\|SMAX\|SMIN\|UADD\|UMAX\|UMIN)V_VPZ_S")>; 2163 (instregex "^(AND\|EOR\|OR\|SADD\|SMAX\|SMIN\|UADD\|UMAX\|UMIN)V_VPZ_D")>;`
/openbsd/gnu/llvm/llvm/lib/Target/AMDGPU/
H A D	AMDGPUISelLowering.cpp	413 setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX}, MVT::i32, in AMDGPUTargetLowering() 2382 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const32); in LowerCTLZ_CTTZ() 2406 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, OprLo, OprHi); in LowerCTLZ_CTTZ() 2409 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const64); in LowerCTLZ_CTTZ() 2484 ShAmt = DAG.getNode(ISD::UMIN, SL, MVT::i32, ShAmt, MaxShAmt); in LowerINT_TO_FP32() 2506 SDValue Adjust = DAG.getNode(ISD::UMIN, SL, MVT::i32, in LowerINT_TO_FP32()
/openbsd/gnu/usr.bin/gcc/gcc/config/frv/
H A D	frv.h	`3314 { "minmax_operator", { SMIN, SMAX, UMIN, UMAX }}, \`
/openbsd/gnu/gcc/gcc/config/cris/
H A D	cris.md	`1654 "(GET_CODE (operands[6]) != UMIN \|\| GET_CODE (operands[7]) == ZERO_EXTEND) 1707 "(GET_CODE (operands[5]) != UMIN \|\| GET_CODE (operands[6]) == ZERO_EXTEND) 1765 "(GET_CODE (operands[7]) != UMIN \|\| GET_CODE (operands[6]) == ZERO_EXTEND) 1815 "(GET_CODE (operands[6]) != UMIN \|\| GET_CODE (operands[5]) == ZERO_EXTEND) 1863 "(GET_CODE (operands[3]) != UMIN \|\| GET_CODE (operands[4]) == ZERO_EXTEND) 1903 "(GET_CODE (operands[4]) != UMIN \|\| GET_CODE (operands[3]) == ZERO_EXTEND)`
/openbsd/gnu/usr.bin/gcc/gcc/config/arm/
H A D	arm.h	`2777 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \`
/openbsd/gnu/llvm/llvm/lib/Target/Mips/
H A D	MipsScheduleP5600.td	`636 (instregex "^ATOMIC_LOAD_(ADD\|SUB\|AND\|OR\|XOR\|NAND\|MIN\|MAX\|UMIN\|UMAX)"`
H A D	MipsSEISelLowering.cpp	`343 setOperationAction(ISD::UMIN, Ty, Legal); in addMSAIntType() 2031 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN() 2043 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()`
/openbsd/gnu/gcc/gcc/config/ia64/
H A D	vect.md	`271 if (ia64_expand_vecint_minmax (UMIN, <MODE>mode, operands))`
/openbsd/gnu/usr.bin/gcc/gcc/config/i386/
H A D	i386.h	`3329 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \`

12 3