Searched refs:has16BitInsts (Results 1 – 9 of 9) sorted by relevance
330 return (ElemWidth == 16 && ST->has16BitInsts()) ? 2 in getMaximumVF()539 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()554 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()565 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()581 if (ST->has16BitInsts() && SLT == MVT::f16 && !HasFP64FP16Denormals) in getArithmeticInstrCost()600 if (ST->has16BitInsts() && SLT == MVT::f16) in getArithmeticInstrCost()624 (SLT == MVT::f16 && ST->has16BitInsts())) { in getArithmeticInstrCost()629 if (SLT == MVT::f16 && ST->has16BitInsts()) { in getArithmeticInstrCost()704 if ((ST->has16BitInsts() && SLT == MVT::f16) || in getIntrinsicInstrCost()802 if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) in getVectorInstrCost()
148 bool has16BitInsts() const { in has16BitInsts() function
517 if (Size <= 16 && ST->has16BitInsts()) in replaceMulWithMul24()772 if (Ty->isHalfTy() && !ST->has16BitInsts()) in visitFDiv()1238 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBinaryOperator()1368 if (ST->has16BitInsts() && needsPromotionToI32(I.getOperand(0)->getType()) && in visitICmpInst()1378 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitSelectInst()1397 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBitreverseIntrinsicInst()
712 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()762 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()798 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()828 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()859 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()870 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()890 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()934 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()952 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()960 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()[all …]
339 if (Subtarget->has16BitInsts()) in AMDGPUTargetLowering()686 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts())); in isFPImmLegal()820 (Subtarget->has16BitInsts() && VT == MVT::f16); in isFAbsFree()863 if (DestSize== 16 && Subtarget->has16BitInsts()) in isTruncateFree()873 if (SrcSize == 16 && Subtarget->has16BitInsts()) in isZExtFree()2579 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerUINT_TO_FP()2619 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerSINT_TO_FP()3438 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16)) in performMulCombine()3598 if (LegalVT != MVT::i32 && (Subtarget->has16BitInsts() && in getFFBX_U32()4045 assert(!Subtarget->has16BitInsts() && "should only see if f16 is illegal"); in performFAbsCombine()
144 if (Subtarget->has16BitInsts()) { in SITargetLowering()414 if (Subtarget->has16BitInsts()) { in SITargetLowering()480 if (Subtarget->has16BitInsts()) { in SITargetLowering()707 if (Subtarget->has16BitInsts()) { in SITargetLowering()851 if (Subtarget->has16BitInsts()) { in getRegisterTypeForCallingConv()882 if (Size == 16 && Subtarget->has16BitInsts()) in getNumRegistersForCallingConv()907 if (Size == 16 && Subtarget->has16BitInsts()) { in getVectorTypeBreakdownForCallingConv()926 if (Size < 16 && Subtarget->has16BitInsts()) { in getVectorTypeBreakdownForCallingConv()1651 if (Subtarget->has16BitInsts() && VT == MVT::i16) { in isTypeDesirableForOp()9988 if (!Subtarget->has16BitInsts() || in performZeroExtendCombine()[all …]
1648 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
3738 return ST.has16BitInsts() && in isInlineConstant()3811 return ST.has16BitInsts() && in isInlineConstant()
1134 if (Size == 16 && !ST.has16BitInsts()) in getV_CMPOpcode()