| i40e_register.h (abf77452) | i40e_register.h (61ae650d) |
|---|---|
| 1/****************************************************************************** 2 | 1/****************************************************************************** 2 |
| 3 Copyright (c) 2013-2018, Intel Corporation | 3 Copyright (c) 2013-2014, Intel Corporation |
| 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 73 unchanged lines hidden (view full) --- 85#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT) 86#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 87#define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT) 88#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 89#define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT) 90#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 91#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT) 92#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 | 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 73 unchanged lines hidden (view full) --- 85#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT) 86#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 87#define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT) 88#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 89#define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT) 90#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 91#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT) 92#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 |
| 93#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT) | 93#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT) |
| 94#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */ 95#define I40E_PF_ARQT_ARQT_SHIFT 0 96#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT) 97#define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */ 98#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0 99#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT) 100#define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */ 101#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0 --- 6 unchanged lines hidden (view full) --- 108#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT) 109#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 110#define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT) 111#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 112#define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT) 113#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 114#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT) 115#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 | 94#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */ 95#define I40E_PF_ARQT_ARQT_SHIFT 0 96#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT) 97#define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */ 98#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0 99#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT) 100#define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */ 101#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0 --- 6 unchanged lines hidden (view full) --- 108#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT) 109#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 110#define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT) 111#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 112#define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT) 113#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 114#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT) 115#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 |
| 116#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT) | 116#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT) |
| 117#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */ 118#define I40E_PF_ATQT_ATQT_SHIFT 0 119#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT) 120#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 121#define I40E_VF_ARQBAH_MAX_INDEX 127 122#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0 123#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT) 124#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ --- 10 unchanged lines hidden (view full) --- 135#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT) 136#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28 137#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT) 138#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29 139#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT) 140#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30 141#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT) 142#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31 | 117#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */ 118#define I40E_PF_ATQT_ATQT_SHIFT 0 119#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT) 120#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 121#define I40E_VF_ARQBAH_MAX_INDEX 127 122#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0 123#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT) 124#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ --- 10 unchanged lines hidden (view full) --- 135#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT) 136#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28 137#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT) 138#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29 139#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT) 140#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30 141#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT) 142#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31 |
| 143#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN_ARQENABLE_SHIFT) | 143#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT) |
| 144#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 145#define I40E_VF_ARQT_MAX_INDEX 127 146#define I40E_VF_ARQT_ARQT_SHIFT 0 147#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT) 148#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 149#define I40E_VF_ATQBAH_MAX_INDEX 127 150#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0 151#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT) --- 11 unchanged lines hidden (view full) --- 163#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT) 164#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28 165#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT) 166#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29 167#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT) 168#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30 169#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT) 170#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31 | 144#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 145#define I40E_VF_ARQT_MAX_INDEX 127 146#define I40E_VF_ARQT_ARQT_SHIFT 0 147#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT) 148#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 149#define I40E_VF_ATQBAH_MAX_INDEX 127 150#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0 151#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT) --- 11 unchanged lines hidden (view full) --- 163#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT) 164#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28 165#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT) 166#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29 167#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT) 168#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30 169#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT) 170#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31 |
| 171#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN_ATQENABLE_SHIFT) | 171#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT) |
| 172#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 173#define I40E_VF_ATQT_MAX_INDEX 127 174#define I40E_VF_ATQT_ATQT_SHIFT 0 175#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT) 176#define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */ 177#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0 178#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT) 179#define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */ --- 47 unchanged lines hidden (view full) --- 227#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4 228#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT) 229#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8 230#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT) 231#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16 232#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT) 233#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24 234#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT) | 172#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 173#define I40E_VF_ATQT_MAX_INDEX 127 174#define I40E_VF_ATQT_ATQT_SHIFT 0 175#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT) 176#define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */ 177#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0 178#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT) 179#define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */ --- 47 unchanged lines hidden (view full) --- 227#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4 228#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT) 229#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8 230#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT) 231#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16 232#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT) 233#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24 234#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT) |
| 235#define I40E_PRT_SWR_PM_THR 0x0026CD00 /* Reset: CORER */ 236#define I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT 0 237#define I40E_PRT_SWR_PM_THR_THRESHOLD_MASK I40E_MASK(0xFF, I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT) | |
| 238#define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */ 239#define I40E_GLDCB_GENC_PCIRTT_SHIFT 0 240#define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT) 241#define I40E_GLDCB_RUPTI 0x00122618 /* Reset: CORER */ 242#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0 243#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT) 244#define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */ 245#define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3 --- 43 unchanged lines hidden (view full) --- 289#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT) 290#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 291#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7 292#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0 293#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) 294#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30 295#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) 296#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31 | 235#define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */ 236#define I40E_GLDCB_GENC_PCIRTT_SHIFT 0 237#define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT) 238#define I40E_GLDCB_RUPTI 0x00122618 /* Reset: CORER */ 239#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0 240#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT) 241#define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */ 242#define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3 --- 43 unchanged lines hidden (view full) --- 286#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT) 287#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 288#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7 289#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0 290#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) 291#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30 292#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) 293#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31 |
| 297#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1u, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) | 294#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) |
| 298#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */ 299#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0 300#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT) 301#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8 302#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT) 303#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16 304#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) 305#define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */ --- 11 unchanged lines hidden (view full) --- 317#define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12 318#define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT) 319#define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15 320#define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT) 321#define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18 322#define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT) 323#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21 324#define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT) | 295#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */ 296#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0 297#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT) 298#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8 299#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT) 300#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16 301#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) 302#define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */ --- 11 unchanged lines hidden (view full) --- 314#define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12 315#define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT) 316#define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15 317#define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT) 318#define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18 319#define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT) 320#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21 321#define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT) |
| 325#define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 326#define I40E_PRTDCB_RUPTQ_MAX_INDEX 7 327#define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0 328#define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT) | |
| 329#define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */ 330#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0 331#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) 332#define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 333#define I40E_PRTDCB_TCMSTC_MAX_INDEX 7 334#define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0 335#define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT) 336#define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */ --- 56 unchanged lines hidden (view full) --- 393#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT) 394#define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ 395#define I40E_GL_FWSTS_FWS0B_SHIFT 0 396#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT) 397#define I40E_GL_FWSTS_FWRI_SHIFT 9 398#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT) 399#define I40E_GL_FWSTS_FWS1B_SHIFT 16 400#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT) | 322#define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */ 323#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0 324#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) 325#define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 326#define I40E_PRTDCB_TCMSTC_MAX_INDEX 7 327#define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0 328#define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT) 329#define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */ --- 56 unchanged lines hidden (view full) --- 386#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT) 387#define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ 388#define I40E_GL_FWSTS_FWS0B_SHIFT 0 389#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT) 390#define I40E_GL_FWSTS_FWRI_SHIFT 9 391#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT) 392#define I40E_GL_FWSTS_FWS1B_SHIFT 16 393#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT) |
| 401#define I40E_GL_FWSTS_FWS1B_EMPR_0 I40E_MASK(0x20, I40E_GL_FWSTS_FWS1B_SHIFT) 402#define I40E_GL_FWSTS_FWS1B_EMPR_10 I40E_MASK(0x2A, I40E_GL_FWSTS_FWS1B_SHIFT) 403#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK \ 404 I40E_MASK(0x30, I40E_GL_FWSTS_FWS1B_SHIFT) 405#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK \ 406 I40E_MASK(0x31, I40E_GL_FWSTS_FWS1B_SHIFT) 407#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK \ 408 I40E_MASK(0x32, I40E_GL_FWSTS_FWS1B_SHIFT) 409#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK \ 410 I40E_MASK(0x33, I40E_GL_FWSTS_FWS1B_SHIFT) 411#define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK \ 412 I40E_MASK(0xB, I40E_GL_FWSTS_FWS1B_SHIFT) 413#define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK \ 414 I40E_MASK(0xC, I40E_GL_FWSTS_FWS1B_SHIFT) | |
| 415#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */ 416#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0 417#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT) 418#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4 419#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT) 420#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8 421#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT) 422#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12 --- 23 unchanged lines hidden (view full) --- 446#define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12 447#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 448#define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17 449#define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT) 450#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19 451#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 452#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20 453#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) | 394#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */ 395#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0 396#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT) 397#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4 398#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT) 399#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8 400#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT) 401#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12 --- 23 unchanged lines hidden (view full) --- 425#define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12 426#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 427#define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17 428#define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT) 429#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19 430#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 431#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20 432#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) |
| 454#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT 26 455#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK I40E_MASK(0xF, I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT) | |
| 456#define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */ 457#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0 458#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT) 459#define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5 460#define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 461#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6 462#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 463#define I40E_GLGEN_GPIO_STAT 0x0008817C /* Reset: POR */ --- 47 unchanged lines hidden (view full) --- 511#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT) 512#define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 513#define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3 514#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0 515#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK I40E_MASK(0x1FFFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT) 516#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17 517#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT) 518#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18 | 433#define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */ 434#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0 435#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT) 436#define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5 437#define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 438#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6 439#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 440#define I40E_GLGEN_GPIO_STAT 0x0008817C /* Reset: POR */ --- 47 unchanged lines hidden (view full) --- 488#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT) 489#define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 490#define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3 491#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0 492#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK I40E_MASK(0x1FFFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT) 493#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17 494#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT) 495#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18 |
| 519#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x7FF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT) 520#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT 29 521#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK I40E_MASK(0x7, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT) | 496#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x3FFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT) |
| 522#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 523#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3 524#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0 525#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT) 526#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1 527#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT) 528#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5 529#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT) --- 17 unchanged lines hidden (view full) --- 547#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT) 548#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 549#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT) 550#define I40E_GLGEN_MSCA_STCODE_SHIFT 28 551#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT) 552#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 553#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT) 554#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 | 497#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 498#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3 499#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0 500#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT) 501#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1 502#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT) 503#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5 504#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT) --- 17 unchanged lines hidden (view full) --- 522#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT) 523#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 524#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT) 525#define I40E_GLGEN_MSCA_STCODE_SHIFT 28 526#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT) 527#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 528#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT) 529#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 |
| 555#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) | 530#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) |
| 556#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 557#define I40E_GLGEN_MSRWD_MAX_INDEX 3 558#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 559#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT) 560#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 561#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 562#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ 563#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 --- 13 unchanged lines hidden (view full) --- 577#define I40E_GLGEN_RSTAT_EMPRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_EMPRCNT_SHIFT) 578#define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10 579#define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT) 580#define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */ 581#define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0 582#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) 583#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8 584#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT) | 531#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 532#define I40E_GLGEN_MSRWD_MAX_INDEX 3 533#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 534#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT) 535#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 536#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 537#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ 538#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 --- 13 unchanged lines hidden (view full) --- 552#define I40E_GLGEN_RSTAT_EMPRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_EMPRCNT_SHIFT) 553#define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10 554#define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT) 555#define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */ 556#define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0 557#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) 558#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8 559#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT) |
| 560#define I40E_GLGEN_RSTENA_EMP 0x000B818C /* Reset: POR */ 561#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0 562#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT) |
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| 585#define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */ 586#define I40E_GLGEN_RTRIG_CORER_SHIFT 0 587#define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT) 588#define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1 589#define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT) 590#define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2 591#define I40E_GLGEN_RTRIG_EMPFWR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_EMPFWR_SHIFT) 592#define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */ --- 301 unchanged lines hidden (view full) --- 894#define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16 895#define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT) 896#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 897#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT) 898#define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30 899#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT) 900#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31 901#define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT) | 563#define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */ 564#define I40E_GLGEN_RTRIG_CORER_SHIFT 0 565#define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT) 566#define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1 567#define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT) 568#define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2 569#define I40E_GLGEN_RTRIG_EMPFWR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_EMPFWR_SHIFT) 570#define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */ --- 301 unchanged lines hidden (view full) --- 872#define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16 873#define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT) 874#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 875#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT) 876#define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30 877#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT) 878#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31 879#define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT) |
| 902#define I40E_GLINT_CTL 0x0003F800 /* Reset: CORER */ 903#define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT 0 904#define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT) 905#define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT 1 906#define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT) 907#define I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT 2 908#define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT) | |
| 909#define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */ 910#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0 911#define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT) 912#define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1 913#define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT) 914#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 915#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 916#define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3 --- 182 unchanged lines hidden (view full) --- 1099#define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6 1100#define I40E_PFINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATE0_INTRL_ENA_SHIFT) 1101#define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 1102#define I40E_PFINT_RATEN_MAX_INDEX 511 1103#define I40E_PFINT_RATEN_INTERVAL_SHIFT 0 1104#define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT) 1105#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6 1106#define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT) | 880#define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */ 881#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0 882#define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT) 883#define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1 884#define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT) 885#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 886#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 887#define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3 --- 182 unchanged lines hidden (view full) --- 1070#define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6 1071#define I40E_PFINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATE0_INTRL_ENA_SHIFT) 1072#define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 1073#define I40E_PFINT_RATEN_MAX_INDEX 511 1074#define I40E_PFINT_RATEN_INTERVAL_SHIFT 0 1075#define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT) 1076#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6 1077#define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT) |
| 1107#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */ | 1078#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: PFR */ |
| 1108#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 1109#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 1110#define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1111#define I40E_QINT_RQCTL_MAX_INDEX 1535 1112#define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0 1113#define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT) 1114#define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11 1115#define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT) --- 88 unchanged lines hidden (view full) --- 1204#define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */ 1205#define I40E_VFINT_ITR0_MAX_INDEX 2 1206#define I40E_VFINT_ITR0_INTERVAL_SHIFT 0 1207#define I40E_VFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR0_INTERVAL_SHIFT) 1208#define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */ 1209#define I40E_VFINT_ITRN_MAX_INDEX 2 1210#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0 1211#define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT) | 1079#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 1080#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 1081#define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1082#define I40E_QINT_RQCTL_MAX_INDEX 1535 1083#define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0 1084#define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT) 1085#define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11 1086#define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT) --- 88 unchanged lines hidden (view full) --- 1175#define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */ 1176#define I40E_VFINT_ITR0_MAX_INDEX 2 1177#define I40E_VFINT_ITR0_INTERVAL_SHIFT 0 1178#define I40E_VFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR0_INTERVAL_SHIFT) 1179#define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */ 1180#define I40E_VFINT_ITRN_MAX_INDEX 2 1181#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0 1182#define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT) |
| 1212#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ | 1183#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ |
| 1213#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127 1214#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 1215#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 1216#define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 1217#define I40E_VPINT_AEQCTL_MAX_INDEX 127 1218#define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0 1219#define I40E_VPINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT) 1220#define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11 --- 65 unchanged lines hidden (view full) --- 1286#define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11 1287#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 1288#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 1289#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16 1290#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT) 1291#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 1292#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 1293#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 | 1184#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127 1185#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 1186#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 1187#define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 1188#define I40E_VPINT_AEQCTL_MAX_INDEX 127 1189#define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0 1190#define I40E_VPINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT) 1191#define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11 --- 65 unchanged lines hidden (view full) --- 1257#define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11 1258#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 1259#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 1260#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16 1261#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT) 1262#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 1263#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 1264#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 |
| 1294#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) | 1265#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) |
| 1295#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */ 1296#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 1297#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) 1298#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 1299#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT) 1300#define I40E_PFLAN_QALLOC_VALID_SHIFT 31 | 1266#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */ 1267#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 1268#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) 1269#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 1270#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT) 1271#define I40E_PFLAN_QALLOC_VALID_SHIFT 31 |
| 1301#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT) | 1272#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT) |
| 1302#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 1303#define I40E_QRX_ENA_MAX_INDEX 1535 1304#define I40E_QRX_ENA_QENA_REQ_SHIFT 0 1305#define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT) 1306#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1 1307#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT) 1308#define I40E_QRX_ENA_QENA_STAT_SHIFT 2 1309#define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT) --- 392 unchanged lines hidden (view full) --- 1702#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT) 1703#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 1704#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT) 1705#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29 1706#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT) 1707#define I40E_GLNVM_SRCTL_START_SHIFT 30 1708#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT) 1709#define I40E_GLNVM_SRCTL_DONE_SHIFT 31 | 1273#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 1274#define I40E_QRX_ENA_MAX_INDEX 1535 1275#define I40E_QRX_ENA_QENA_REQ_SHIFT 0 1276#define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT) 1277#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1 1278#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT) 1279#define I40E_QRX_ENA_QENA_STAT_SHIFT 2 1280#define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT) --- 392 unchanged lines hidden (view full) --- 1673#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT) 1674#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 1675#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT) 1676#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29 1677#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT) 1678#define I40E_GLNVM_SRCTL_START_SHIFT 30 1679#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT) 1680#define I40E_GLNVM_SRCTL_DONE_SHIFT 31 |
| 1710#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT) | 1681#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT) |
| 1711#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */ 1712#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0 1713#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT) 1714#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 1715#define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT) 1716#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 1717#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0 1718#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT) --- 117 unchanged lines hidden (view full) --- 1836#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0 1837#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT) 1838#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16 1839#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT) 1840#define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */ 1841#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3 1842#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0 1843#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT) | 1682#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */ 1683#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0 1684#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT) 1685#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 1686#define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT) 1687#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 1688#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0 1689#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT) --- 117 unchanged lines hidden (view full) --- 1807#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0 1808#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT) 1809#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16 1810#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT) 1811#define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */ 1812#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3 1813#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0 1814#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT) |
| 1815#define I40E_GLPCI_LATCT 0x0009C4B4 /* Reset: PCIR */ 1816#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0 1817#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT) |
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| 1844#define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */ 1845#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0 1846#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT) 1847#define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1 1848#define I40E_GLPCI_LBARCTRL_BAR32_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_BAR32_SHIFT) 1849#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3 1850#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT) 1851#define I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT 4 --- 80 unchanged lines hidden (view full) --- 1932#define I40E_GLPCI_VENDORID 0x000BE518 /* Reset: PCIR */ 1933#define I40E_GLPCI_VENDORID_VENDORID_SHIFT 0 1934#define I40E_GLPCI_VENDORID_VENDORID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_VENDORID_VENDORID_SHIFT) 1935#define I40E_GLPCI_VFSUP 0x000BE4B8 /* Reset: PCIR */ 1936#define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0 1937#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT) 1938#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1 1939#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT) | 1818#define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */ 1819#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0 1820#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT) 1821#define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1 1822#define I40E_GLPCI_LBARCTRL_BAR32_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_BAR32_SHIFT) 1823#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3 1824#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT) 1825#define I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT 4 --- 80 unchanged lines hidden (view full) --- 1906#define I40E_GLPCI_VENDORID 0x000BE518 /* Reset: PCIR */ 1907#define I40E_GLPCI_VENDORID_VENDORID_SHIFT 0 1908#define I40E_GLPCI_VENDORID_VENDORID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_VENDORID_VENDORID_SHIFT) 1909#define I40E_GLPCI_VFSUP 0x000BE4B8 /* Reset: PCIR */ 1910#define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0 1911#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT) 1912#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1 1913#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT) |
| 1940#define I40E_GLTPH_CTRL 0x000BE480 /* Reset: PCIR */ 1941#define I40E_GLTPH_CTRL_DESC_PH_SHIFT 9 1942#define I40E_GLTPH_CTRL_DESC_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DESC_PH_SHIFT) 1943#define I40E_GLTPH_CTRL_DATA_PH_SHIFT 11 1944#define I40E_GLTPH_CTRL_DATA_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DATA_PH_SHIFT) | |
| 1945#define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */ 1946#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0 1947#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT) 1948#define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3 1949#define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK I40E_MASK(0x1F, I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT) 1950#define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8 1951#define I40E_PF_FUNC_RID_BUS_NUMBER_MASK I40E_MASK(0xFF, I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT) 1952#define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */ --- 113 unchanged lines hidden (view full) --- 2066#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31 2067#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT) 2068#define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */ 2069#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0 2070#define I40E_PRTPM_RLPIC_ERLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT) 2071#define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */ 2072#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0 2073#define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT) | 1914#define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */ 1915#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0 1916#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT) 1917#define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3 1918#define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK I40E_MASK(0x1F, I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT) 1919#define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8 1920#define I40E_PF_FUNC_RID_BUS_NUMBER_MASK I40E_MASK(0xFF, I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT) 1921#define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */ --- 113 unchanged lines hidden (view full) --- 2035#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31 2036#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT) 2037#define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */ 2038#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0 2039#define I40E_PRTPM_RLPIC_ERLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT) 2040#define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */ 2041#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0 2042#define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT) |
| 2074#define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */ 2075#define I40E_GL_PRS_FVBM_MAX_INDEX 3 2076#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT 0 2077#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_MASK I40E_MASK(0x7F, I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT) 2078#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT 8 2079#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_MASK I40E_MASK(0x3F, I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT) 2080#define I40E_GL_PRS_FVBM_MSK_ENA_SHIFT 31 2081#define I40E_GL_PRS_FVBM_MSK_ENA_MASK I40E_MASK(0x1, I40E_GL_PRS_FVBM_MSK_ENA_SHIFT) | |
| 2082#define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */ 2083#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0 2084#define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT) 2085#define I40E_GLRPB_GHW 0x000AC830 /* Reset: CORER */ 2086#define I40E_GLRPB_GHW_GHW_SHIFT 0 2087#define I40E_GLRPB_GHW_GHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT) 2088#define I40E_GLRPB_GLW 0x000AC834 /* Reset: CORER */ 2089#define I40E_GLRPB_GLW_GLW_SHIFT 0 --- 155 unchanged lines hidden (view full) --- 2245#define I40E_PFQF_HLUT_LUT3_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT) 2246#define I40E_PRTQF_CTL_0 0x00256E60 /* Reset: CORER */ 2247#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0 2248#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK I40E_MASK(0x1, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT) 2249#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ /* Reset: CORER */ 2250#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63 2251#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0 2252#define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) | 2043#define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */ 2044#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0 2045#define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT) 2046#define I40E_GLRPB_GHW 0x000AC830 /* Reset: CORER */ 2047#define I40E_GLRPB_GHW_GHW_SHIFT 0 2048#define I40E_GLRPB_GHW_GHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT) 2049#define I40E_GLRPB_GLW 0x000AC834 /* Reset: CORER */ 2050#define I40E_GLRPB_GLW_GLW_SHIFT 0 --- 155 unchanged lines hidden (view full) --- 2206#define I40E_PFQF_HLUT_LUT3_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT) 2207#define I40E_PRTQF_CTL_0 0x00256E60 /* Reset: CORER */ 2208#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0 2209#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK I40E_MASK(0x1, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT) 2210#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ /* Reset: CORER */ 2211#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63 2212#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0 2213#define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) |
| 2253#define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 2254#define I40E_PRTQF_FD_INSET_MAX_INDEX 63 2255#define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 2256#define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT) 2257#define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 2258#define I40E_PRTQF_FD_INSET_MAX_INDEX 63 2259#define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 2260#define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT) | |
| 2261#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 2262#define I40E_PRTQF_FD_MSK_MAX_INDEX 63 2263#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0 2264#define I40E_PRTQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT) 2265#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16 2266#define I40E_PRTQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT) 2267#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */ 2268#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8 --- 156 unchanged lines hidden (view full) --- 2425#define I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT 0 2426#define I40E_GL_RXERR1_L_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT) 2427#define I40E_GL_RXERR2_L(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2428#define I40E_GL_RXERR2_L_MAX_INDEX 143 2429#define I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT 0 2430#define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT) 2431#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2432#define I40E_GLPRT_BPRCH_MAX_INDEX 3 | 2214#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 2215#define I40E_PRTQF_FD_MSK_MAX_INDEX 63 2216#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0 2217#define I40E_PRTQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT) 2218#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16 2219#define I40E_PRTQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT) 2220#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */ 2221#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8 --- 156 unchanged lines hidden (view full) --- 2378#define I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT 0 2379#define I40E_GL_RXERR1_L_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT) 2380#define I40E_GL_RXERR2_L(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2381#define I40E_GL_RXERR2_L_MAX_INDEX 143 2382#define I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT 0 2383#define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT) 2384#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2385#define I40E_GLPRT_BPRCH_MAX_INDEX 3 |
| 2433#define I40E_GLPRT_BPRCH_BPRCH_SHIFT 0 2434#define I40E_GLPRT_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_BPRCH_SHIFT) | 2386#define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0 2387#define I40E_GLPRT_BPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_UPRCH_SHIFT) |
| 2435#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2436#define I40E_GLPRT_BPRCL_MAX_INDEX 3 | 2388#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2389#define I40E_GLPRT_BPRCL_MAX_INDEX 3 |
| 2437#define I40E_GLPRT_BPRCL_BPRCL_SHIFT 0 2438#define I40E_GLPRT_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_BPRCL_SHIFT) | 2390#define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0 2391#define I40E_GLPRT_BPRCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_UPRCH_SHIFT) |
| 2439#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2440#define I40E_GLPRT_BPTCH_MAX_INDEX 3 | 2392#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2393#define I40E_GLPRT_BPTCH_MAX_INDEX 3 |
| 2441#define I40E_GLPRT_BPTCH_BPTCH_SHIFT 0 2442#define I40E_GLPRT_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_BPTCH_SHIFT) | 2394#define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0 2395#define I40E_GLPRT_BPTCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_UPRCH_SHIFT) |
| 2443#define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2444#define I40E_GLPRT_BPTCL_MAX_INDEX 3 | 2396#define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2397#define I40E_GLPRT_BPTCL_MAX_INDEX 3 |
| 2445#define I40E_GLPRT_BPTCL_BPTCL_SHIFT 0 2446#define I40E_GLPRT_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_BPTCL_SHIFT) | 2398#define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0 2399#define I40E_GLPRT_BPTCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_UPRCH_SHIFT) |
| 2447#define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2448#define I40E_GLPRT_CRCERRS_MAX_INDEX 3 2449#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0 2450#define I40E_GLPRT_CRCERRS_CRCERRS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_CRCERRS_CRCERRS_SHIFT) 2451#define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2452#define I40E_GLPRT_GORCH_MAX_INDEX 3 2453#define I40E_GLPRT_GORCH_GORCH_SHIFT 0 2454#define I40E_GLPRT_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GORCH_GORCH_SHIFT) --- 216 unchanged lines hidden (view full) --- 2671#define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2672#define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3 2673#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0 2674#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT) 2675#define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2676#define I40E_GLPRT_TDOLD_MAX_INDEX 3 2677#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0 2678#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT) | 2400#define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2401#define I40E_GLPRT_CRCERRS_MAX_INDEX 3 2402#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0 2403#define I40E_GLPRT_CRCERRS_CRCERRS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_CRCERRS_CRCERRS_SHIFT) 2404#define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2405#define I40E_GLPRT_GORCH_MAX_INDEX 3 2406#define I40E_GLPRT_GORCH_GORCH_SHIFT 0 2407#define I40E_GLPRT_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GORCH_GORCH_SHIFT) --- 216 unchanged lines hidden (view full) --- 2624#define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2625#define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3 2626#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0 2627#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT) 2628#define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2629#define I40E_GLPRT_TDOLD_MAX_INDEX 3 2630#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0 2631#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT) |
| 2632#define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2633#define I40E_GLPRT_TDPC_MAX_INDEX 3 2634#define I40E_GLPRT_TDPC_TDPC_SHIFT 0 2635#define I40E_GLPRT_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDPC_TDPC_SHIFT) |
|
| 2679#define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2680#define I40E_GLPRT_UPRCH_MAX_INDEX 3 2681#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0 2682#define I40E_GLPRT_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPRCH_UPRCH_SHIFT) 2683#define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2684#define I40E_GLPRT_UPRCL_MAX_INDEX 3 2685#define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0 2686#define I40E_GLPRT_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPRCL_UPRCL_SHIFT) --- 128 unchanged lines hidden (view full) --- 2815#define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2816#define I40E_GLV_RDPC_MAX_INDEX 383 2817#define I40E_GLV_RDPC_RDPC_SHIFT 0 2818#define I40E_GLV_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT) 2819#define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2820#define I40E_GLV_RUPP_MAX_INDEX 383 2821#define I40E_GLV_RUPP_RUPP_SHIFT 0 2822#define I40E_GLV_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT) | 2636#define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2637#define I40E_GLPRT_UPRCH_MAX_INDEX 3 2638#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0 2639#define I40E_GLPRT_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPRCH_UPRCH_SHIFT) 2640#define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2641#define I40E_GLPRT_UPRCL_MAX_INDEX 3 2642#define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0 2643#define I40E_GLPRT_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPRCL_UPRCL_SHIFT) --- 128 unchanged lines hidden (view full) --- 2772#define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2773#define I40E_GLV_RDPC_MAX_INDEX 383 2774#define I40E_GLV_RDPC_RDPC_SHIFT 0 2775#define I40E_GLV_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT) 2776#define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2777#define I40E_GLV_RUPP_MAX_INDEX 383 2778#define I40E_GLV_RUPP_RUPP_SHIFT 0 2779#define I40E_GLV_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT) |
| 2823#define I40E_GLV_TEPC(_i) (0x00344000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ | 2780#define I40E_GLV_TEPC(_VSI) (0x00344000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */ |
| 2824#define I40E_GLV_TEPC_MAX_INDEX 383 2825#define I40E_GLV_TEPC_TEPC_SHIFT 0 2826#define I40E_GLV_TEPC_TEPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT) 2827#define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2828#define I40E_GLV_UPRCH_MAX_INDEX 383 2829#define I40E_GLV_UPRCH_UPRCH_SHIFT 0 2830#define I40E_GLV_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT) 2831#define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ --- 205 unchanged lines hidden (view full) --- 3037#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0 3038#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT) 3039#define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */ 3040#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0 3041#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT) 3042#define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */ 3043#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0 3044#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT) | 2781#define I40E_GLV_TEPC_MAX_INDEX 383 2782#define I40E_GLV_TEPC_TEPC_SHIFT 0 2783#define I40E_GLV_TEPC_TEPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT) 2784#define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2785#define I40E_GLV_UPRCH_MAX_INDEX 383 2786#define I40E_GLV_UPRCH_UPRCH_SHIFT 0 2787#define I40E_GLV_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT) 2788#define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ --- 205 unchanged lines hidden (view full) --- 2994#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0 2995#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT) 2996#define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */ 2997#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0 2998#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT) 2999#define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */ 3000#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0 3001#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT) |
| 3002#define I40E_GLSCD_QUANTA 0x000B2080 /* Reset: CORER */ 3003#define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0 3004#define I40E_GLSCD_QUANTA_TSCDQUANTA_MASK I40E_MASK(0x7, I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT) |
|
| 3045#define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */ 3046#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 3047#define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT) 3048#define I40E_GL_MDET_RX_EVENT_SHIFT 8 3049#define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT) 3050#define I40E_GL_MDET_RX_QUEUE_SHIFT 17 3051#define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT) 3052#define I40E_GL_MDET_RX_VALID_SHIFT 31 --- 16 unchanged lines hidden (view full) --- 3069#define I40E_PF_MDET_TX_VALID_SHIFT 0 3070#define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT) 3071#define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */ 3072#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 3073#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) 3074#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 3075#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT) 3076#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 | 3005#define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */ 3006#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 3007#define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT) 3008#define I40E_GL_MDET_RX_EVENT_SHIFT 8 3009#define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT) 3010#define I40E_GL_MDET_RX_QUEUE_SHIFT 17 3011#define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT) 3012#define I40E_GL_MDET_RX_VALID_SHIFT 31 --- 16 unchanged lines hidden (view full) --- 3029#define I40E_PF_MDET_TX_VALID_SHIFT 0 3030#define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT) 3031#define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */ 3032#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 3033#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) 3034#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 3035#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT) 3036#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 |
| 3077#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT) | 3037#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT) |
| 3078#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3079#define I40E_VP_MDET_RX_MAX_INDEX 127 3080#define I40E_VP_MDET_RX_VALID_SHIFT 0 3081#define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT) 3082#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3083#define I40E_VP_MDET_TX_MAX_INDEX 127 3084#define I40E_VP_MDET_TX_VALID_SHIFT 0 3085#define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT) --- 119 unchanged lines hidden (view full) --- 3205#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT) 3206#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 3207#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT) 3208#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 3209#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT) 3210#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 3211#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT) 3212#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 | 3038#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3039#define I40E_VP_MDET_RX_MAX_INDEX 127 3040#define I40E_VP_MDET_RX_VALID_SHIFT 0 3041#define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT) 3042#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3043#define I40E_VP_MDET_TX_MAX_INDEX 127 3044#define I40E_VP_MDET_TX_VALID_SHIFT 0 3045#define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT) --- 119 unchanged lines hidden (view full) --- 3165#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT) 3166#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 3167#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT) 3168#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 3169#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT) 3170#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 3171#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT) 3172#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 |
| 3213#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN1_ARQENABLE_SHIFT) | 3173#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT) |
| 3214#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ 3215#define I40E_VF_ARQT1_ARQT_SHIFT 0 3216#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT) 3217#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ 3218#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 3219#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT) 3220#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ 3221#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 --- 6 unchanged lines hidden (view full) --- 3228#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT) 3229#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 3230#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT) 3231#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 3232#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT) 3233#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 3234#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT) 3235#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 | 3174#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ 3175#define I40E_VF_ARQT1_ARQT_SHIFT 0 3176#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT) 3177#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ 3178#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 3179#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT) 3180#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ 3181#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 --- 6 unchanged lines hidden (view full) --- 3188#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT) 3189#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 3190#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT) 3191#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 3192#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT) 3193#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 3194#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT) 3195#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 |
| 3236#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN1_ATQENABLE_SHIFT) | 3196#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT) |
| 3237#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ 3238#define I40E_VF_ATQT1_ATQT_SHIFT 0 3239#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT) 3240#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ 3241#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 3242#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) 3243#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ 3244#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 --- 57 unchanged lines hidden (view full) --- 3302#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ 3303#define I40E_VFINT_ITR01_MAX_INDEX 2 3304#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0 3305#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT) 3306#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ 3307#define I40E_VFINT_ITRN1_MAX_INDEX 2 3308#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 3309#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT) | 3197#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ 3198#define I40E_VF_ATQT1_ATQT_SHIFT 0 3199#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT) 3200#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ 3201#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 3202#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) 3203#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ 3204#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 --- 57 unchanged lines hidden (view full) --- 3262#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ 3263#define I40E_VFINT_ITR01_MAX_INDEX 2 3264#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0 3265#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT) 3266#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ 3267#define I40E_VFINT_ITRN1_MAX_INDEX 2 3268#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 3269#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT) |
| 3310#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */ | 3270#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: VFR */ |
| 3311#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 3312#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) 3313#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3314#define I40E_QRX_TAIL1_MAX_INDEX 15 3315#define I40E_QRX_TAIL1_TAIL_SHIFT 0 3316#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT) 3317#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ 3318#define I40E_QTX_TAIL1_MAX_INDEX 15 --- 91 unchanged lines hidden (view full) --- 3410#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 3411#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT) 3412#define I40E_VFQF_HREGION_REGION_6_SHIFT 25 3413#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT) 3414#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 3415#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) 3416#define I40E_VFQF_HREGION_REGION_7_SHIFT 29 3417#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT) | 3271#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 3272#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) 3273#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3274#define I40E_QRX_TAIL1_MAX_INDEX 15 3275#define I40E_QRX_TAIL1_TAIL_SHIFT 0 3276#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT) 3277#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ 3278#define I40E_QTX_TAIL1_MAX_INDEX 15 --- 91 unchanged lines hidden (view full) --- 3370#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 3371#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT) 3372#define I40E_VFQF_HREGION_REGION_6_SHIFT 25 3373#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT) 3374#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 3375#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) 3376#define I40E_VFQF_HREGION_REGION_7_SHIFT 29 3377#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT) |
| 3418 3419#define I40E_MNGSB_FDCRC 0x000B7050 /* Reset: POR */ 3420#define I40E_MNGSB_FDCRC_CRC_RES_SHIFT 0 3421#define I40E_MNGSB_FDCRC_CRC_RES_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCRC_CRC_RES_SHIFT) 3422#define I40E_MNGSB_FDCS 0x000B7040 /* Reset: POR */ 3423#define I40E_MNGSB_FDCS_CRC_CONT_SHIFT 2 3424#define I40E_MNGSB_FDCS_CRC_CONT_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_CONT_SHIFT) 3425#define I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT 3 3426#define I40E_MNGSB_FDCS_CRC_SEED_EN_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_SEED_EN_SHIFT) 3427#define I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT 4 3428#define I40E_MNGSB_FDCS_CRC_WR_INH_MASK I40E_MASK(0x1, I40E_MNGSB_FDCS_CRC_WR_INH_SHIFT) 3429#define I40E_MNGSB_FDCS_CRC_SEED_SHIFT 8 3430#define I40E_MNGSB_FDCS_CRC_SEED_MASK I40E_MASK(0xFF, I40E_MNGSB_FDCS_CRC_SEED_SHIFT) 3431#define I40E_MNGSB_FDS 0x000B7048 /* Reset: POR */ 3432#define I40E_MNGSB_FDS_START_BC_SHIFT 0 3433#define I40E_MNGSB_FDS_START_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_START_BC_SHIFT) 3434#define I40E_MNGSB_FDS_LAST_BC_SHIFT 16 3435#define I40E_MNGSB_FDS_LAST_BC_MASK I40E_MASK(0xFFF, I40E_MNGSB_FDS_LAST_BC_SHIFT) 3436 3437#define I40E_GL_VF_CTRL_RX(_VF) (0x00083600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 3438#define I40E_GL_VF_CTRL_RX_MAX_INDEX 127 3439#define I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT 0 3440#define I40E_GL_VF_CTRL_RX_AQ_RX_EN_MASK I40E_MASK(0x1, I40E_GL_VF_CTRL_RX_AQ_RX_EN_SHIFT) 3441#define I40E_GL_VF_CTRL_TX(_VF) (0x00083400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 3442#define I40E_GL_VF_CTRL_TX_MAX_INDEX 127 3443#define I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT 0 3444#define I40E_GL_VF_CTRL_TX_AQ_TX_EN_MASK I40E_MASK(0x1, I40E_GL_VF_CTRL_TX_AQ_TX_EN_SHIFT) 3445 3446#define I40E_GLCM_LAN_CACHESIZE 0x0010C4D8 /* Reset: CORER */ 3447#define I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT 0 3448#define I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_LAN_CACHESIZE_WORD_SIZE_SHIFT) 3449#define I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT 12 3450#define I40E_GLCM_LAN_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_LAN_CACHESIZE_SETS_SHIFT) 3451#define I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT 16 3452#define I40E_GLCM_LAN_CACHESIZE_WAYS_MASK I40E_MASK(0x3FF, I40E_GLCM_LAN_CACHESIZE_WAYS_SHIFT) 3453#define I40E_GLCM_PE_CACHESIZE 0x00138FE4 /* Reset: CORER */ 3454#define I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT 0 3455#define I40E_GLCM_PE_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFFF, I40E_GLCM_PE_CACHESIZE_WORD_SIZE_SHIFT) 3456#define I40E_GLCM_PE_CACHESIZE_SETS_SHIFT 12 3457#define I40E_GLCM_PE_CACHESIZE_SETS_MASK I40E_MASK(0xF, I40E_GLCM_PE_CACHESIZE_SETS_SHIFT) 3458#define I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT 16 3459#define I40E_GLCM_PE_CACHESIZE_WAYS_MASK I40E_MASK(0x1FF, I40E_GLCM_PE_CACHESIZE_WAYS_SHIFT) 3460#define I40E_PFCM_PE_ERRDATA 0x00138D00 /* Reset: PFR */ 3461#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 3462#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT) 3463#define I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 3464#define I40E_PFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT) 3465#define I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT 8 3466#define I40E_PFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT) 3467#define I40E_PFCM_PE_ERRINFO 0x00138C80 /* Reset: PFR */ 3468#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 3469#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT) 3470#define I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 3471#define I40E_PFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT) 3472#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 3473#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) 3474#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 3475#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) 3476#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 3477#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) 3478 3479#define I40E_PRTDCB_TFMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 3480#define I40E_PRTDCB_TFMSTC_MAX_INDEX 7 3481#define I40E_PRTDCB_TFMSTC_MSTC_SHIFT 0 3482#define I40E_PRTDCB_TFMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TFMSTC_MSTC_SHIFT) 3483#define I40E_GL_FWSTS_FWROWD_SHIFT 8 3484#define I40E_GL_FWSTS_FWROWD_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWROWD_SHIFT) 3485#define I40E_GLFOC_CACHESIZE 0x000AA0DC /* Reset: CORER */ 3486#define I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT 0 3487#define I40E_GLFOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLFOC_CACHESIZE_WORD_SIZE_SHIFT) 3488#define I40E_GLFOC_CACHESIZE_SETS_SHIFT 8 3489#define I40E_GLFOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLFOC_CACHESIZE_SETS_SHIFT) 3490#define I40E_GLFOC_CACHESIZE_WAYS_SHIFT 20 3491#define I40E_GLFOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLFOC_CACHESIZE_WAYS_SHIFT) 3492#define I40E_GLHMC_APBVTINUSEBASE(_i) (0x000C4a00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3493#define I40E_GLHMC_APBVTINUSEBASE_MAX_INDEX 15 3494#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0 3495#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT) 3496#define I40E_GLHMC_CEQPART(_i) (0x001312C0 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3497#define I40E_GLHMC_CEQPART_MAX_INDEX 15 3498#define I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT 0 3499#define I40E_GLHMC_CEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT) 3500#define I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT 16 3501#define I40E_GLHMC_CEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT) 3502#define I40E_GLHMC_DBCQMAX 0x000C20F0 /* Reset: CORER */ 3503#define I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT 0 3504#define I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_MASK I40E_MASK(0x3FFFF, I40E_GLHMC_DBCQMAX_GLHMC_DBCQMAX_SHIFT) 3505#define I40E_GLHMC_DBCQPART(_i) (0x00131240 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3506#define I40E_GLHMC_DBCQPART_MAX_INDEX 15 3507#define I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT 0 3508#define I40E_GLHMC_DBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT) 3509#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT 16 3510#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT) 3511#define I40E_GLHMC_DBQPMAX 0x000C20EC /* Reset: CORER */ 3512#define I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT 0 3513#define I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_MASK I40E_MASK(0x7FFFF, I40E_GLHMC_DBQPMAX_GLHMC_DBQPMAX_SHIFT) 3514#define I40E_GLHMC_DBQPPART(_i) (0x00138D80 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3515#define I40E_GLHMC_DBQPPART_MAX_INDEX 15 3516#define I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT 0 3517#define I40E_GLHMC_DBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT) 3518#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT 16 3519#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT) 3520#define I40E_GLHMC_PEARPBASE(_i) (0x000C4800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3521#define I40E_GLHMC_PEARPBASE_MAX_INDEX 15 3522#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT 0 3523#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT) 3524#define I40E_GLHMC_PEARPCNT(_i) (0x000C4900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3525#define I40E_GLHMC_PEARPCNT_MAX_INDEX 15 3526#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT 0 3527#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT) 3528#define I40E_GLHMC_PEARPMAX 0x000C2038 /* Reset: CORER */ 3529#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT 0 3530#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT) 3531#define I40E_GLHMC_PEARPOBJSZ 0x000C2034 /* Reset: CORER */ 3532#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT 0 3533#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_MASK I40E_MASK(0x7, I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT) 3534#define I40E_GLHMC_PECQBASE(_i) (0x000C4200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3535#define I40E_GLHMC_PECQBASE_MAX_INDEX 15 3536#define I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT 0 3537#define I40E_GLHMC_PECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT) 3538#define I40E_GLHMC_PECQCNT(_i) (0x000C4300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3539#define I40E_GLHMC_PECQCNT_MAX_INDEX 15 3540#define I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT 0 3541#define I40E_GLHMC_PECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT) 3542#define I40E_GLHMC_PECQOBJSZ 0x000C2020 /* Reset: CORER */ 3543#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT 0 3544#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT) 3545#define I40E_GLHMC_PEHTCNT(_i) (0x000C4700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3546#define I40E_GLHMC_PEHTCNT_MAX_INDEX 15 3547#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT 0 3548#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT) 3549#define I40E_GLHMC_PEHTEBASE(_i) (0x000C4600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3550#define I40E_GLHMC_PEHTEBASE_MAX_INDEX 15 3551#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT 0 3552#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT) 3553#define I40E_GLHMC_PEHTEOBJSZ 0x000C202c /* Reset: CORER */ 3554#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT 0 3555#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT) 3556#define I40E_GLHMC_PEHTMAX 0x000C2030 /* Reset: CORER */ 3557#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT 0 3558#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_MASK I40E_MASK(0x1FFFFF, I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT) 3559#define I40E_GLHMC_PEMRBASE(_i) (0x000C4c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3560#define I40E_GLHMC_PEMRBASE_MAX_INDEX 15 3561#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT 0 3562#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT) 3563#define I40E_GLHMC_PEMRCNT(_i) (0x000C4d00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3564#define I40E_GLHMC_PEMRCNT_MAX_INDEX 15 3565#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT 0 3566#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT) 3567#define I40E_GLHMC_PEMRMAX 0x000C2040 /* Reset: CORER */ 3568#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT 0 3569#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT) 3570#define I40E_GLHMC_PEMROBJSZ 0x000C203c /* Reset: CORER */ 3571#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT 0 3572#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT) 3573#define I40E_GLHMC_PEPBLBASE(_i) (0x000C5800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3574#define I40E_GLHMC_PEPBLBASE_MAX_INDEX 15 3575#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT 0 3576#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT) 3577#define I40E_GLHMC_PEPBLCNT(_i) (0x000C5900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3578#define I40E_GLHMC_PEPBLCNT_MAX_INDEX 15 3579#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT 0 3580#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT) 3581#define I40E_GLHMC_PEPBLMAX 0x000C206c /* Reset: CORER */ 3582#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT 0 3583#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT) 3584#define I40E_GLHMC_PEPFFIRSTSD 0x000C20E4 /* Reset: CORER */ 3585#define I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT 0 3586#define I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_MASK I40E_MASK(0xFFF, I40E_GLHMC_PEPFFIRSTSD_GLHMC_PEPFFIRSTSD_SHIFT) 3587#define I40E_GLHMC_PEQ1BASE(_i) (0x000C5200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3588#define I40E_GLHMC_PEQ1BASE_MAX_INDEX 15 3589#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT 0 3590#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT) 3591#define I40E_GLHMC_PEQ1CNT(_i) (0x000C5300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3592#define I40E_GLHMC_PEQ1CNT_MAX_INDEX 15 3593#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT 0 3594#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT) 3595#define I40E_GLHMC_PEQ1FLBASE(_i) (0x000C5400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3596#define I40E_GLHMC_PEQ1FLBASE_MAX_INDEX 15 3597#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0 3598#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT) 3599#define I40E_GLHMC_PEQ1FLMAX 0x000C2058 /* Reset: CORER */ 3600#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT 0 3601#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT) 3602#define I40E_GLHMC_PEQ1MAX 0x000C2054 /* Reset: CORER */ 3603#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT 0 3604#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT) 3605#define I40E_GLHMC_PEQ1OBJSZ 0x000C2050 /* Reset: CORER */ 3606#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT 0 3607#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT) 3608#define I40E_GLHMC_PEQPBASE(_i) (0x000C4000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3609#define I40E_GLHMC_PEQPBASE_MAX_INDEX 15 3610#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT 0 3611#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT) 3612#define I40E_GLHMC_PEQPCNT(_i) (0x000C4100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3613#define I40E_GLHMC_PEQPCNT_MAX_INDEX 15 3614#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT 0 3615#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT) 3616#define I40E_GLHMC_PEQPOBJSZ 0x000C201c /* Reset: CORER */ 3617#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT 0 3618#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT) 3619#define I40E_GLHMC_PESRQBASE(_i) (0x000C4400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3620#define I40E_GLHMC_PESRQBASE_MAX_INDEX 15 3621#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT 0 3622#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT) 3623#define I40E_GLHMC_PESRQCNT(_i) (0x000C4500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3624#define I40E_GLHMC_PESRQCNT_MAX_INDEX 15 3625#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT 0 3626#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT) 3627#define I40E_GLHMC_PESRQMAX 0x000C2028 /* Reset: CORER */ 3628#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT 0 3629#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT) 3630#define I40E_GLHMC_PESRQOBJSZ 0x000C2024 /* Reset: CORER */ 3631#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT 0 3632#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT) 3633#define I40E_GLHMC_PETIMERBASE(_i) (0x000C5A00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3634#define I40E_GLHMC_PETIMERBASE_MAX_INDEX 15 3635#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT 0 3636#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT) 3637#define I40E_GLHMC_PETIMERCNT(_i) (0x000C5B00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3638#define I40E_GLHMC_PETIMERCNT_MAX_INDEX 15 3639#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT 0 3640#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT) 3641#define I40E_GLHMC_PETIMERMAX 0x000C2084 /* Reset: CORER */ 3642#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT 0 3643#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT) 3644#define I40E_GLHMC_PETIMEROBJSZ 0x000C2080 /* Reset: CORER */ 3645#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT 0 3646#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT) 3647#define I40E_GLHMC_PEXFBASE(_i) (0x000C4e00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3648#define I40E_GLHMC_PEXFBASE_MAX_INDEX 15 3649#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT 0 3650#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT) 3651#define I40E_GLHMC_PEXFCNT(_i) (0x000C4f00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3652#define I40E_GLHMC_PEXFCNT_MAX_INDEX 15 3653#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT 0 3654#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT) 3655#define I40E_GLHMC_PEXFFLBASE(_i) (0x000C5000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3656#define I40E_GLHMC_PEXFFLBASE_MAX_INDEX 15 3657#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT 0 3658#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT) 3659#define I40E_GLHMC_PEXFFLMAX 0x000C204c /* Reset: CORER */ 3660#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT 0 3661#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK I40E_MASK(0x1FFFFFF, I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT) 3662#define I40E_GLHMC_PEXFMAX 0x000C2048 /* Reset: CORER */ 3663#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT 0 3664#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK I40E_MASK(0x3FFFFFF, I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT) 3665#define I40E_GLHMC_PEXFOBJSZ 0x000C2044 /* Reset: CORER */ 3666#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT 0 3667#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT) 3668#define I40E_GLHMC_PFPESDPART(_i) (0x000C0880 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3669#define I40E_GLHMC_PFPESDPART_MAX_INDEX 15 3670#define I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT 0 3671#define I40E_GLHMC_PFPESDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_PFPESDPART_PMSDBASE_SHIFT) 3672#define I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT 16 3673#define I40E_GLHMC_PFPESDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_PFPESDPART_PMSDSIZE_SHIFT) 3674#define I40E_GLHMC_VFAPBVTINUSEBASE(_i) (0x000Cca00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3675#define I40E_GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31 3676#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0 3677#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT) 3678#define I40E_GLHMC_VFCEQPART(_i) (0x00132240 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3679#define I40E_GLHMC_VFCEQPART_MAX_INDEX 31 3680#define I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT 0 3681#define I40E_GLHMC_VFCEQPART_PMCEQBASE_MASK I40E_MASK(0xFF, I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT) 3682#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT 16 3683#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT) 3684#define I40E_GLHMC_VFDBCQPART(_i) (0x00132140 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3685#define I40E_GLHMC_VFDBCQPART_MAX_INDEX 31 3686#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT 0 3687#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT) 3688#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT 16 3689#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT) 3690#define I40E_GLHMC_VFDBQPPART(_i) (0x00138E00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3691#define I40E_GLHMC_VFDBQPPART_MAX_INDEX 31 3692#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT 0 3693#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_MASK I40E_MASK(0x3FFF, I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT) 3694#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT 16 3695#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_MASK I40E_MASK(0x7FFF, I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT) 3696#define I40E_GLHMC_VFFSIAVBASE(_i) (0x000Cd600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3697#define I40E_GLHMC_VFFSIAVBASE_MAX_INDEX 31 3698#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT 0 3699#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT) 3700#define I40E_GLHMC_VFFSIAVCNT(_i) (0x000Cd700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3701#define I40E_GLHMC_VFFSIAVCNT_MAX_INDEX 31 3702#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT 0 3703#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT) 3704#define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3705#define I40E_GLHMC_VFPDINV_MAX_INDEX 31 3706#define I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT 0 3707#define I40E_GLHMC_VFPDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT) 3708#define I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT 15 3709#define I40E_GLHMC_VFPDINV_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_GLHMC_VFPDINV_PMSDPARTSEL_SHIFT) 3710#define I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT 16 3711#define I40E_GLHMC_VFPDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT) 3712#define I40E_GLHMC_VFPEARPBASE(_i) (0x000Cc800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3713#define I40E_GLHMC_VFPEARPBASE_MAX_INDEX 31 3714#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT 0 3715#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT) 3716#define I40E_GLHMC_VFPEARPCNT(_i) (0x000Cc900 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3717#define I40E_GLHMC_VFPEARPCNT_MAX_INDEX 31 3718#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT 0 3719#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT) 3720#define I40E_GLHMC_VFPECQBASE(_i) (0x000Cc200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3721#define I40E_GLHMC_VFPECQBASE_MAX_INDEX 31 3722#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT 0 3723#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT) 3724#define I40E_GLHMC_VFPECQCNT(_i) (0x000Cc300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3725#define I40E_GLHMC_VFPECQCNT_MAX_INDEX 31 3726#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT 0 3727#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT) 3728#define I40E_GLHMC_VFPEHTCNT(_i) (0x000Cc700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3729#define I40E_GLHMC_VFPEHTCNT_MAX_INDEX 31 3730#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT 0 3731#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT) 3732#define I40E_GLHMC_VFPEHTEBASE(_i) (0x000Cc600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3733#define I40E_GLHMC_VFPEHTEBASE_MAX_INDEX 31 3734#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT 0 3735#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT) 3736#define I40E_GLHMC_VFPEMRBASE(_i) (0x000Ccc00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3737#define I40E_GLHMC_VFPEMRBASE_MAX_INDEX 31 3738#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT 0 3739#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT) 3740#define I40E_GLHMC_VFPEMRCNT(_i) (0x000Ccd00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3741#define I40E_GLHMC_VFPEMRCNT_MAX_INDEX 31 3742#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT 0 3743#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT) 3744#define I40E_GLHMC_VFPEPBLBASE(_i) (0x000Cd800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3745#define I40E_GLHMC_VFPEPBLBASE_MAX_INDEX 31 3746#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT 0 3747#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT) 3748#define I40E_GLHMC_VFPEPBLCNT(_i) (0x000Cd900 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3749#define I40E_GLHMC_VFPEPBLCNT_MAX_INDEX 31 3750#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT 0 3751#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT) 3752#define I40E_GLHMC_VFPEQ1BASE(_i) (0x000Cd200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3753#define I40E_GLHMC_VFPEQ1BASE_MAX_INDEX 31 3754#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT 0 3755#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT) 3756#define I40E_GLHMC_VFPEQ1CNT(_i) (0x000Cd300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3757#define I40E_GLHMC_VFPEQ1CNT_MAX_INDEX 31 3758#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT 0 3759#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT) 3760#define I40E_GLHMC_VFPEQ1FLBASE(_i) (0x000Cd400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3761#define I40E_GLHMC_VFPEQ1FLBASE_MAX_INDEX 31 3762#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0 3763#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT) 3764#define I40E_GLHMC_VFPEQPBASE(_i) (0x000Cc000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3765#define I40E_GLHMC_VFPEQPBASE_MAX_INDEX 31 3766#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT 0 3767#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT) 3768#define I40E_GLHMC_VFPEQPCNT(_i) (0x000Cc100 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3769#define I40E_GLHMC_VFPEQPCNT_MAX_INDEX 31 3770#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT 0 3771#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT) 3772#define I40E_GLHMC_VFPESRQBASE(_i) (0x000Cc400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3773#define I40E_GLHMC_VFPESRQBASE_MAX_INDEX 31 3774#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT 0 3775#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT) 3776#define I40E_GLHMC_VFPESRQCNT(_i) (0x000Cc500 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3777#define I40E_GLHMC_VFPESRQCNT_MAX_INDEX 31 3778#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT 0 3779#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT) 3780#define I40E_GLHMC_VFPETIMERBASE(_i) (0x000CDA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3781#define I40E_GLHMC_VFPETIMERBASE_MAX_INDEX 31 3782#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT 0 3783#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT) 3784#define I40E_GLHMC_VFPETIMERCNT(_i) (0x000CDB00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3785#define I40E_GLHMC_VFPETIMERCNT_MAX_INDEX 31 3786#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT 0 3787#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT) 3788#define I40E_GLHMC_VFPEXFBASE(_i) (0x000Cce00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3789#define I40E_GLHMC_VFPEXFBASE_MAX_INDEX 31 3790#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT 0 3791#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT) 3792#define I40E_GLHMC_VFPEXFCNT(_i) (0x000Ccf00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3793#define I40E_GLHMC_VFPEXFCNT_MAX_INDEX 31 3794#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT 0 3795#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT) 3796#define I40E_GLHMC_VFPEXFFLBASE(_i) (0x000Cd000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3797#define I40E_GLHMC_VFPEXFFLBASE_MAX_INDEX 31 3798#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT 0 3799#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT) 3800#define I40E_GLHMC_VFSDPART(_i) (0x000C8800 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 3801#define I40E_GLHMC_VFSDPART_MAX_INDEX 31 3802#define I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT 0 3803#define I40E_GLHMC_VFSDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT) 3804#define I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT 16 3805#define I40E_GLHMC_VFSDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT) 3806#define I40E_GLPBLOC_CACHESIZE 0x000A80BC /* Reset: CORER */ 3807#define I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT 0 3808#define I40E_GLPBLOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPBLOC_CACHESIZE_WORD_SIZE_SHIFT) 3809#define I40E_GLPBLOC_CACHESIZE_SETS_SHIFT 8 3810#define I40E_GLPBLOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPBLOC_CACHESIZE_SETS_SHIFT) 3811#define I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT 20 3812#define I40E_GLPBLOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPBLOC_CACHESIZE_WAYS_SHIFT) 3813#define I40E_GLPDOC_CACHESIZE 0x000D0088 /* Reset: CORER */ 3814#define I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT 0 3815#define I40E_GLPDOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPDOC_CACHESIZE_WORD_SIZE_SHIFT) 3816#define I40E_GLPDOC_CACHESIZE_SETS_SHIFT 8 3817#define I40E_GLPDOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPDOC_CACHESIZE_SETS_SHIFT) 3818#define I40E_GLPDOC_CACHESIZE_WAYS_SHIFT 20 3819#define I40E_GLPDOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPDOC_CACHESIZE_WAYS_SHIFT) 3820#define I40E_GLPEOC_CACHESIZE 0x000A60E8 /* Reset: CORER */ 3821#define I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT 0 3822#define I40E_GLPEOC_CACHESIZE_WORD_SIZE_MASK I40E_MASK(0xFF, I40E_GLPEOC_CACHESIZE_WORD_SIZE_SHIFT) 3823#define I40E_GLPEOC_CACHESIZE_SETS_SHIFT 8 3824#define I40E_GLPEOC_CACHESIZE_SETS_MASK I40E_MASK(0xFFF, I40E_GLPEOC_CACHESIZE_SETS_SHIFT) 3825#define I40E_GLPEOC_CACHESIZE_WAYS_SHIFT 20 3826#define I40E_GLPEOC_CACHESIZE_WAYS_MASK I40E_MASK(0xF, I40E_GLPEOC_CACHESIZE_WAYS_SHIFT) 3827#define I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT 15 3828#define I40E_PFHMC_PDINV_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT) 3829#define I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT 15 3830#define I40E_PFHMC_SDCMD_PMSDPARTSEL_MASK I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDPARTSEL_SHIFT) 3831#define I40E_GL_PPRS_SPARE 0x000856E0 /* Reset: CORER */ 3832#define I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT 0 3833#define I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_PPRS_SPARE_GL_PPRS_SPARE_SHIFT) 3834#define I40E_GL_TLAN_SPARE 0x000E64E0 /* Reset: CORER */ 3835#define I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT 0 3836#define I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TLAN_SPARE_GL_TLAN_SPARE_SHIFT) 3837#define I40E_GL_TUPM_SPARE 0x000a2230 /* Reset: CORER */ 3838#define I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT 0 3839#define I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_TUPM_SPARE_GL_TUPM_SPARE_SHIFT) 3840#define I40E_GLGEN_CAR_DEBUG 0x000B81C0 /* Reset: POR */ 3841#define I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT 0 3842#define I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_SHIFT) 3843#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT 1 3844#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_SHIFT) 3845#define I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT 2 3846#define I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_SHIFT) 3847#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT 3 3848#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_SHIFT) 3849#define I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT 4 3850#define I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_SHIFT) 3851#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT 5 3852#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_SHIFT) 3853#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT 6 3854#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_SHIFT) 3855#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT 7 3856#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_SHIFT) 3857#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT 8 3858#define I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_SHIFT) 3859#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT 9 3860#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_SHIFT) 3861#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT 10 3862#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_SHIFT) 3863#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT 11 3864#define I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_SHIFT) 3865#define I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT 12 3866#define I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_SHIFT) 3867#define I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT 13 3868#define I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_SHIFT) 3869#define I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT 14 3870#define I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_MASK I40E_MASK(0x1, I40E_GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_SHIFT) 3871#define I40E_GLGEN_MISC_SPARE 0x000880E0 /* Reset: POR */ 3872#define I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT 0 3873#define I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_MISC_SPARE_GLGEN_MISC_SPARE_SHIFT) 3874#define I40E_GL_UFUSE_SOC 0x000BE550 /* Reset: POR */ 3875#define I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT 0 3876#define I40E_GL_UFUSE_SOC_PORT_MODE_MASK I40E_MASK(0x3, I40E_GL_UFUSE_SOC_PORT_MODE_SHIFT) 3877#define I40E_GL_UFUSE_SOC_NIC_ID_SHIFT 2 3878#define I40E_GL_UFUSE_SOC_NIC_ID_MASK I40E_MASK(0x1, I40E_GL_UFUSE_SOC_NIC_ID_SHIFT) 3879#define I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT 3 3880#define I40E_GL_UFUSE_SOC_SPARE_FUSES_MASK I40E_MASK(0x1FFF, I40E_GL_UFUSE_SOC_SPARE_FUSES_SHIFT) 3881#define I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30 3882#define I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT) 3883#define I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30 3884#define I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT) 3885#define I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30 3886#define I40E_VFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_WB_ON_ITR_SHIFT) 3887#define I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30 3888#define I40E_VFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_WB_ON_ITR_SHIFT) 3889#define I40E_VPLAN_QBASE(_VF) (0x00074800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 3890#define I40E_VPLAN_QBASE_MAX_INDEX 127 3891#define I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT 0 3892#define I40E_VPLAN_QBASE_VFFIRSTQ_MASK I40E_MASK(0x7FF, I40E_VPLAN_QBASE_VFFIRSTQ_SHIFT) 3893#define I40E_VPLAN_QBASE_VFNUMQ_SHIFT 11 3894#define I40E_VPLAN_QBASE_VFNUMQ_MASK I40E_MASK(0xFF, I40E_VPLAN_QBASE_VFNUMQ_SHIFT) 3895#define I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT 31 3896#define I40E_VPLAN_QBASE_VFQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_QBASE_VFQTABLE_ENA_SHIFT) 3897#define I40E_PRTMAC_LINK_DOWN_COUNTER 0x001E2440 /* Reset: GLOBR */ 3898#define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT 0 3899#define I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_SHIFT) 3900#define I40E_GLNVM_AL_REQ 0x000B6164 /* Reset: POR */ 3901#define I40E_GLNVM_AL_REQ_POR_SHIFT 0 3902#define I40E_GLNVM_AL_REQ_POR_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_POR_SHIFT) 3903#define I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT 1 3904#define I40E_GLNVM_AL_REQ_PCIE_IMIB_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PCIE_IMIB_SHIFT) 3905#define I40E_GLNVM_AL_REQ_GLOBR_SHIFT 2 3906#define I40E_GLNVM_AL_REQ_GLOBR_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_GLOBR_SHIFT) 3907#define I40E_GLNVM_AL_REQ_CORER_SHIFT 3 3908#define I40E_GLNVM_AL_REQ_CORER_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_CORER_SHIFT) 3909#define I40E_GLNVM_AL_REQ_PE_SHIFT 4 3910#define I40E_GLNVM_AL_REQ_PE_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PE_SHIFT) 3911#define I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT 5 3912#define I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_MASK I40E_MASK(0x1, I40E_GLNVM_AL_REQ_PCIE_IMIB_ASSERT_SHIFT) 3913#define I40E_GLNVM_ALTIMERS 0x000B6140 /* Reset: POR */ 3914#define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT 0 3915#define I40E_GLNVM_ALTIMERS_PCI_ALTIMER_MASK I40E_MASK(0xFFF, I40E_GLNVM_ALTIMERS_PCI_ALTIMER_SHIFT) 3916#define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT 12 3917#define I40E_GLNVM_ALTIMERS_GEN_ALTIMER_MASK I40E_MASK(0xFFFFF, I40E_GLNVM_ALTIMERS_GEN_ALTIMER_SHIFT) 3918#define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 3919#define I40E_GLNVM_FLA_LOCKED_SHIFT 6 3920#define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 3921 3922#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 3923#define I40E_GLNVM_ULD_PCIER_DONE_SHIFT 0 3924#define I40E_GLNVM_ULD_PCIER_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_SHIFT) 3925#define I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT 1 3926#define I40E_GLNVM_ULD_PCIER_DONE_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_1_SHIFT) 3927#define I40E_GLNVM_ULD_CORER_DONE_SHIFT 3 3928#define I40E_GLNVM_ULD_CORER_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CORER_DONE_SHIFT) 3929#define I40E_GLNVM_ULD_GLOBR_DONE_SHIFT 4 3930#define I40E_GLNVM_ULD_GLOBR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_GLOBR_DONE_SHIFT) 3931#define I40E_GLNVM_ULD_POR_DONE_SHIFT 5 3932#define I40E_GLNVM_ULD_POR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_POR_DONE_SHIFT) 3933#define I40E_GLNVM_ULD_POR_DONE_1_SHIFT 8 3934#define I40E_GLNVM_ULD_POR_DONE_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_POR_DONE_1_SHIFT) 3935#define I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT 9 3936#define I40E_GLNVM_ULD_PCIER_DONE_2_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PCIER_DONE_2_SHIFT) 3937#define I40E_GLNVM_ULD_PE_DONE_SHIFT 10 3938#define I40E_GLNVM_ULD_PE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_PE_DONE_SHIFT) 3939#define I40E_GLNVM_ULT 0x000B6154 /* Reset: POR */ 3940#define I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT 0 3941#define I40E_GLNVM_ULT_CONF_PCIR_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIR_AE_SHIFT) 3942#define I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT 1 3943#define I40E_GLNVM_ULT_CONF_PCIRTL_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIRTL_AE_SHIFT) 3944#define I40E_GLNVM_ULT_RESERVED_1_SHIFT 2 3945#define I40E_GLNVM_ULT_RESERVED_1_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_1_SHIFT) 3946#define I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT 3 3947#define I40E_GLNVM_ULT_CONF_CORE_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_CORE_AE_SHIFT) 3948#define I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT 4 3949#define I40E_GLNVM_ULT_CONF_GLOBAL_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_GLOBAL_AE_SHIFT) 3950#define I40E_GLNVM_ULT_CONF_POR_AE_SHIFT 5 3951#define I40E_GLNVM_ULT_CONF_POR_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_POR_AE_SHIFT) 3952#define I40E_GLNVM_ULT_RESERVED_2_SHIFT 6 3953#define I40E_GLNVM_ULT_RESERVED_2_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_2_SHIFT) 3954#define I40E_GLNVM_ULT_RESERVED_3_SHIFT 7 3955#define I40E_GLNVM_ULT_RESERVED_3_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_RESERVED_3_SHIFT) 3956#define I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT 8 3957#define I40E_GLNVM_ULT_CONF_EMP_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_EMP_AE_SHIFT) 3958#define I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT 9 3959#define I40E_GLNVM_ULT_CONF_PCIALT_AE_MASK I40E_MASK(0x1, I40E_GLNVM_ULT_CONF_PCIALT_AE_SHIFT) 3960#define I40E_GLNVM_ULT_RESERVED_4_SHIFT 10 3961#define I40E_GLNVM_ULT_RESERVED_4_MASK I40E_MASK(0x3FFFFF, I40E_GLNVM_ULT_RESERVED_4_SHIFT) 3962#define I40E_MEM_INIT_DONE_STAT 0x000B615C /* Reset: POR */ 3963#define I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT 0 3964#define I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_CMLAN_MEM_INIT_DONE_SHIFT) 3965#define I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT 1 3966#define I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_PMAT_MEM_INIT_DONE_SHIFT) 3967#define I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT 2 3968#define I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RCU_MEM_INIT_DONE_SHIFT) 3969#define I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT 3 3970#define I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TDPU_MEM_INIT_DONE_SHIFT) 3971#define I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT 4 3972#define I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TLAN_MEM_INIT_DONE_SHIFT) 3973#define I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT 5 3974#define I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RLAN_MEM_INIT_DONE_SHIFT) 3975#define I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT 6 3976#define I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RDPU_MEM_INIT_DONE_SHIFT) 3977#define I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT 7 3978#define I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_PPRS_MEM_INIT_DONE_SHIFT) 3979#define I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT 8 3980#define I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RPB_MEM_INIT_DONE_SHIFT) 3981#define I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT 9 3982#define I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TPB_MEM_INIT_DONE_SHIFT) 3983#define I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT 10 3984#define I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_FOC_MEM_INIT_DONE_SHIFT) 3985#define I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT 11 3986#define I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TSCD_MEM_INIT_DONE_SHIFT) 3987#define I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT 12 3988#define I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_TCB_MEM_INIT_DONE_SHIFT) 3989#define I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT 13 3990#define I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_RCB_MEM_INIT_DONE_SHIFT) 3991#define I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT 14 3992#define I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_WUC_MEM_INIT_DONE_SHIFT) 3993#define I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT 15 3994#define I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_STAT_MEM_INIT_DONE_SHIFT) 3995#define I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT 16 3996#define I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_MASK I40E_MASK(0x1, I40E_MEM_INIT_DONE_STAT_ITR_MEM_INIT_DONE_SHIFT) 3997#define I40E_MNGSB_DADD 0x000B7030 /* Reset: POR */ 3998#define I40E_MNGSB_DADD_ADDR_SHIFT 0 3999#define I40E_MNGSB_DADD_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DADD_ADDR_SHIFT) 4000#define I40E_MNGSB_DCNT 0x000B7034 /* Reset: POR */ 4001#define I40E_MNGSB_DCNT_BYTE_CNT_SHIFT 0 4002#define I40E_MNGSB_DCNT_BYTE_CNT_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_DCNT_BYTE_CNT_SHIFT) 4003#define I40E_MNGSB_MSGCTL 0x000B7020 /* Reset: POR */ 4004#define I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT 0 4005#define I40E_MNGSB_MSGCTL_HDR_DWS_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_HDR_DWS_SHIFT) 4006#define I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT 8 4007#define I40E_MNGSB_MSGCTL_EXP_RDW_MASK I40E_MASK(0x1FF, I40E_MNGSB_MSGCTL_EXP_RDW_SHIFT) 4008#define I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT 26 4009#define I40E_MNGSB_MSGCTL_MSG_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_MSG_MODE_SHIFT) 4010#define I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT 28 4011#define I40E_MNGSB_MSGCTL_TOKEN_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_MSGCTL_TOKEN_MODE_SHIFT) 4012#define I40E_MNGSB_MSGCTL_BARCLR_SHIFT 30 4013#define I40E_MNGSB_MSGCTL_BARCLR_MASK I40E_MASK(0x1, I40E_MNGSB_MSGCTL_BARCLR_SHIFT) 4014#define I40E_MNGSB_MSGCTL_CMDV_SHIFT 31 4015#define I40E_MNGSB_MSGCTL_CMDV_MASK I40E_MASK(0x1, I40E_MNGSB_MSGCTL_CMDV_SHIFT) 4016#define I40E_MNGSB_RDATA 0x000B7300 /* Reset: POR */ 4017#define I40E_MNGSB_RDATA_DATA_SHIFT 0 4018#define I40E_MNGSB_RDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_RDATA_DATA_SHIFT) 4019#define I40E_MNGSB_RHDR0 0x000B72FC /* Reset: POR */ 4020#define I40E_MNGSB_RHDR0_DESTINATION_SHIFT 0 4021#define I40E_MNGSB_RHDR0_DESTINATION_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_DESTINATION_SHIFT) 4022#define I40E_MNGSB_RHDR0_SOURCE_SHIFT 8 4023#define I40E_MNGSB_RHDR0_SOURCE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_SOURCE_SHIFT) 4024#define I40E_MNGSB_RHDR0_OPCODE_SHIFT 16 4025#define I40E_MNGSB_RHDR0_OPCODE_MASK I40E_MASK(0xFF, I40E_MNGSB_RHDR0_OPCODE_SHIFT) 4026#define I40E_MNGSB_RHDR0_TAG_SHIFT 24 4027#define I40E_MNGSB_RHDR0_TAG_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_TAG_SHIFT) 4028#define I40E_MNGSB_RHDR0_RESPONSE_SHIFT 27 4029#define I40E_MNGSB_RHDR0_RESPONSE_MASK I40E_MASK(0x7, I40E_MNGSB_RHDR0_RESPONSE_SHIFT) 4030#define I40E_MNGSB_RHDR0_EH_SHIFT 31 4031#define I40E_MNGSB_RHDR0_EH_MASK I40E_MASK(0x1, I40E_MNGSB_RHDR0_EH_SHIFT) 4032#define I40E_MNGSB_RSPCTL 0x000B7024 /* Reset: POR */ 4033#define I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT 0 4034#define I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_MASK I40E_MASK(0x1FF, I40E_MNGSB_RSPCTL_DMA_MSG_DWORDS_SHIFT) 4035#define I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT 26 4036#define I40E_MNGSB_RSPCTL_RSP_MODE_MASK I40E_MASK(0x3, I40E_MNGSB_RSPCTL_RSP_MODE_SHIFT) 4037#define I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT 30 4038#define I40E_MNGSB_RSPCTL_RSP_BAD_LEN_MASK I40E_MASK(0x1, I40E_MNGSB_RSPCTL_RSP_BAD_LEN_SHIFT) 4039#define I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT 31 4040#define I40E_MNGSB_RSPCTL_RSP_ERR_MASK I40E_MASK(0x1, I40E_MNGSB_RSPCTL_RSP_ERR_SHIFT) 4041#define I40E_MNGSB_WDATA 0x000B7100 /* Reset: POR */ 4042#define I40E_MNGSB_WDATA_DATA_SHIFT 0 4043#define I40E_MNGSB_WDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WDATA_DATA_SHIFT) 4044#define I40E_MNGSB_WHDR0 0x000B70F4 /* Reset: POR */ 4045#define I40E_MNGSB_WHDR0_RAW_DEST_SHIFT 0 4046#define I40E_MNGSB_WHDR0_RAW_DEST_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_RAW_DEST_SHIFT) 4047#define I40E_MNGSB_WHDR0_DEST_SEL_SHIFT 12 4048#define I40E_MNGSB_WHDR0_DEST_SEL_MASK I40E_MASK(0xF, I40E_MNGSB_WHDR0_DEST_SEL_SHIFT) 4049#define I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT 16 4050#define I40E_MNGSB_WHDR0_OPCODE_SEL_MASK I40E_MASK(0xFF, I40E_MNGSB_WHDR0_OPCODE_SEL_SHIFT) 4051#define I40E_MNGSB_WHDR0_TAG_SHIFT 24 4052#define I40E_MNGSB_WHDR0_TAG_MASK I40E_MASK(0x7F, I40E_MNGSB_WHDR0_TAG_SHIFT) 4053#define I40E_MNGSB_WHDR1 0x000B70F8 /* Reset: POR */ 4054#define I40E_MNGSB_WHDR1_ADDR_SHIFT 0 4055#define I40E_MNGSB_WHDR1_ADDR_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR1_ADDR_SHIFT) 4056#define I40E_MNGSB_WHDR2 0x000B70FC /* Reset: POR */ 4057#define I40E_MNGSB_WHDR2_LENGTH_SHIFT 0 4058#define I40E_MNGSB_WHDR2_LENGTH_MASK I40E_MASK(0xFFFFFFFF, I40E_MNGSB_WHDR2_LENGTH_SHIFT) 4059 4060#define I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT 21 4061#define I40E_GLPCI_CAPSUP_WAKUP_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_WAKUP_EN_SHIFT) 4062 4063#define I40E_GLPCI_CUR_CLNT_COMMON 0x0009CA18 /* Reset: PCIR */ 4064#define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT 0 4065#define I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_DATA_LINES_SHIFT) 4066#define I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT 16 4067#define I40E_GLPCI_CUR_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_COMMON_OSR_SHIFT) 4068#define I40E_GLPCI_CUR_CLNT_PIPEMON 0x0009CA20 /* Reset: PCIR */ 4069#define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT 0 4070#define I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_CLNT_PIPEMON_DATA_LINES_SHIFT) 4071#define I40E_GLPCI_CUR_MNG_ALWD 0x0009c514 /* Reset: PCIR */ 4072#define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT 0 4073#define I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_DATA_LINES_SHIFT) 4074#define I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT 16 4075#define I40E_GLPCI_CUR_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_ALWD_OSR_SHIFT) 4076#define I40E_GLPCI_CUR_MNG_RSVD 0x0009c594 /* Reset: PCIR */ 4077#define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT 0 4078#define I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_DATA_LINES_SHIFT) 4079#define I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT 16 4080#define I40E_GLPCI_CUR_MNG_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_MNG_RSVD_OSR_SHIFT) 4081#define I40E_GLPCI_CUR_PMAT_ALWD 0x0009c510 /* Reset: PCIR */ 4082#define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT 0 4083#define I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_DATA_LINES_SHIFT) 4084#define I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT 16 4085#define I40E_GLPCI_CUR_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_ALWD_OSR_SHIFT) 4086#define I40E_GLPCI_CUR_PMAT_RSVD 0x0009c590 /* Reset: PCIR */ 4087#define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT 0 4088#define I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_DATA_LINES_SHIFT) 4089#define I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT 16 4090#define I40E_GLPCI_CUR_PMAT_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_PMAT_RSVD_OSR_SHIFT) 4091#define I40E_GLPCI_CUR_RLAN_ALWD 0x0009c500 /* Reset: PCIR */ 4092#define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT 0 4093#define I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_DATA_LINES_SHIFT) 4094#define I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT 16 4095#define I40E_GLPCI_CUR_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_ALWD_OSR_SHIFT) 4096#define I40E_GLPCI_CUR_RLAN_RSVD 0x0009c580 /* Reset: PCIR */ 4097#define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT 0 4098#define I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_DATA_LINES_SHIFT) 4099#define I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT 16 4100#define I40E_GLPCI_CUR_RLAN_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RLAN_RSVD_OSR_SHIFT) 4101#define I40E_GLPCI_CUR_RXPE_ALWD 0x0009c508 /* Reset: PCIR */ 4102#define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT 0 4103#define I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_DATA_LINES_SHIFT) 4104#define I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT 16 4105#define I40E_GLPCI_CUR_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_ALWD_OSR_SHIFT) 4106#define I40E_GLPCI_CUR_RXPE_RSVD 0x0009c588 /* Reset: PCIR */ 4107#define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT 0 4108#define I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_DATA_LINES_SHIFT) 4109#define I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT 16 4110#define I40E_GLPCI_CUR_RXPE_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_RXPE_RSVD_OSR_SHIFT) 4111#define I40E_GLPCI_CUR_TDPU_ALWD 0x0009c518 /* Reset: PCIR */ 4112#define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT 0 4113#define I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_DATA_LINES_SHIFT) 4114#define I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT 16 4115#define I40E_GLPCI_CUR_TDPU_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_ALWD_OSR_SHIFT) 4116#define I40E_GLPCI_CUR_TDPU_RSVD 0x0009c598 /* Reset: PCIR */ 4117#define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT 0 4118#define I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_DATA_LINES_SHIFT) 4119#define I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT 16 4120#define I40E_GLPCI_CUR_TDPU_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TDPU_RSVD_OSR_SHIFT) 4121#define I40E_GLPCI_CUR_TLAN_ALWD 0x0009c504 /* Reset: PCIR */ 4122#define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT 0 4123#define I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_DATA_LINES_SHIFT) 4124#define I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT 16 4125#define I40E_GLPCI_CUR_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_ALWD_OSR_SHIFT) 4126#define I40E_GLPCI_CUR_TLAN_RSVD 0x0009c584 /* Reset: PCIR */ 4127#define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT 0 4128#define I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_DATA_LINES_SHIFT) 4129#define I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT 16 4130#define I40E_GLPCI_CUR_TLAN_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TLAN_RSVD_OSR_SHIFT) 4131#define I40E_GLPCI_CUR_TXPE_ALWD 0x0009c50C /* Reset: PCIR */ 4132#define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT 0 4133#define I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_DATA_LINES_SHIFT) 4134#define I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT 16 4135#define I40E_GLPCI_CUR_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_ALWD_OSR_SHIFT) 4136#define I40E_GLPCI_CUR_TXPE_RSVD 0x0009c58c /* Reset: PCIR */ 4137#define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT 0 4138#define I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_DATA_LINES_SHIFT) 4139#define I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT 16 4140#define I40E_GLPCI_CUR_TXPE_RSVD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_TXPE_RSVD_OSR_SHIFT) 4141#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON 0x0009CA28 /* Reset: PCIR */ 4142#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT 0 4143#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_DATA_LINES_SHIFT) 4144#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT 16 4145#define I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_CUR_WATMK_CLNT_COMMON_OSR_SHIFT) 4146 4147#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT 4 4148#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT) 4149#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT 10 4150#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT) 4151#define I40E_GLPCI_NPQ_CFG 0x0009CA00 /* Reset: PCIR */ 4152#define I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT 0 4153#define I40E_GLPCI_NPQ_CFG_EXTEND_TO_MASK I40E_MASK(0x1, I40E_GLPCI_NPQ_CFG_EXTEND_TO_SHIFT) 4154#define I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT 1 4155#define I40E_GLPCI_NPQ_CFG_SMALL_TO_MASK I40E_MASK(0x1, I40E_GLPCI_NPQ_CFG_SMALL_TO_SHIFT) 4156#define I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT 2 4157#define I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_WEIGHT_AVG_SHIFT) 4158#define I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT 6 4159#define I40E_GLPCI_NPQ_CFG_NPQ_SPARE_MASK I40E_MASK(0x3FF, I40E_GLPCI_NPQ_CFG_NPQ_SPARE_SHIFT) 4160#define I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT 16 4161#define I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_MASK I40E_MASK(0xF, I40E_GLPCI_NPQ_CFG_NPQ_ERR_STAT_SHIFT) 4162#define I40E_GLPCI_WATMK_CLNT_PIPEMON 0x0009CA30 /* Reset: PCIR */ 4163#define I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT 0 4164#define I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_SHIFT) 4165#define I40E_GLPCI_WATMK_MNG_ALWD 0x0009CB14 /* Reset: PCIR */ 4166#define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT 0 4167#define I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_DATA_LINES_SHIFT) 4168#define I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT 16 4169#define I40E_GLPCI_WATMK_MNG_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_MNG_ALWD_OSR_SHIFT) 4170#define I40E_GLPCI_WATMK_PMAT_ALWD 0x0009CB10 /* Reset: PCIR */ 4171#define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT 0 4172#define I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_DATA_LINES_SHIFT) 4173#define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT 16 4174#define I40E_GLPCI_WATMK_PMAT_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_PMAT_ALWD_OSR_SHIFT) 4175#define I40E_GLPCI_WATMK_RLAN_ALWD 0x0009CB00 /* Reset: PCIR */ 4176#define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT 0 4177#define I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_DATA_LINES_SHIFT) 4178#define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT 16 4179#define I40E_GLPCI_WATMK_RLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RLAN_ALWD_OSR_SHIFT) 4180#define I40E_GLPCI_WATMK_RXPE_ALWD 0x0009CB08 /* Reset: PCIR */ 4181#define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT 0 4182#define I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_DATA_LINES_SHIFT) 4183#define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT 16 4184#define I40E_GLPCI_WATMK_RXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_RXPE_ALWD_OSR_SHIFT) 4185#define I40E_GLPCI_WATMK_TLAN_ALWD 0x0009CB04 /* Reset: PCIR */ 4186#define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT 0 4187#define I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_DATA_LINES_SHIFT) 4188#define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT 16 4189#define I40E_GLPCI_WATMK_TLAN_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TLAN_ALWD_OSR_SHIFT) 4190#define I40E_GLPCI_WATMK_TPDU_ALWD 0x0009CB18 /* Reset: PCIR */ 4191#define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT 0 4192#define I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_DATA_LINES_SHIFT) 4193#define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT 16 4194#define I40E_GLPCI_WATMK_TPDU_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TPDU_ALWD_OSR_SHIFT) 4195#define I40E_GLPCI_WATMK_TXPE_ALWD 0x0009CB0c /* Reset: PCIR */ 4196#define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT 0 4197#define I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_DATA_LINES_SHIFT) 4198#define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT 16 4199#define I40E_GLPCI_WATMK_TXPE_ALWD_OSR_MASK I40E_MASK(0xFFFF, I40E_GLPCI_WATMK_TXPE_ALWD_OSR_SHIFT) 4200#define I40E_GLPE_CPUSTATUS0 0x0000D040 /* Reset: PE_CORER */ 4201#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT 0 4202#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT) 4203#define I40E_GLPE_CPUSTATUS1 0x0000D044 /* Reset: PE_CORER */ 4204#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT 0 4205#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT) 4206#define I40E_GLPE_CPUSTATUS2 0x0000D048 /* Reset: PE_CORER */ 4207#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT 0 4208#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT) 4209#define I40E_GLPE_CPUTRIG0 0x0000D060 /* Reset: PE_CORER */ 4210#define I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT 0 4211#define I40E_GLPE_CPUTRIG0_PECPUTRIG0_MASK I40E_MASK(0xFFFF, I40E_GLPE_CPUTRIG0_PECPUTRIG0_SHIFT) 4212#define I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT 17 4213#define I40E_GLPE_CPUTRIG0_TEPREQUEST0_MASK I40E_MASK(0x1, I40E_GLPE_CPUTRIG0_TEPREQUEST0_SHIFT) 4214#define I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT 18 4215#define I40E_GLPE_CPUTRIG0_OOPREQUEST0_MASK I40E_MASK(0x1, I40E_GLPE_CPUTRIG0_OOPREQUEST0_SHIFT) 4216#define I40E_GLPE_DUAL40_RUPM 0x0000DA04 /* Reset: PE_CORER */ 4217#define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT 0 4218#define I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_MASK I40E_MASK(0x1, I40E_GLPE_DUAL40_RUPM_DUAL_40G_MODE_SHIFT) 4219#define I40E_GLPE_PFAEQEDROPCNT(_i) (0x00131440 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 4220#define I40E_GLPE_PFAEQEDROPCNT_MAX_INDEX 15 4221#define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0 4222#define I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFAEQEDROPCNT_AEQEDROPCNT_SHIFT) 4223#define I40E_GLPE_PFCEQEDROPCNT(_i) (0x001313C0 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 4224#define I40E_GLPE_PFCEQEDROPCNT_MAX_INDEX 15 4225#define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0 4226#define I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCEQEDROPCNT_CEQEDROPCNT_SHIFT) 4227#define I40E_GLPE_PFCQEDROPCNT(_i) (0x00131340 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 4228#define I40E_GLPE_PFCQEDROPCNT_MAX_INDEX 15 4229#define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT 0 4230#define I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_PFCQEDROPCNT_CQEDROPCNT_SHIFT) 4231#define I40E_GLPE_RUPM_CQPPOOL 0x0000DACC /* Reset: PE_CORER */ 4232#define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT 0 4233#define I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_CQPPOOL_CQPSPADS_SHIFT) 4234#define I40E_GLPE_RUPM_FLRPOOL 0x0000DAC4 /* Reset: PE_CORER */ 4235#define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT 0 4236#define I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_FLRPOOL_FLRSPADS_SHIFT) 4237#define I40E_GLPE_RUPM_GCTL 0x0000DA00 /* Reset: PE_CORER */ 4238#define I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT 0 4239#define I40E_GLPE_RUPM_GCTL_ALLOFFTH_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_GCTL_ALLOFFTH_SHIFT) 4240#define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT 26 4241#define I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P0_DIS_SHIFT) 4242#define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT 27 4243#define I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P1_DIS_SHIFT) 4244#define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT 28 4245#define I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P2_DIS_SHIFT) 4246#define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT 29 4247#define I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_P3_DIS_SHIFT) 4248#define I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT 30 4249#define I40E_GLPE_RUPM_GCTL_RUPM_DIS_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_RUPM_DIS_SHIFT) 4250#define I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT 31 4251#define I40E_GLPE_RUPM_GCTL_SWLB_MODE_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_GCTL_SWLB_MODE_SHIFT) 4252#define I40E_GLPE_RUPM_PTXPOOL 0x0000DAC8 /* Reset: PE_CORER */ 4253#define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT 0 4254#define I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PTXPOOL_PTXSPADS_SHIFT) 4255#define I40E_GLPE_RUPM_PUSHPOOL 0x0000DAC0 /* Reset: PE_CORER */ 4256#define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT 0 4257#define I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_MASK I40E_MASK(0xFF, I40E_GLPE_RUPM_PUSHPOOL_PUSHSPADS_SHIFT) 4258#define I40E_GLPE_RUPM_TXHOST_EN 0x0000DA08 /* Reset: PE_CORER */ 4259#define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT 0 4260#define I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_MASK I40E_MASK(0x1, I40E_GLPE_RUPM_TXHOST_EN_TXHOST_EN_SHIFT) 4261#define I40E_GLPE_VFAEQEDROPCNT(_i) (0x00132540 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 4262#define I40E_GLPE_VFAEQEDROPCNT_MAX_INDEX 31 4263#define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT 0 4264#define I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFAEQEDROPCNT_AEQEDROPCNT_SHIFT) 4265#define I40E_GLPE_VFCEQEDROPCNT(_i) (0x00132440 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 4266#define I40E_GLPE_VFCEQEDROPCNT_MAX_INDEX 31 4267#define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT 0 4268#define I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCEQEDROPCNT_CEQEDROPCNT_SHIFT) 4269#define I40E_GLPE_VFCQEDROPCNT(_i) (0x00132340 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ 4270#define I40E_GLPE_VFCQEDROPCNT_MAX_INDEX 31 4271#define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT 0 4272#define I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFCQEDROPCNT_CQEDROPCNT_SHIFT) 4273#define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4274#define I40E_GLPE_VFFLMOBJCTRL_MAX_INDEX 31 4275#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0 4276#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT) 4277#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8 4278#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK I40E_MASK(0x7, I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT) 4279#define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4280#define I40E_GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31 4281#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0 4282#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT) 4283#define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4284#define I40E_GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31 4285#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT 0 4286#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT) 4287#define I40E_GLPE_VFUDACTRL(_i) (0x0000C000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4288#define I40E_GLPE_VFUDACTRL_MAX_INDEX 31 4289#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT 0 4290#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT) 4291#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT 1 4292#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT) 4293#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT 2 4294#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT) 4295#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT 3 4296#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT) 4297#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT 4 4298#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1, I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT) 4299#define I40E_GLPE_VFUDAUCFBQPN(_i) (0x0000C100 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4300#define I40E_GLPE_VFUDAUCFBQPN_MAX_INDEX 31 4301#define I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT 0 4302#define I40E_GLPE_VFUDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT) 4303#define I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT 31 4304#define I40E_GLPE_VFUDAUCFBQPN_VALID_MASK I40E_MASK(0x1, I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT) 4305#define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */ 4306#define I40E_PFPE_AEQALLOC_AECOUNT_SHIFT 0 4307#define I40E_PFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_AEQALLOC_AECOUNT_SHIFT) 4308#define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */ 4309#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0 4310#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT) 4311#define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */ 4312#define I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT 0 4313#define I40E_PFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT) 4314#define I40E_PFPE_CCQPSTATUS 0x00008100 /* Reset: PFR */ 4315#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0 4316#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1, I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT) 4317#define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4 4318#define I40E_PFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_PFPE_CCQPSTATUS_HMC_PROFILE_SHIFT) 4319#define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16 4320#define I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_PFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT) 4321#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31 4322#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1, I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT) 4323#define I40E_PFPE_CQACK 0x00131100 /* Reset: PFR */ 4324#define I40E_PFPE_CQACK_PECQID_SHIFT 0 4325#define I40E_PFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQACK_PECQID_SHIFT) 4326#define I40E_PFPE_CQARM 0x00131080 /* Reset: PFR */ 4327#define I40E_PFPE_CQARM_PECQID_SHIFT 0 4328#define I40E_PFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_PFPE_CQARM_PECQID_SHIFT) 4329#define I40E_PFPE_CQPDB 0x00008000 /* Reset: PFR */ 4330#define I40E_PFPE_CQPDB_WQHEAD_SHIFT 0 4331#define I40E_PFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPDB_WQHEAD_SHIFT) 4332#define I40E_PFPE_CQPERRCODES 0x00008880 /* Reset: PFR */ 4333#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0 4334#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT) 4335#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16 4336#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT) 4337#define I40E_PFPE_CQPTAIL 0x00008080 /* Reset: PFR */ 4338#define I40E_PFPE_CQPTAIL_WQTAIL_SHIFT 0 4339#define I40E_PFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_PFPE_CQPTAIL_WQTAIL_SHIFT) 4340#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31 4341#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT) 4342#define I40E_PFPE_FLMQ1ALLOCERR 0x00008980 /* Reset: PFR */ 4343#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0 4344#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT) 4345#define I40E_PFPE_FLMXMITALLOCERR 0x00008900 /* Reset: PFR */ 4346#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT 0 4347#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK I40E_MASK(0xFFFF, I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT) 4348#define I40E_PFPE_IPCONFIG0 0x00008280 /* Reset: PFR */ 4349#define I40E_PFPE_IPCONFIG0_PEIPID_SHIFT 0 4350#define I40E_PFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_PFPE_IPCONFIG0_PEIPID_SHIFT) 4351#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16 4352#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT) 4353#define I40E_PFPE_MRTEIDXMASK 0x00008600 /* Reset: PFR */ 4354#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0 4355#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT) 4356#define I40E_PFPE_RCVUNEXPECTEDERROR 0x00008680 /* Reset: PFR */ 4357#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0 4358#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT) 4359#define I40E_PFPE_TCPNOWTIMER 0x00008580 /* Reset: PFR */ 4360#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0 4361#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT) 4362#define I40E_PFPE_UDACTRL 0x00008700 /* Reset: PFR */ 4363#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT 0 4364#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT) 4365#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT 1 4366#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT) 4367#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT 2 4368#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT) 4369#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT 3 4370#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT) 4371#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT 4 4372#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_MASK I40E_MASK(0x1, I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT) 4373#define I40E_PFPE_UDAUCFBQPN 0x00008780 /* Reset: PFR */ 4374#define I40E_PFPE_UDAUCFBQPN_QPN_SHIFT 0 4375#define I40E_PFPE_UDAUCFBQPN_QPN_MASK I40E_MASK(0x3FFFF, I40E_PFPE_UDAUCFBQPN_QPN_SHIFT) 4376#define I40E_PFPE_UDAUCFBQPN_VALID_SHIFT 31 4377#define I40E_PFPE_UDAUCFBQPN_VALID_MASK I40E_MASK(0x1, I40E_PFPE_UDAUCFBQPN_VALID_SHIFT) 4378#define I40E_PFPE_WQEALLOC 0x00138C00 /* Reset: PFR */ 4379#define I40E_PFPE_WQEALLOC_PEQPID_SHIFT 0 4380#define I40E_PFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_PFPE_WQEALLOC_PEQPID_SHIFT) 4381#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20 4382#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT) 4383#define I40E_PRTDCB_RLPMC 0x0001F140 /* Reset: PE_CORER */ 4384#define I40E_PRTDCB_RLPMC_TC2PFC_SHIFT 0 4385#define I40E_PRTDCB_RLPMC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RLPMC_TC2PFC_SHIFT) 4386#define I40E_PRTDCB_TCMSTC_RLPM(_i) (0x0001F040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: PE_CORER */ 4387#define I40E_PRTDCB_TCMSTC_RLPM_MAX_INDEX 7 4388#define I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT 0 4389#define I40E_PRTDCB_TCMSTC_RLPM_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_RLPM_MSTC_SHIFT) 4390#define I40E_PRTDCB_TCPMC_RLPM 0x0001F1A0 /* Reset: PE_CORER */ 4391#define I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT 0 4392#define I40E_PRTDCB_TCPMC_RLPM_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_RLPM_CPM_SHIFT) 4393#define I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT 13 4394#define I40E_PRTDCB_TCPMC_RLPM_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_RLPM_LLTC_SHIFT) 4395#define I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT 30 4396#define I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_RLPM_TCPM_MODE_SHIFT) 4397#define I40E_PRTE_RUPM_TCCNTR03 0x0000DAE0 /* Reset: PE_CORER */ 4398#define I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT 0 4399#define I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC0COUNT_SHIFT) 4400#define I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT 8 4401#define I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC1COUNT_SHIFT) 4402#define I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT 16 4403#define I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC2COUNT_SHIFT) 4404#define I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT 24 4405#define I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTE_RUPM_TCCNTR03_TC3COUNT_SHIFT) 4406#define I40E_PRTPE_RUPM_CNTR 0x0000DB20 /* Reset: PE_CORER */ 4407#define I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT 0 4408#define I40E_PRTPE_RUPM_CNTR_COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CNTR_COUNT_SHIFT) 4409#define I40E_PRTPE_RUPM_CTL 0x0000DA40 /* Reset: PE_CORER */ 4410#define I40E_PRTPE_RUPM_CTL_LLTC_SHIFT 13 4411#define I40E_PRTPE_RUPM_CTL_LLTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_CTL_LLTC_SHIFT) 4412#define I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT 30 4413#define I40E_PRTPE_RUPM_CTL_RUPM_MODE_MASK I40E_MASK(0x1, I40E_PRTPE_RUPM_CTL_RUPM_MODE_SHIFT) 4414#define I40E_PRTPE_RUPM_PFCCTL 0x0000DA60 /* Reset: PE_CORER */ 4415#define I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT 0 4416#define I40E_PRTPE_RUPM_PFCCTL_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCCTL_TC2PFC_SHIFT) 4417#define I40E_PRTPE_RUPM_PFCPC 0x0000DA80 /* Reset: PE_CORER */ 4418#define I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT 0 4419#define I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCPC_PORTOFFTH_SHIFT) 4420#define I40E_PRTPE_RUPM_PFCTCC 0x0000DAA0 /* Reset: PE_CORER */ 4421#define I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT 0 4422#define I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_TCOFFTH_SHIFT) 4423#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT 16 4424#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_TH_SHIFT) 4425#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT 31 4426#define I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_MASK I40E_MASK(0x1, I40E_PRTPE_RUPM_PFCTCC_LL_PRI_EN_SHIFT) 4427#define I40E_PRTPE_RUPM_PTCTCCNTR47 0x0000DB60 /* Reset: PE_CORER */ 4428#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT 0 4429#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC4COUNT_SHIFT) 4430#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT 8 4431#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC5COUNT_SHIFT) 4432#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT 16 4433#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC6COUNT_SHIFT) 4434#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT 24 4435#define I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTCTCCNTR47_TC7COUNT_SHIFT) 4436#define I40E_PRTPE_RUPM_PTXTCCNTR03 0x0000DB40 /* Reset: PE_CORER */ 4437#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT 0 4438#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC0COUNT_SHIFT) 4439#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT 8 4440#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC1COUNT_SHIFT) 4441#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT 16 4442#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC2COUNT_SHIFT) 4443#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT 24 4444#define I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_PTXTCCNTR03_TC3COUNT_SHIFT) 4445#define I40E_PRTPE_RUPM_TCCNTR47 0x0000DB00 /* Reset: PE_CORER */ 4446#define I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT 0 4447#define I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC4COUNT_SHIFT) 4448#define I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT 8 4449#define I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC5COUNT_SHIFT) 4450#define I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT 16 4451#define I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC6COUNT_SHIFT) 4452#define I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT 24 4453#define I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_TCCNTR47_TC7COUNT_SHIFT) 4454#define I40E_PRTPE_RUPM_THRES 0x0000DA20 /* Reset: PE_CORER */ 4455#define I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT 0 4456#define I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MINSPADSPERTC_SHIFT) 4457#define I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT 8 4458#define I40E_PRTPE_RUPM_THRES_MAXSPADS_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADS_SHIFT) 4459#define I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT 16 4460#define I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_MASK I40E_MASK(0xFF, I40E_PRTPE_RUPM_THRES_MAXSPADSPERTC_SHIFT) 4461#define I40E_VFPE_AEQALLOC(_VF) (0x00130C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4462#define I40E_VFPE_AEQALLOC_MAX_INDEX 127 4463#define I40E_VFPE_AEQALLOC_AECOUNT_SHIFT 0 4464#define I40E_VFPE_AEQALLOC_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC_AECOUNT_SHIFT) 4465#define I40E_VFPE_CCQPHIGH(_VF) (0x00001000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4466#define I40E_VFPE_CCQPHIGH_MAX_INDEX 127 4467#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0 4468#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT) 4469#define I40E_VFPE_CCQPLOW(_VF) (0x00000C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4470#define I40E_VFPE_CCQPLOW_MAX_INDEX 127 4471#define I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT 0 4472#define I40E_VFPE_CCQPLOW_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT) 4473#define I40E_VFPE_CCQPSTATUS(_VF) (0x00000800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4474#define I40E_VFPE_CCQPSTATUS_MAX_INDEX 127 4475#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0 4476#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT) 4477#define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT 4 4478#define I40E_VFPE_CCQPSTATUS_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS_HMC_PROFILE_SHIFT) 4479#define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT 16 4480#define I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS_RDMA_EN_VFS_SHIFT) 4481#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31 4482#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT) 4483#define I40E_VFPE_CQACK(_VF) (0x00130800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4484#define I40E_VFPE_CQACK_MAX_INDEX 127 4485#define I40E_VFPE_CQACK_PECQID_SHIFT 0 4486#define I40E_VFPE_CQACK_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK_PECQID_SHIFT) 4487#define I40E_VFPE_CQARM(_VF) (0x00130400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4488#define I40E_VFPE_CQARM_MAX_INDEX 127 4489#define I40E_VFPE_CQARM_PECQID_SHIFT 0 4490#define I40E_VFPE_CQARM_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM_PECQID_SHIFT) 4491#define I40E_VFPE_CQPDB(_VF) (0x00000000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4492#define I40E_VFPE_CQPDB_MAX_INDEX 127 4493#define I40E_VFPE_CQPDB_WQHEAD_SHIFT 0 4494#define I40E_VFPE_CQPDB_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB_WQHEAD_SHIFT) 4495#define I40E_VFPE_CQPERRCODES(_VF) (0x00001800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4496#define I40E_VFPE_CQPERRCODES_MAX_INDEX 127 4497#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0 4498#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT) 4499#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16 4500#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT) 4501#define I40E_VFPE_CQPTAIL(_VF) (0x00000400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4502#define I40E_VFPE_CQPTAIL_MAX_INDEX 127 4503#define I40E_VFPE_CQPTAIL_WQTAIL_SHIFT 0 4504#define I40E_VFPE_CQPTAIL_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL_WQTAIL_SHIFT) 4505#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31 4506#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT) 4507#define I40E_VFPE_IPCONFIG0(_VF) (0x00001400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4508#define I40E_VFPE_IPCONFIG0_MAX_INDEX 127 4509#define I40E_VFPE_IPCONFIG0_PEIPID_SHIFT 0 4510#define I40E_VFPE_IPCONFIG0_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG0_PEIPID_SHIFT) 4511#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16 4512#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT) 4513#define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4514#define I40E_VFPE_MRTEIDXMASK_MAX_INDEX 127 4515#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0 4516#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT) 4517#define I40E_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00003400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4518#define I40E_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 127 4519#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0 4520#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT) 4521#define I40E_VFPE_TCPNOWTIMER(_VF) (0x00002C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4522#define I40E_VFPE_TCPNOWTIMER_MAX_INDEX 127 4523#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0 4524#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT) 4525#define I40E_VFPE_WQEALLOC(_VF) (0x00138000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 4526#define I40E_VFPE_WQEALLOC_MAX_INDEX 127 4527#define I40E_VFPE_WQEALLOC_PEQPID_SHIFT 0 4528#define I40E_VFPE_WQEALLOC_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC_PEQPID_SHIFT) 4529#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20 4530#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT) 4531#define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4532#define I40E_GLPES_PFIP4RXDISCARD_MAX_INDEX 15 4533#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0 4534#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT) 4535#define I40E_GLPES_PFIP4RXFRAGSHI(_i) (0x00010804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4536#define I40E_GLPES_PFIP4RXFRAGSHI_MAX_INDEX 15 4537#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0 4538#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT) 4539#define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4540#define I40E_GLPES_PFIP4RXFRAGSLO_MAX_INDEX 15 4541#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0 4542#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT) 4543#define I40E_GLPES_PFIP4RXMCOCTSHI(_i) (0x00010A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4544#define I40E_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 15 4545#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0 4546#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT) 4547#define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4548#define I40E_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 15 4549#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0 4550#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT) 4551#define I40E_GLPES_PFIP4RXMCPKTSHI(_i) (0x00010C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4552#define I40E_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 15 4553#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0 4554#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT) 4555#define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4556#define I40E_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 15 4557#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0 4558#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT) 4559#define I40E_GLPES_PFIP4RXOCTSHI(_i) (0x00010204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4560#define I40E_GLPES_PFIP4RXOCTSHI_MAX_INDEX 15 4561#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0 4562#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT) 4563#define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4564#define I40E_GLPES_PFIP4RXOCTSLO_MAX_INDEX 15 4565#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0 4566#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT) 4567#define I40E_GLPES_PFIP4RXPKTSHI(_i) (0x00010404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4568#define I40E_GLPES_PFIP4RXPKTSHI_MAX_INDEX 15 4569#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0 4570#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT) 4571#define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4572#define I40E_GLPES_PFIP4RXPKTSLO_MAX_INDEX 15 4573#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0 4574#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT) 4575#define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4576#define I40E_GLPES_PFIP4RXTRUNC_MAX_INDEX 15 4577#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0 4578#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT) 4579#define I40E_GLPES_PFIP4TXFRAGSHI(_i) (0x00011E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4580#define I40E_GLPES_PFIP4TXFRAGSHI_MAX_INDEX 15 4581#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0 4582#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT) 4583#define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4584#define I40E_GLPES_PFIP4TXFRAGSLO_MAX_INDEX 15 4585#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0 4586#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT) 4587#define I40E_GLPES_PFIP4TXMCOCTSHI(_i) (0x00012004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4588#define I40E_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 15 4589#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0 4590#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT) 4591#define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4592#define I40E_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 15 4593#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0 4594#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT) 4595#define I40E_GLPES_PFIP4TXMCPKTSHI(_i) (0x00012204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4596#define I40E_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 15 4597#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0 4598#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT) 4599#define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4600#define I40E_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 15 4601#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0 4602#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT) 4603#define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4604#define I40E_GLPES_PFIP4TXNOROUTE_MAX_INDEX 15 4605#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0 4606#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT) 4607#define I40E_GLPES_PFIP4TXOCTSHI(_i) (0x00011A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4608#define I40E_GLPES_PFIP4TXOCTSHI_MAX_INDEX 15 4609#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0 4610#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT) 4611#define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4612#define I40E_GLPES_PFIP4TXOCTSLO_MAX_INDEX 15 4613#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0 4614#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT) 4615#define I40E_GLPES_PFIP4TXPKTSHI(_i) (0x00011C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4616#define I40E_GLPES_PFIP4TXPKTSHI_MAX_INDEX 15 4617#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0 4618#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT) 4619#define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4620#define I40E_GLPES_PFIP4TXPKTSLO_MAX_INDEX 15 4621#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0 4622#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT) 4623#define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4624#define I40E_GLPES_PFIP6RXDISCARD_MAX_INDEX 15 4625#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0 4626#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT) 4627#define I40E_GLPES_PFIP6RXFRAGSHI(_i) (0x00011404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4628#define I40E_GLPES_PFIP6RXFRAGSHI_MAX_INDEX 15 4629#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0 4630#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT) 4631#define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4632#define I40E_GLPES_PFIP6RXFRAGSLO_MAX_INDEX 15 4633#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0 4634#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT) 4635#define I40E_GLPES_PFIP6RXMCOCTSHI(_i) (0x00011604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4636#define I40E_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 15 4637#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0 4638#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT) 4639#define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4640#define I40E_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 15 4641#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0 4642#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT) 4643#define I40E_GLPES_PFIP6RXMCPKTSHI(_i) (0x00011804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4644#define I40E_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 15 4645#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0 4646#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT) 4647#define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4648#define I40E_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 15 4649#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0 4650#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT) 4651#define I40E_GLPES_PFIP6RXOCTSHI(_i) (0x00010E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4652#define I40E_GLPES_PFIP6RXOCTSHI_MAX_INDEX 15 4653#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0 4654#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT) 4655#define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4656#define I40E_GLPES_PFIP6RXOCTSLO_MAX_INDEX 15 4657#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0 4658#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT) 4659#define I40E_GLPES_PFIP6RXPKTSHI(_i) (0x00011004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4660#define I40E_GLPES_PFIP6RXPKTSHI_MAX_INDEX 15 4661#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0 4662#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT) 4663#define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4664#define I40E_GLPES_PFIP6RXPKTSLO_MAX_INDEX 15 4665#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0 4666#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT) 4667#define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4668#define I40E_GLPES_PFIP6RXTRUNC_MAX_INDEX 15 4669#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0 4670#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT) 4671#define I40E_GLPES_PFIP6TXFRAGSHI(_i) (0x00012804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4672#define I40E_GLPES_PFIP6TXFRAGSHI_MAX_INDEX 15 4673#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0 4674#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT) 4675#define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4676#define I40E_GLPES_PFIP6TXFRAGSLO_MAX_INDEX 15 4677#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0 4678#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT) 4679#define I40E_GLPES_PFIP6TXMCOCTSHI(_i) (0x00012A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4680#define I40E_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 15 4681#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0 4682#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT) 4683#define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4684#define I40E_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 15 4685#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0 4686#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT) 4687#define I40E_GLPES_PFIP6TXMCPKTSHI(_i) (0x00012C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4688#define I40E_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 15 4689#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0 4690#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT) 4691#define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4692#define I40E_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 15 4693#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0 4694#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT) 4695#define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4696#define I40E_GLPES_PFIP6TXNOROUTE_MAX_INDEX 15 4697#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0 4698#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT) 4699#define I40E_GLPES_PFIP6TXOCTSHI(_i) (0x00012404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4700#define I40E_GLPES_PFIP6TXOCTSHI_MAX_INDEX 15 4701#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0 4702#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT) 4703#define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4704#define I40E_GLPES_PFIP6TXOCTSLO_MAX_INDEX 15 4705#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0 4706#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT) 4707#define I40E_GLPES_PFIP6TXPKTSHI(_i) (0x00012604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4708#define I40E_GLPES_PFIP6TXPKTSHI_MAX_INDEX 15 4709#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0 4710#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT) 4711#define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4712#define I40E_GLPES_PFIP6TXPKTSLO_MAX_INDEX 15 4713#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0 4714#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT) 4715#define I40E_GLPES_PFRDMARXRDSHI(_i) (0x00013E04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4716#define I40E_GLPES_PFRDMARXRDSHI_MAX_INDEX 15 4717#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0 4718#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT) 4719#define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4720#define I40E_GLPES_PFRDMARXRDSLO_MAX_INDEX 15 4721#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0 4722#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT) 4723#define I40E_GLPES_PFRDMARXSNDSHI(_i) (0x00014004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4724#define I40E_GLPES_PFRDMARXSNDSHI_MAX_INDEX 15 4725#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0 4726#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT) 4727#define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4728#define I40E_GLPES_PFRDMARXSNDSLO_MAX_INDEX 15 4729#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0 4730#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT) 4731#define I40E_GLPES_PFRDMARXWRSHI(_i) (0x00013C04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4732#define I40E_GLPES_PFRDMARXWRSHI_MAX_INDEX 15 4733#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0 4734#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT) 4735#define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4736#define I40E_GLPES_PFRDMARXWRSLO_MAX_INDEX 15 4737#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0 4738#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT) 4739#define I40E_GLPES_PFRDMATXRDSHI(_i) (0x00014404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4740#define I40E_GLPES_PFRDMATXRDSHI_MAX_INDEX 15 4741#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0 4742#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT) 4743#define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4744#define I40E_GLPES_PFRDMATXRDSLO_MAX_INDEX 15 4745#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0 4746#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT) 4747#define I40E_GLPES_PFRDMATXSNDSHI(_i) (0x00014604 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4748#define I40E_GLPES_PFRDMATXSNDSHI_MAX_INDEX 15 4749#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0 4750#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT) 4751#define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4752#define I40E_GLPES_PFRDMATXSNDSLO_MAX_INDEX 15 4753#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0 4754#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT) 4755#define I40E_GLPES_PFRDMATXWRSHI(_i) (0x00014204 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4756#define I40E_GLPES_PFRDMATXWRSHI_MAX_INDEX 15 4757#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0 4758#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT) 4759#define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4760#define I40E_GLPES_PFRDMATXWRSLO_MAX_INDEX 15 4761#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0 4762#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT) 4763#define I40E_GLPES_PFRDMAVBNDHI(_i) (0x00014804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4764#define I40E_GLPES_PFRDMAVBNDHI_MAX_INDEX 15 4765#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0 4766#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT) 4767#define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4768#define I40E_GLPES_PFRDMAVBNDLO_MAX_INDEX 15 4769#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0 4770#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT) 4771#define I40E_GLPES_PFRDMAVINVHI(_i) (0x00014A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4772#define I40E_GLPES_PFRDMAVINVHI_MAX_INDEX 15 4773#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT 0 4774#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT) 4775#define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4776#define I40E_GLPES_PFRDMAVINVLO_MAX_INDEX 15 4777#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT 0 4778#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT) 4779#define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4780#define I40E_GLPES_PFRXVLANERR_MAX_INDEX 15 4781#define I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT 0 4782#define I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT) 4783#define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4784#define I40E_GLPES_PFTCPRTXSEG_MAX_INDEX 15 4785#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT 0 4786#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT) 4787#define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4788#define I40E_GLPES_PFTCPRXOPTERR_MAX_INDEX 15 4789#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0 4790#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT) 4791#define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ 4792#define I40E_GLPES_PFTCPRXPROTOERR_MAX_INDEX 15 4793#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0 4794#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT) 4795#define I40E_GLPES_PFTCPRXSEGSHI(_i) (0x00013004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4796#define I40E_GLPES_PFTCPRXSEGSHI_MAX_INDEX 15 4797#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0 4798#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT) 4799#define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4800#define I40E_GLPES_PFTCPRXSEGSLO_MAX_INDEX 15 4801#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0 4802#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT) 4803#define I40E_GLPES_PFTCPTXSEGHI(_i) (0x00013404 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4804#define I40E_GLPES_PFTCPTXSEGHI_MAX_INDEX 15 4805#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0 4806#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT) 4807#define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4808#define I40E_GLPES_PFTCPTXSEGLO_MAX_INDEX 15 4809#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0 4810#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT) 4811#define I40E_GLPES_PFUDPRXPKTSHI(_i) (0x00013804 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4812#define I40E_GLPES_PFUDPRXPKTSHI_MAX_INDEX 15 4813#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0 4814#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT) 4815#define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4816#define I40E_GLPES_PFUDPRXPKTSLO_MAX_INDEX 15 4817#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0 4818#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT) 4819#define I40E_GLPES_PFUDPTXPKTSHI(_i) (0x00013A04 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4820#define I40E_GLPES_PFUDPTXPKTSHI_MAX_INDEX 15 4821#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0 4822#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT) 4823#define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ 4824#define I40E_GLPES_PFUDPTXPKTSLO_MAX_INDEX 15 4825#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0 4826#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT) 4827#define I40E_GLPES_RDMARXMULTFPDUSHI 0x0001E014 /* Reset: PE_CORER */ 4828#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT 0 4829#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT) 4830#define I40E_GLPES_RDMARXMULTFPDUSLO 0x0001E010 /* Reset: PE_CORER */ 4831#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT 0 4832#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT) 4833#define I40E_GLPES_RDMARXOOODDPHI 0x0001E01C /* Reset: PE_CORER */ 4834#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT 0 4835#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT) 4836#define I40E_GLPES_RDMARXOOODDPLO 0x0001E018 /* Reset: PE_CORER */ 4837#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT 0 4838#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT) 4839#define I40E_GLPES_RDMARXOOONOMARK 0x0001E004 /* Reset: PE_CORER */ 4840#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT 0 4841#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT) 4842#define I40E_GLPES_RDMARXUNALIGN 0x0001E000 /* Reset: PE_CORER */ 4843#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT 0 4844#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT) 4845#define I40E_GLPES_TCPRXFOURHOLEHI 0x0001E044 /* Reset: PE_CORER */ 4846#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT 0 4847#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT) 4848#define I40E_GLPES_TCPRXFOURHOLELO 0x0001E040 /* Reset: PE_CORER */ 4849#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT 0 4850#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT) 4851#define I40E_GLPES_TCPRXONEHOLEHI 0x0001E02C /* Reset: PE_CORER */ 4852#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT 0 4853#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT) 4854#define I40E_GLPES_TCPRXONEHOLELO 0x0001E028 /* Reset: PE_CORER */ 4855#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT 0 4856#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT) 4857#define I40E_GLPES_TCPRXPUREACKHI 0x0001E024 /* Reset: PE_CORER */ 4858#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT 0 4859#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT) 4860#define I40E_GLPES_TCPRXPUREACKSLO 0x0001E020 /* Reset: PE_CORER */ 4861#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT 0 4862#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT) 4863#define I40E_GLPES_TCPRXTHREEHOLEHI 0x0001E03C /* Reset: PE_CORER */ 4864#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT 0 4865#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT) 4866#define I40E_GLPES_TCPRXTHREEHOLELO 0x0001E038 /* Reset: PE_CORER */ 4867#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT 0 4868#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT) 4869#define I40E_GLPES_TCPRXTWOHOLEHI 0x0001E034 /* Reset: PE_CORER */ 4870#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT 0 4871#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT) 4872#define I40E_GLPES_TCPRXTWOHOLELO 0x0001E030 /* Reset: PE_CORER */ 4873#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT 0 4874#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT) 4875#define I40E_GLPES_TCPTXRETRANSFASTHI 0x0001E04C /* Reset: PE_CORER */ 4876#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT 0 4877#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT) 4878#define I40E_GLPES_TCPTXRETRANSFASTLO 0x0001E048 /* Reset: PE_CORER */ 4879#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT 0 4880#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT) 4881#define I40E_GLPES_TCPTXTOUTSFASTHI 0x0001E054 /* Reset: PE_CORER */ 4882#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT 0 4883#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT) 4884#define I40E_GLPES_TCPTXTOUTSFASTLO 0x0001E050 /* Reset: PE_CORER */ 4885#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT 0 4886#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT) 4887#define I40E_GLPES_TCPTXTOUTSHI 0x0001E05C /* Reset: PE_CORER */ 4888#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT 0 4889#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT) 4890#define I40E_GLPES_TCPTXTOUTSLO 0x0001E058 /* Reset: PE_CORER */ 4891#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT 0 4892#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT) 4893#define I40E_GLPES_VFIP4RXDISCARD(_i) (0x00018600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4894#define I40E_GLPES_VFIP4RXDISCARD_MAX_INDEX 31 4895#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0 4896#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT) 4897#define I40E_GLPES_VFIP4RXFRAGSHI(_i) (0x00018804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4898#define I40E_GLPES_VFIP4RXFRAGSHI_MAX_INDEX 31 4899#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0 4900#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT) 4901#define I40E_GLPES_VFIP4RXFRAGSLO(_i) (0x00018800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4902#define I40E_GLPES_VFIP4RXFRAGSLO_MAX_INDEX 31 4903#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0 4904#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT) 4905#define I40E_GLPES_VFIP4RXMCOCTSHI(_i) (0x00018A04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4906#define I40E_GLPES_VFIP4RXMCOCTSHI_MAX_INDEX 31 4907#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0 4908#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT) 4909#define I40E_GLPES_VFIP4RXMCOCTSLO(_i) (0x00018A00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4910#define I40E_GLPES_VFIP4RXMCOCTSLO_MAX_INDEX 31 4911#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0 4912#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT) 4913#define I40E_GLPES_VFIP4RXMCPKTSHI(_i) (0x00018C04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4914#define I40E_GLPES_VFIP4RXMCPKTSHI_MAX_INDEX 31 4915#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0 4916#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT) 4917#define I40E_GLPES_VFIP4RXMCPKTSLO(_i) (0x00018C00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4918#define I40E_GLPES_VFIP4RXMCPKTSLO_MAX_INDEX 31 4919#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0 4920#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT) 4921#define I40E_GLPES_VFIP4RXOCTSHI(_i) (0x00018204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4922#define I40E_GLPES_VFIP4RXOCTSHI_MAX_INDEX 31 4923#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0 4924#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT) 4925#define I40E_GLPES_VFIP4RXOCTSLO(_i) (0x00018200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4926#define I40E_GLPES_VFIP4RXOCTSLO_MAX_INDEX 31 4927#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0 4928#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT) 4929#define I40E_GLPES_VFIP4RXPKTSHI(_i) (0x00018404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4930#define I40E_GLPES_VFIP4RXPKTSHI_MAX_INDEX 31 4931#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0 4932#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT) 4933#define I40E_GLPES_VFIP4RXPKTSLO(_i) (0x00018400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4934#define I40E_GLPES_VFIP4RXPKTSLO_MAX_INDEX 31 4935#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0 4936#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT) 4937#define I40E_GLPES_VFIP4RXTRUNC(_i) (0x00018700 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4938#define I40E_GLPES_VFIP4RXTRUNC_MAX_INDEX 31 4939#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0 4940#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT) 4941#define I40E_GLPES_VFIP4TXFRAGSHI(_i) (0x00019E04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4942#define I40E_GLPES_VFIP4TXFRAGSHI_MAX_INDEX 31 4943#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0 4944#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT) 4945#define I40E_GLPES_VFIP4TXFRAGSLO(_i) (0x00019E00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4946#define I40E_GLPES_VFIP4TXFRAGSLO_MAX_INDEX 31 4947#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0 4948#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT) 4949#define I40E_GLPES_VFIP4TXMCOCTSHI(_i) (0x0001A004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4950#define I40E_GLPES_VFIP4TXMCOCTSHI_MAX_INDEX 31 4951#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0 4952#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT) 4953#define I40E_GLPES_VFIP4TXMCOCTSLO(_i) (0x0001A000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4954#define I40E_GLPES_VFIP4TXMCOCTSLO_MAX_INDEX 31 4955#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0 4956#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT) 4957#define I40E_GLPES_VFIP4TXMCPKTSHI(_i) (0x0001A204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4958#define I40E_GLPES_VFIP4TXMCPKTSHI_MAX_INDEX 31 4959#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0 4960#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT) 4961#define I40E_GLPES_VFIP4TXMCPKTSLO(_i) (0x0001A200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4962#define I40E_GLPES_VFIP4TXMCPKTSLO_MAX_INDEX 31 4963#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0 4964#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT) 4965#define I40E_GLPES_VFIP4TXNOROUTE(_i) (0x0001AE00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4966#define I40E_GLPES_VFIP4TXNOROUTE_MAX_INDEX 31 4967#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0 4968#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT) 4969#define I40E_GLPES_VFIP4TXOCTSHI(_i) (0x00019A04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4970#define I40E_GLPES_VFIP4TXOCTSHI_MAX_INDEX 31 4971#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0 4972#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT) 4973#define I40E_GLPES_VFIP4TXOCTSLO(_i) (0x00019A00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4974#define I40E_GLPES_VFIP4TXOCTSLO_MAX_INDEX 31 4975#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0 4976#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT) 4977#define I40E_GLPES_VFIP4TXPKTSHI(_i) (0x00019C04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4978#define I40E_GLPES_VFIP4TXPKTSHI_MAX_INDEX 31 4979#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0 4980#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT) 4981#define I40E_GLPES_VFIP4TXPKTSLO(_i) (0x00019C00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4982#define I40E_GLPES_VFIP4TXPKTSLO_MAX_INDEX 31 4983#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0 4984#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT) 4985#define I40E_GLPES_VFIP6RXDISCARD(_i) (0x00019200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 4986#define I40E_GLPES_VFIP6RXDISCARD_MAX_INDEX 31 4987#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0 4988#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT) 4989#define I40E_GLPES_VFIP6RXFRAGSHI(_i) (0x00019404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4990#define I40E_GLPES_VFIP6RXFRAGSHI_MAX_INDEX 31 4991#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0 4992#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT) 4993#define I40E_GLPES_VFIP6RXFRAGSLO(_i) (0x00019400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4994#define I40E_GLPES_VFIP6RXFRAGSLO_MAX_INDEX 31 4995#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0 4996#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT) 4997#define I40E_GLPES_VFIP6RXMCOCTSHI(_i) (0x00019604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 4998#define I40E_GLPES_VFIP6RXMCOCTSHI_MAX_INDEX 31 4999#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0 5000#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT) 5001#define I40E_GLPES_VFIP6RXMCOCTSLO(_i) (0x00019600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5002#define I40E_GLPES_VFIP6RXMCOCTSLO_MAX_INDEX 31 5003#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0 5004#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT) 5005#define I40E_GLPES_VFIP6RXMCPKTSHI(_i) (0x00019804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5006#define I40E_GLPES_VFIP6RXMCPKTSHI_MAX_INDEX 31 5007#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0 5008#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT) 5009#define I40E_GLPES_VFIP6RXMCPKTSLO(_i) (0x00019800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5010#define I40E_GLPES_VFIP6RXMCPKTSLO_MAX_INDEX 31 5011#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0 5012#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT) 5013#define I40E_GLPES_VFIP6RXOCTSHI(_i) (0x00018E04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5014#define I40E_GLPES_VFIP6RXOCTSHI_MAX_INDEX 31 5015#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0 5016#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT) 5017#define I40E_GLPES_VFIP6RXOCTSLO(_i) (0x00018E00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5018#define I40E_GLPES_VFIP6RXOCTSLO_MAX_INDEX 31 5019#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0 5020#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT) 5021#define I40E_GLPES_VFIP6RXPKTSHI(_i) (0x00019004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5022#define I40E_GLPES_VFIP6RXPKTSHI_MAX_INDEX 31 5023#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0 5024#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT) 5025#define I40E_GLPES_VFIP6RXPKTSLO(_i) (0x00019000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5026#define I40E_GLPES_VFIP6RXPKTSLO_MAX_INDEX 31 5027#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0 5028#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT) 5029#define I40E_GLPES_VFIP6RXTRUNC(_i) (0x00019300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 5030#define I40E_GLPES_VFIP6RXTRUNC_MAX_INDEX 31 5031#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0 5032#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT) 5033#define I40E_GLPES_VFIP6TXFRAGSHI(_i) (0x0001A804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5034#define I40E_GLPES_VFIP6TXFRAGSHI_MAX_INDEX 31 5035#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0 5036#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT) 5037#define I40E_GLPES_VFIP6TXFRAGSLO(_i) (0x0001A800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5038#define I40E_GLPES_VFIP6TXFRAGSLO_MAX_INDEX 31 5039#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0 5040#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT) 5041#define I40E_GLPES_VFIP6TXMCOCTSHI(_i) (0x0001AA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5042#define I40E_GLPES_VFIP6TXMCOCTSHI_MAX_INDEX 31 5043#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0 5044#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT) 5045#define I40E_GLPES_VFIP6TXMCOCTSLO(_i) (0x0001AA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5046#define I40E_GLPES_VFIP6TXMCOCTSLO_MAX_INDEX 31 5047#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0 5048#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT) 5049#define I40E_GLPES_VFIP6TXMCPKTSHI(_i) (0x0001AC04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5050#define I40E_GLPES_VFIP6TXMCPKTSHI_MAX_INDEX 31 5051#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0 5052#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT) 5053#define I40E_GLPES_VFIP6TXMCPKTSLO(_i) (0x0001AC00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5054#define I40E_GLPES_VFIP6TXMCPKTSLO_MAX_INDEX 31 5055#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0 5056#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT) 5057#define I40E_GLPES_VFIP6TXNOROUTE(_i) (0x0001AF00 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 5058#define I40E_GLPES_VFIP6TXNOROUTE_MAX_INDEX 31 5059#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0 5060#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT) 5061#define I40E_GLPES_VFIP6TXOCTSHI(_i) (0x0001A404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5062#define I40E_GLPES_VFIP6TXOCTSHI_MAX_INDEX 31 5063#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0 5064#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT) 5065#define I40E_GLPES_VFIP6TXOCTSLO(_i) (0x0001A400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5066#define I40E_GLPES_VFIP6TXOCTSLO_MAX_INDEX 31 5067#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0 5068#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT) 5069#define I40E_GLPES_VFIP6TXPKTSHI(_i) (0x0001A604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5070#define I40E_GLPES_VFIP6TXPKTSHI_MAX_INDEX 31 5071#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0 5072#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT) 5073#define I40E_GLPES_VFIP6TXPKTSLO(_i) (0x0001A600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5074#define I40E_GLPES_VFIP6TXPKTSLO_MAX_INDEX 31 5075#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0 5076#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT) 5077#define I40E_GLPES_VFRDMARXRDSHI(_i) (0x0001BE04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5078#define I40E_GLPES_VFRDMARXRDSHI_MAX_INDEX 31 5079#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0 5080#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT) 5081#define I40E_GLPES_VFRDMARXRDSLO(_i) (0x0001BE00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5082#define I40E_GLPES_VFRDMARXRDSLO_MAX_INDEX 31 5083#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0 5084#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT) 5085#define I40E_GLPES_VFRDMARXSNDSHI(_i) (0x0001C004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5086#define I40E_GLPES_VFRDMARXSNDSHI_MAX_INDEX 31 5087#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0 5088#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT) 5089#define I40E_GLPES_VFRDMARXSNDSLO(_i) (0x0001C000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5090#define I40E_GLPES_VFRDMARXSNDSLO_MAX_INDEX 31 5091#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0 5092#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT) 5093#define I40E_GLPES_VFRDMARXWRSHI(_i) (0x0001BC04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5094#define I40E_GLPES_VFRDMARXWRSHI_MAX_INDEX 31 5095#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0 5096#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT) 5097#define I40E_GLPES_VFRDMARXWRSLO(_i) (0x0001BC00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5098#define I40E_GLPES_VFRDMARXWRSLO_MAX_INDEX 31 5099#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0 5100#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT) 5101#define I40E_GLPES_VFRDMATXRDSHI(_i) (0x0001C404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5102#define I40E_GLPES_VFRDMATXRDSHI_MAX_INDEX 31 5103#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0 5104#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT) 5105#define I40E_GLPES_VFRDMATXRDSLO(_i) (0x0001C400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5106#define I40E_GLPES_VFRDMATXRDSLO_MAX_INDEX 31 5107#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0 5108#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT) 5109#define I40E_GLPES_VFRDMATXSNDSHI(_i) (0x0001C604 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5110#define I40E_GLPES_VFRDMATXSNDSHI_MAX_INDEX 31 5111#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0 5112#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT) 5113#define I40E_GLPES_VFRDMATXSNDSLO(_i) (0x0001C600 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5114#define I40E_GLPES_VFRDMATXSNDSLO_MAX_INDEX 31 5115#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0 5116#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT) 5117#define I40E_GLPES_VFRDMATXWRSHI(_i) (0x0001C204 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5118#define I40E_GLPES_VFRDMATXWRSHI_MAX_INDEX 31 5119#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0 5120#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT) 5121#define I40E_GLPES_VFRDMATXWRSLO(_i) (0x0001C200 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5122#define I40E_GLPES_VFRDMATXWRSLO_MAX_INDEX 31 5123#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0 5124#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT) 5125#define I40E_GLPES_VFRDMAVBNDHI(_i) (0x0001C804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5126#define I40E_GLPES_VFRDMAVBNDHI_MAX_INDEX 31 5127#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0 5128#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT) 5129#define I40E_GLPES_VFRDMAVBNDLO(_i) (0x0001C800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5130#define I40E_GLPES_VFRDMAVBNDLO_MAX_INDEX 31 5131#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0 5132#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT) 5133#define I40E_GLPES_VFRDMAVINVHI(_i) (0x0001CA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5134#define I40E_GLPES_VFRDMAVINVHI_MAX_INDEX 31 5135#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT 0 5136#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT) 5137#define I40E_GLPES_VFRDMAVINVLO(_i) (0x0001CA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5138#define I40E_GLPES_VFRDMAVINVLO_MAX_INDEX 31 5139#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT 0 5140#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT) 5141#define I40E_GLPES_VFRXVLANERR(_i) (0x00018000 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 5142#define I40E_GLPES_VFRXVLANERR_MAX_INDEX 31 5143#define I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT 0 5144#define I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT) 5145#define I40E_GLPES_VFTCPRTXSEG(_i) (0x0001B600 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 5146#define I40E_GLPES_VFTCPRTXSEG_MAX_INDEX 31 5147#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT 0 5148#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT) 5149#define I40E_GLPES_VFTCPRXOPTERR(_i) (0x0001B200 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 5150#define I40E_GLPES_VFTCPRXOPTERR_MAX_INDEX 31 5151#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0 5152#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT) 5153#define I40E_GLPES_VFTCPRXPROTOERR(_i) (0x0001B300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: PE_CORER */ 5154#define I40E_GLPES_VFTCPRXPROTOERR_MAX_INDEX 31 5155#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0 5156#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK I40E_MASK(0xFFFFFF, I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT) 5157#define I40E_GLPES_VFTCPRXSEGSHI(_i) (0x0001B004 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5158#define I40E_GLPES_VFTCPRXSEGSHI_MAX_INDEX 31 5159#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0 5160#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT) 5161#define I40E_GLPES_VFTCPRXSEGSLO(_i) (0x0001B000 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5162#define I40E_GLPES_VFTCPRXSEGSLO_MAX_INDEX 31 5163#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0 5164#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT) 5165#define I40E_GLPES_VFTCPTXSEGHI(_i) (0x0001B404 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5166#define I40E_GLPES_VFTCPTXSEGHI_MAX_INDEX 31 5167#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0 5168#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT) 5169#define I40E_GLPES_VFTCPTXSEGLO(_i) (0x0001B400 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5170#define I40E_GLPES_VFTCPTXSEGLO_MAX_INDEX 31 5171#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0 5172#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT) 5173#define I40E_GLPES_VFUDPRXPKTSHI(_i) (0x0001B804 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5174#define I40E_GLPES_VFUDPRXPKTSHI_MAX_INDEX 31 5175#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0 5176#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT) 5177#define I40E_GLPES_VFUDPRXPKTSLO(_i) (0x0001B800 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5178#define I40E_GLPES_VFUDPRXPKTSLO_MAX_INDEX 31 5179#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0 5180#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT) 5181#define I40E_GLPES_VFUDPTXPKTSHI(_i) (0x0001BA04 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5182#define I40E_GLPES_VFUDPTXPKTSHI_MAX_INDEX 31 5183#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0 5184#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK I40E_MASK(0xFFFF, I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT) 5185#define I40E_GLPES_VFUDPTXPKTSLO(_i) (0x0001BA00 + ((_i) * 8)) /* _i=0...31 */ /* Reset: PE_CORER */ 5186#define I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX 31 5187#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0 5188#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT) 5189#define I40E_GLGEN_PME_TO 0x000B81BC /* Reset: POR */ 5190#define I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT 0 5191#define I40E_GLGEN_PME_TO_PME_TO_FOR_PE_MASK I40E_MASK(0x1, I40E_GLGEN_PME_TO_PME_TO_FOR_PE_SHIFT) 5192#define I40E_GLQF_APBVT(_i) (0x00260000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset: CORER */ 5193#define I40E_GLQF_APBVT_MAX_INDEX 2047 5194#define I40E_GLQF_APBVT_APBVT_SHIFT 0 5195#define I40E_GLQF_APBVT_APBVT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_APBVT_APBVT_SHIFT) 5196#define I40E_GLQF_FD_PCTYPES(_i) (0x00268000 + ((_i) * 4)) /* _i=0...63 */ /* Reset: POR */ 5197#define I40E_GLQF_FD_PCTYPES_MAX_INDEX 63 5198#define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT 0 5199#define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_MASK I40E_MASK(0x3F, I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT) 5200#define I40E_GLQF_FD_MSK(_i, _j) (0x00267200 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 5201#define I40E_GLQF_FD_MSK_MAX_INDEX 1 5202#define I40E_GLQF_FD_MSK_MASK_SHIFT 0 5203#define I40E_GLQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_GLQF_FD_MSK_MASK_SHIFT) 5204#define I40E_GLQF_FD_MSK_OFFSET_SHIFT 16 5205#define I40E_GLQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_GLQF_FD_MSK_OFFSET_SHIFT) 5206#define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 5207#define I40E_GLQF_HASH_INSET_MAX_INDEX 1 5208#define I40E_GLQF_HASH_INSET_INSET_SHIFT 0 5209#define I40E_GLQF_HASH_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_HASH_INSET_INSET_SHIFT) 5210#define I40E_GLQF_HASH_MSK(_i, _j) (0x00267A00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 5211#define I40E_GLQF_HASH_MSK_MAX_INDEX 1 5212#define I40E_GLQF_HASH_MSK_MASK_SHIFT 0 5213#define I40E_GLQF_HASH_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_GLQF_HASH_MSK_MASK_SHIFT) 5214#define I40E_GLQF_HASH_MSK_OFFSET_SHIFT 16 5215#define I40E_GLQF_HASH_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_GLQF_HASH_MSK_OFFSET_SHIFT) 5216#define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */ 5217#define I40E_GLQF_ORT_MAX_INDEX 63 5218#define I40E_GLQF_ORT_PIT_INDX_SHIFT 0 5219#define I40E_GLQF_ORT_PIT_INDX_MASK I40E_MASK(0x1F, I40E_GLQF_ORT_PIT_INDX_SHIFT) 5220#define I40E_GLQF_ORT_FIELD_CNT_SHIFT 5 5221#define I40E_GLQF_ORT_FIELD_CNT_MASK I40E_MASK(0x3, I40E_GLQF_ORT_FIELD_CNT_SHIFT) 5222#define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7 5223#define I40E_GLQF_ORT_FLX_PAYLOAD_MASK I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) 5224#define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) /* _i=0...23 */ /* Reset: CORER */ 5225#define I40E_GLQF_PIT_MAX_INDEX 23 5226#define I40E_GLQF_PIT_SOURCE_OFF_SHIFT 0 5227#define I40E_GLQF_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_GLQF_PIT_SOURCE_OFF_SHIFT) 5228#define I40E_GLQF_PIT_FSIZE_SHIFT 5 5229#define I40E_GLQF_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_GLQF_PIT_FSIZE_SHIFT) 5230#define I40E_GLQF_PIT_DEST_OFF_SHIFT 10 5231#define I40E_GLQF_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_GLQF_PIT_DEST_OFF_SHIFT) 5232#define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 5233#define I40E_GLQF_FDEVICTENA_MAX_INDEX 1 5234#define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT 0 5235#define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT) 5236#define I40E_GLQF_FDEVICTFLAG 0x00270280 /* Reset: CORER */ 5237#define I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT 0 5238#define I40E_GLQF_FDEVICTFLAG_TX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_TX_FLAGS_SHIFT) 5239#define I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT 8 5240#define I40E_GLQF_FDEVICTFLAG_RX_FLAGS_MASK I40E_MASK(0xFF, I40E_GLQF_FDEVICTFLAG_RX_FLAGS_SHIFT) 5241#define I40E_PFQF_CTL_2 0x00270300 /* Reset: CORER */ 5242#define I40E_PFQF_CTL_2_PEHSIZE_SHIFT 0 5243#define I40E_PFQF_CTL_2_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEHSIZE_SHIFT) 5244#define I40E_PFQF_CTL_2_PEDSIZE_SHIFT 5 5245#define I40E_PFQF_CTL_2_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_2_PEDSIZE_SHIFT) 5246/* Redefined for X722 family */ 5247#define I40E_X722_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */ 5248#define I40E_X722_PFQF_HLUT_MAX_INDEX 127 5249#define I40E_X722_PFQF_HLUT_LUT0_SHIFT 0 5250#define I40E_X722_PFQF_HLUT_LUT0_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT0_SHIFT) 5251#define I40E_X722_PFQF_HLUT_LUT1_SHIFT 8 5252#define I40E_X722_PFQF_HLUT_LUT1_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT1_SHIFT) 5253#define I40E_X722_PFQF_HLUT_LUT2_SHIFT 16 5254#define I40E_X722_PFQF_HLUT_LUT2_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT2_SHIFT) 5255#define I40E_X722_PFQF_HLUT_LUT3_SHIFT 24 5256#define I40E_X722_PFQF_HLUT_LUT3_MASK I40E_MASK(0x7F, I40E_X722_PFQF_HLUT_LUT3_SHIFT) 5257#define I40E_PFQF_HREGION(_i) (0x00245400 + ((_i) * 128)) /* _i=0...7 */ /* Reset: CORER */ 5258#define I40E_PFQF_HREGION_MAX_INDEX 7 5259#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 5260#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT) 5261#define I40E_PFQF_HREGION_REGION_0_SHIFT 1 5262#define I40E_PFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_0_SHIFT) 5263#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 5264#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT) 5265#define I40E_PFQF_HREGION_REGION_1_SHIFT 5 5266#define I40E_PFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_1_SHIFT) 5267#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 5268#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT) 5269#define I40E_PFQF_HREGION_REGION_2_SHIFT 9 5270#define I40E_PFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_2_SHIFT) 5271#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 5272#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT) 5273#define I40E_PFQF_HREGION_REGION_3_SHIFT 13 5274#define I40E_PFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_3_SHIFT) 5275#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 5276#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT) 5277#define I40E_PFQF_HREGION_REGION_4_SHIFT 17 5278#define I40E_PFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_4_SHIFT) 5279#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 5280#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT) 5281#define I40E_PFQF_HREGION_REGION_5_SHIFT 21 5282#define I40E_PFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_5_SHIFT) 5283#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 5284#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT) 5285#define I40E_PFQF_HREGION_REGION_6_SHIFT 25 5286#define I40E_PFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_6_SHIFT) 5287#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 5288#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT) 5289#define I40E_PFQF_HREGION_REGION_7_SHIFT 29 5290#define I40E_PFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_PFQF_HREGION_REGION_7_SHIFT) 5291#define I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT 8 5292#define I40E_VSIQF_CTL_RSS_LUT_TYPE_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_RSS_LUT_TYPE_SHIFT) 5293#define I40E_VSIQF_HKEY(_i, _VSI) (0x002A0000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...12, _VSI=0...383 */ /* Reset: CORER */ 5294#define I40E_VSIQF_HKEY_MAX_INDEX 12 5295#define I40E_VSIQF_HKEY_KEY_0_SHIFT 0 5296#define I40E_VSIQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_0_SHIFT) 5297#define I40E_VSIQF_HKEY_KEY_1_SHIFT 8 5298#define I40E_VSIQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_1_SHIFT) 5299#define I40E_VSIQF_HKEY_KEY_2_SHIFT 16 5300#define I40E_VSIQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_2_SHIFT) 5301#define I40E_VSIQF_HKEY_KEY_3_SHIFT 24 5302#define I40E_VSIQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VSIQF_HKEY_KEY_3_SHIFT) 5303#define I40E_VSIQF_HLUT(_i, _VSI) (0x00220000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...15, _VSI=0...383 */ /* Reset: CORER */ 5304#define I40E_VSIQF_HLUT_MAX_INDEX 15 5305#define I40E_VSIQF_HLUT_LUT0_SHIFT 0 5306#define I40E_VSIQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT0_SHIFT) 5307#define I40E_VSIQF_HLUT_LUT1_SHIFT 8 5308#define I40E_VSIQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT1_SHIFT) 5309#define I40E_VSIQF_HLUT_LUT2_SHIFT 16 5310#define I40E_VSIQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT2_SHIFT) 5311#define I40E_VSIQF_HLUT_LUT3_SHIFT 24 5312#define I40E_VSIQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VSIQF_HLUT_LUT3_SHIFT) 5313#define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */ 5314#define I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT 0 5315#define I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_CLEAR_GLGEN_STAT_CLEAR_SHIFT) 5316#define I40E_GLGEN_STAT_HALT 0x00390000 /* Reset: CORER */ 5317#define I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT 0 5318#define I40E_GLGEN_STAT_HALT_HALT_CELLS_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT) 5319#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30 5320#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT) 5321#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30 5322#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT) 5323#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */ 5324#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0 5325#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT) 5326#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */ 5327#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0 5328#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT) 5329#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */ 5330#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0 5331#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT) 5332#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */ 5333#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0 5334#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT) 5335#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4 5336#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT) 5337#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16 5338#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT) 5339#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31 5340#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT) 5341#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */ 5342#define I40E_VFPE_CQACK1_PECQID_SHIFT 0 5343#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT) 5344#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */ 5345#define I40E_VFPE_CQARM1_PECQID_SHIFT 0 5346#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT) 5347#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */ 5348#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0 5349#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT) 5350#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */ 5351#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0 5352#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT) 5353#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16 5354#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT) 5355#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */ 5356#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0 5357#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT) 5358#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31 5359#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT) 5360#define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */ 5361#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0 5362#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT) 5363#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16 5364#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT) 5365#define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */ 5366#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0 5367#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT) 5368#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */ 5369#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0 5370#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT) 5371#define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */ 5372#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0 5373#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT) 5374#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */ 5375#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0 5376#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT) 5377#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20 5378#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT) 5379 5380#endif /* _I40E_REGISTER_H_ */ | 3378#endif |