i40e_type.h (b4a7ce06) | i40e_type.h (2984a8dd) |
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1/****************************************************************************** 2 3 Copyright (c) 2013-2018, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 333 unchanged lines hidden (view full) --- 342#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ 343 I40E_PHY_TYPE_OFFSET) 344#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ 345 I40E_PHY_TYPE_OFFSET) 346#define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ 347 I40E_PHY_TYPE_OFFSET) 348#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ 349 I40E_PHY_TYPE_OFFSET) | 1/****************************************************************************** 2 3 Copyright (c) 2013-2018, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 333 unchanged lines hidden (view full) --- 342#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ 343 I40E_PHY_TYPE_OFFSET) 344#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ 345 I40E_PHY_TYPE_OFFSET) 346#define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ 347 I40E_PHY_TYPE_OFFSET) 348#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ 349 I40E_PHY_TYPE_OFFSET) |
350/* Offset for 2.5G/5G PHY Types value to bit number conversion */ 351#define I40E_PHY_TYPE_OFFSET2 (-10) 352#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \ 353 I40E_PHY_TYPE_OFFSET2) 354#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \ 355 I40E_PHY_TYPE_OFFSET2) |
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350#define I40E_HW_CAP_MAX_GPIO 30 351#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 352#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 353 354enum i40e_acpi_programming_method { 355 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, 356 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 357}; --- 1127 unchanged lines hidden (view full) --- 1485 u64 fd_atr_tunnel_match; 1486 u32 fd_atr_status; 1487 u32 fd_sb_status; 1488 /* EEE LPI */ 1489 u32 tx_lpi_status; 1490 u32 rx_lpi_status; 1491 u64 tx_lpi_count; /* etlpic */ 1492 u64 rx_lpi_count; /* erlpic */ | 356#define I40E_HW_CAP_MAX_GPIO 30 357#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 358#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 359 360enum i40e_acpi_programming_method { 361 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, 362 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 363}; --- 1127 unchanged lines hidden (view full) --- 1491 u64 fd_atr_tunnel_match; 1492 u32 fd_atr_status; 1493 u32 fd_sb_status; 1494 /* EEE LPI */ 1495 u32 tx_lpi_status; 1496 u32 rx_lpi_status; 1497 u64 tx_lpi_count; /* etlpic */ 1498 u64 rx_lpi_count; /* erlpic */ |
1499 u64 tx_lpi_duration; 1500 u64 rx_lpi_duration; |
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1493}; 1494 1495/* Checksum and Shadow RAM pointers */ 1496#define I40E_SR_NVM_CONTROL_WORD 0x00 1497#define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 1498#define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 1499#define I40E_SR_OPTION_ROM_PTR 0x05 1500#define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 --- 36 unchanged lines hidden (view full) --- 1537#define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 1538#define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 1539#define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 1540#define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 1541#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 1542#define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 1543#define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D 1544#define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E | 1501}; 1502 1503/* Checksum and Shadow RAM pointers */ 1504#define I40E_SR_NVM_CONTROL_WORD 0x00 1505#define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 1506#define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 1507#define I40E_SR_OPTION_ROM_PTR 0x05 1508#define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 --- 36 unchanged lines hidden (view full) --- 1545#define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 1546#define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 1547#define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 1548#define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 1549#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 1550#define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 1551#define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D 1552#define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E |
1553#define I40E_SR_5TH_FREE_PROVISION_AREA_PTR 0x50 |
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1545 1546/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1547#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1548#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1549#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1550#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1551#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) 1552#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) --- 170 unchanged lines hidden (view full) --- 1723#define I40E_FLEX_54_SHIFT 9 1724#define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT) 1725#define I40E_FLEX_55_SHIFT 8 1726#define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT) 1727#define I40E_FLEX_56_SHIFT 7 1728#define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT) 1729#define I40E_FLEX_57_SHIFT 6 1730#define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT) | 1554 1555/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1556#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1557#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1558#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1559#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1560#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) 1561#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) --- 170 unchanged lines hidden (view full) --- 1732#define I40E_FLEX_54_SHIFT 9 1733#define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT) 1734#define I40E_FLEX_55_SHIFT 8 1735#define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT) 1736#define I40E_FLEX_56_SHIFT 7 1737#define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT) 1738#define I40E_FLEX_57_SHIFT 6 1739#define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT) |
1740#define I40E_BCM_PHY_PCS_STATUS1_PAGE 0x3 1741#define I40E_BCM_PHY_PCS_STATUS1_REG 0x0001 1742#define I40E_BCM_PHY_PCS_STATUS1_RX_LPI BIT(8) 1743#define I40E_BCM_PHY_PCS_STATUS1_TX_LPI BIT(9) 1744 |
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1731#endif /* _I40E_TYPE_H_ */ | 1745#endif /* _I40E_TYPE_H_ */ |