if_ixl.c (6d011ad5) if_ixl.c (d4683565)
1/******************************************************************************
2
3 Copyright (c) 2013-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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43
44#ifdef RSS
45#include <net/rss_config.h>
46#endif
47
48/*********************************************************************
49 * Driver version
50 *********************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2013-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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43
44#ifdef RSS
45#include <net/rss_config.h>
46#endif
47
48/*********************************************************************
49 * Driver version
50 *********************************************************************/
51char ixl_driver_version[] = "1.4.24-k";
51char ixl_driver_version[] = "1.4.27-k";
52
53/*********************************************************************
54 * PCI Device ID Table
55 *
56 * Used by probe to select devices to load on
57 * Last field stores an index into ixl_strings
58 * Last entry must be all 0s
59 *

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552 }
553
554 error = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
555 if (error) {
556 device_printf(dev, "configure_lan_hmc failed: %d\n", error);
557 goto err_mac_hmc;
558 }
559
52
53/*********************************************************************
54 * PCI Device ID Table
55 *
56 * Used by probe to select devices to load on
57 * Last field stores an index into ixl_strings
58 * Last entry must be all 0s
59 *

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552 }
553
554 error = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
555 if (error) {
556 device_printf(dev, "configure_lan_hmc failed: %d\n", error);
557 goto err_mac_hmc;
558 }
559
560 /* Disable LLDP from the firmware */
561 i40e_aq_stop_lldp(hw, TRUE, NULL);
560 /* Disable LLDP from the firmware for certain NVM versions */
561 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
562 (pf->hw.aq.fw_maj_ver < 4))
563 i40e_aq_stop_lldp(hw, TRUE, NULL);
562
563 i40e_get_mac_addr(hw, hw->mac.addr);
564 error = i40e_validate_mac_addr(hw->mac.addr);
565 if (error) {
566 device_printf(dev, "validate_mac_addr failed: %d\n", error);
567 goto err_mac_hmc;
568 }
569 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);

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2577ixl_configure_queue_intr_msix(struct ixl_pf *pf)
2578{
2579 struct i40e_hw *hw = &pf->hw;
2580 struct ixl_vsi *vsi = &pf->vsi;
2581 u32 reg;
2582 u16 vector = 1;
2583
2584 for (int i = 0; i < vsi->num_queues; i++, vector++) {
564
565 i40e_get_mac_addr(hw, hw->mac.addr);
566 error = i40e_validate_mac_addr(hw->mac.addr);
567 if (error) {
568 device_printf(dev, "validate_mac_addr failed: %d\n", error);
569 goto err_mac_hmc;
570 }
571 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHER_ADDR_LEN);

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2579ixl_configure_queue_intr_msix(struct ixl_pf *pf)
2580{
2581 struct i40e_hw *hw = &pf->hw;
2582 struct ixl_vsi *vsi = &pf->vsi;
2583 u32 reg;
2584 u16 vector = 1;
2585
2586 for (int i = 0; i < vsi->num_queues; i++, vector++) {
2585 wr32(hw, I40E_PFINT_DYN_CTLN(i), i);
2587 wr32(hw, I40E_PFINT_DYN_CTLN(i), 0);
2588 /* First queue type is RX / 0 */
2586 wr32(hw, I40E_PFINT_LNKLSTN(i), i);
2587
2588 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2589 (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2590 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2591 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2592 (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2593 wr32(hw, I40E_QINT_RQCTL(i), reg);
2594
2595 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2596 (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2597 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2589 wr32(hw, I40E_PFINT_LNKLSTN(i), i);
2590
2591 reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
2592 (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
2593 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2594 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2595 (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
2596 wr32(hw, I40E_QINT_RQCTL(i), reg);
2597
2598 reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
2599 (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
2600 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
2598 ((i+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
2601 (IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
2599 (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2602 (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
2600 if (i == (vsi->num_queues - 1))
2601 reg |= (IXL_QUEUE_EOL
2602 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
2603 wr32(hw, I40E_QINT_TQCTL(i), reg);
2604 }
2605}
2606
2607/*
2608 * Configure for MSI single vector operation
2609 */
2610static void

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3877
3878#ifdef RSS
3879 /* Fetch the configured RSS key */
3880 rss_getkey((uint8_t *) &rss_seed);
3881#endif
3882
3883 /* Fill out hash function seed */
3884 for (i = 0; i < IXL_KEYSZ; i++)
2603 wr32(hw, I40E_QINT_TQCTL(i), reg);
2604 }
2605}
2606
2607/*
2608 * Configure for MSI single vector operation
2609 */
2610static void

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3877
3878#ifdef RSS
3879 /* Fetch the configured RSS key */
3880 rss_getkey((uint8_t *) &rss_seed);
3881#endif
3882
3883 /* Fill out hash function seed */
3884 for (i = 0; i < IXL_KEYSZ; i++)
3885 wr32(hw, I40E_PFQF_HKEY(i), rss_seed[i]);
3885 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), rss_seed[i]);
3886
3887 /* Enable PCTYPES for RSS: */
3888#ifdef RSS
3889 rss_hash_config = rss_gethashconfig();
3890 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4)
3891 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3892 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4)
3893 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);

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3910 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) |
3911 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
3912 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
3913 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) |
3914 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |
3915 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) |
3916 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3917#endif
3886
3887 /* Enable PCTYPES for RSS: */
3888#ifdef RSS
3889 rss_hash_config = rss_gethashconfig();
3890 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4)
3891 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3892 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4)
3893 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);

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3910 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) |
3911 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
3912 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
3913 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) |
3914 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |
3915 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) |
3916 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3917#endif
3918 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
3919 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
3918 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
3919 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
3920 hena |= set_hena;
3920 hena |= set_hena;
3921 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
3922 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
3921 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
3922 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
3923
3924 /* Populate the LUT with max no. of queues in round robin fashion */
3925 for (i = j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
3926 if (j == vsi->num_queues)
3927 j = 0;
3928#ifdef RSS
3929 /*
3930 * Fetch the RSS bucket id for the given indirection entry.

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6111 /*
6112 * Two queues are mapped in a single register, so we have to do some
6113 * gymnastics to convert the queue number into a register index and
6114 * shift.
6115 */
6116 index = qnum / 2;
6117 shift = (qnum % 2) * I40E_VSILAN_QTABLE_QINDEX_1_SHIFT;
6118
3923
3924 /* Populate the LUT with max no. of queues in round robin fashion */
3925 for (i = j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
3926 if (j == vsi->num_queues)
3927 j = 0;
3928#ifdef RSS
3929 /*
3930 * Fetch the RSS bucket id for the given indirection entry.

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6111 /*
6112 * Two queues are mapped in a single register, so we have to do some
6113 * gymnastics to convert the queue number into a register index and
6114 * shift.
6115 */
6116 index = qnum / 2;
6117 shift = (qnum % 2) * I40E_VSILAN_QTABLE_QINDEX_1_SHIFT;
6118
6119 qtable = rd32(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num));
6119 qtable = i40e_read_rx_ctl(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num));
6120 qtable &= ~(I40E_VSILAN_QTABLE_QINDEX_0_MASK << shift);
6121 qtable |= val << shift;
6120 qtable &= ~(I40E_VSILAN_QTABLE_QINDEX_0_MASK << shift);
6121 qtable |= val << shift;
6122 wr32(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num), qtable);
6122 i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(index, vf->vsi.vsi_num), qtable);
6123}
6124
6125static void
6126ixl_vf_map_queues(struct ixl_pf *pf, struct ixl_vf *vf)
6127{
6128 struct i40e_hw *hw;
6129 uint32_t qtable;
6130 int i;
6131
6132 hw = &pf->hw;
6133
6134 /*
6135 * Contiguous mappings aren't actually supported by the hardware,
6136 * so we have to use non-contiguous mappings.
6137 */
6123}
6124
6125static void
6126ixl_vf_map_queues(struct ixl_pf *pf, struct ixl_vf *vf)
6127{
6128 struct i40e_hw *hw;
6129 uint32_t qtable;
6130 int i;
6131
6132 hw = &pf->hw;
6133
6134 /*
6135 * Contiguous mappings aren't actually supported by the hardware,
6136 * so we have to use non-contiguous mappings.
6137 */
6138 wr32(hw, I40E_VSILAN_QBASE(vf->vsi.vsi_num),
6138 i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vf->vsi.vsi_num),
6139 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
6140
6141 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_num),
6142 I40E_VPLAN_MAPENA_TXRX_ENA_MASK);
6143
6144 for (i = 0; i < vf->vsi.num_queues; i++) {
6145 qtable = (vf->vsi.first_queue + i) <<
6146 I40E_VPLAN_QTABLE_QINDEX_SHIFT;

--- 1322 unchanged lines hidden --- 		6139 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
6140
6141 wr32(hw, I40E_VPLAN_MAPENA(vf->vf_num),
6142 I40E_VPLAN_MAPENA_TXRX_ENA_MASK);
6143
6144 for (i = 0; i < vf->vsi.num_queues; i++) {
6145 qtable = (vf->vsi.first_queue + i) <<
6146 I40E_VPLAN_QTABLE_QINDEX_SHIFT;

--- 1322 unchanged lines hidden ---