1/******************************************************************************
2
3 Copyright (c) 2013-2014, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
--- 15 unchanged lines hidden (view full) ---
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD$*/
34
35
36#ifndef _IXL_H_
37#define _IXL_H_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/buf_ring.h>
43#include <sys/mbuf.h>
44#include <sys/protosw.h>
45#include <sys/socket.h>
46#include <sys/malloc.h>
47#include <sys/kernel.h>
48#include <sys/module.h>
49#include <sys/sockio.h>
50
51#include <net/if.h>
52#include <net/if_arp.h>
53#include <net/bpf.h>
54#include <net/ethernet.h>
55#include <net/if_dl.h>
56#include <net/if_media.h>
57
58#include <net/bpf.h>
59#include <net/if_types.h>
60#include <net/if_vlan_var.h>
61
62#include <netinet/in_systm.h>
63#include <netinet/in.h>
64#include <netinet/if_ether.h>
--- 16 unchanged lines hidden (view full) ---
81#include <dev/pci/pcivar.h>
82#include <dev/pci/pcireg.h>
83#include <sys/proc.h>
84#include <sys/sysctl.h>
85#include <sys/endian.h>
86#include <sys/taskqueue.h>
87#include <sys/pcpu.h>
88#include <sys/smp.h>
89#include <machine/smp.h>
90
91#include "i40e_type.h"
92#include "i40e_prototype.h"
93
94#ifdef IXL_DEBUG
95#include <sys/sbuf.h>
96
97#define MAC_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x"
98#define MAC_FORMAT_ARGS(mac_addr) \
99 (mac_addr)[0], (mac_addr)[1], (mac_addr)[2], (mac_addr)[3], \
100 (mac_addr)[4], (mac_addr)[5]
101#define ON_OFF_STR(is_set) ((is_set) ? "On" : "Off")
102
103
104#define _DBG_PRINTF(S, ...) printf("%s: " S "\n", __func__, ##__VA_ARGS__)
105#define _DEV_DBG_PRINTF(dev, S, ...) device_printf(dev, "%s: " S "\n", __func__, ##__VA_ARGS__)
106#define _IF_DBG_PRINTF(ifp, S, ...) if_printf(ifp, "%s: " S "\n", __func__, ##__VA_ARGS__)
107
108/* Defines for printing generic debug information */
109#define DPRINTF(...) _DBG_PRINTF(__VA_ARGS__)
110#define DDPRINTF(...) _DEV_DBG_PRINTF(__VA_ARGS__)
111#define IDPRINTF(...) _IF_DBG_PRINTF(__VA_ARGS__)
112
113/* Defines for printing specific debug information */
114#define DEBUG_INIT 1
115#define DEBUG_IOCTL 1
116#define DEBUG_HW 1
117
118#define INIT_DEBUGOUT(...) if (DEBUG_INIT) _DBG_PRINTF(__VA_ARGS__)
119#define INIT_DBG_DEV(...) if (DEBUG_INIT) _DEV_DBG_PRINTF(__VA_ARGS__)
120#define INIT_DBG_IF(...) if (DEBUG_INIT) _IF_DBG_PRINTF(__VA_ARGS__)
121
122#define IOCTL_DEBUGOUT(...) if (DEBUG_IOCTL) _DBG_PRINTF(__VA_ARGS__)
123#define IOCTL_DBG_IF2(ifp, S, ...) if (DEBUG_IOCTL) \
124 if_printf(ifp, S "\n", ##__VA_ARGS__)
125#define IOCTL_DBG_IF(...) if (DEBUG_IOCTL) _IF_DBG_PRINTF(__VA_ARGS__)
126
127#define HW_DEBUGOUT(...) if (DEBUG_HW) _DBG_PRINTF(__VA_ARGS__)
128
129#else
130#define DEBUG_INIT 0
131#define DEBUG_IOCTL 0
132#define DEBUG_HW 0
133
134#define DPRINTF(...)
135#define DDPRINTF(...)
136#define IDPRINTF(...)
137
138#define INIT_DEBUGOUT(...)
139#define INIT_DBG_DEV(...)
140#define INIT_DBG_IF(...)
141#define IOCTL_DEBUGOUT(...)
142#define IOCTL_DBG_IF2(...)
143#define IOCTL_DBG_IF(...)
144#define HW_DEBUGOUT(...)
145#endif
146
147/* Tunables */
148
149/*
150 * Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the
151 * number of tx/rx descriptors allocated by the driver. Increasing this
152 * value allows the driver to queue more operations. Each descriptor is 16
153 * or 32 bytes (configurable in FVL)
154 */
155#define DEFAULT_RING 1024
156#define PERFORM_RING 2048
157#define MAX_RING 4096
158#define MIN_RING 32
159
160/*
161** Default number of entries in Tx queue buf_ring.
162*/
163#define DEFAULT_TXBRSZ (4096 * 4096)
164
165/* Alignment for rings */
166#define DBA_ALIGN 128
167
168/*
169 * This parameter controls the maximum no of times the driver will loop in
170 * the isr. Minimum Value = 1
171 */
172#define MAX_LOOP 10
173
174/*
175 * This is the max watchdog interval, ie. the time that can
176 * pass between any two TX clean operations, such only happening
177 * when the TX hardware is functioning.
178 */
179#define IXL_WATCHDOG (10 * hz)
180
181/*
182 * This parameters control when the driver calls the routine to reclaim
183 * transmit descriptors.
184 */
185#define IXL_TX_CLEANUP_THRESHOLD (que->num_desc / 8)
186#define IXL_TX_OP_THRESHOLD (que->num_desc / 32)
187
188/* Flow control constants */
189#define IXL_FC_PAUSE 0xFFFF
190#define IXL_FC_HI 0x20000
191#define IXL_FC_LO 0x10000
192
193#define MAX_MULTICAST_ADDR 128
194
195#define IXL_BAR 3
196#define IXL_ADM_LIMIT 2
197#define IXL_TSO_SIZE 65535
198#define IXL_TX_BUF_SZ ((u32) 1514)
199#define IXL_AQ_BUF_SZ ((u32) 4096)
200#define IXL_RX_HDR 128
201#define IXL_AQ_LEN 256
202#define IXL_AQ_BUFSZ 4096
203#define IXL_RX_LIMIT 512
204#define IXL_RX_ITR 0
205#define IXL_TX_ITR 1
206#define IXL_ITR_NONE 3
207#define IXL_QUEUE_EOL 0x7FF
208#define IXL_MAX_FRAME 0x2600
209#define IXL_MAX_TX_SEGS 8
210#define IXL_MAX_TSO_SEGS 66
211#define IXL_SPARSE_CHAIN 6
212#define IXL_QUEUE_HUNG 0x80000000
213
214/* ERJ: hardware can support ~1.5k filters between all functions */
215#define IXL_MAX_FILTERS 256
216#define IXL_MAX_TX_BUSY 10
217
218#define IXL_NVM_VERSION_LO_SHIFT 0
219#define IXL_NVM_VERSION_LO_MASK (0xff << IXL_NVM_VERSION_LO_SHIFT)
220#define IXL_NVM_VERSION_HI_SHIFT 12
221#define IXL_NVM_VERSION_HI_MASK (0xf << IXL_NVM_VERSION_HI_SHIFT)
222
223
224/*
225 * Interrupt Moderation parameters
226 */
227#define IXL_MAX_ITR 0x07FF
228#define IXL_ITR_100K 0x0005
229#define IXL_ITR_20K 0x0019
230#define IXL_ITR_8K 0x003E
231#define IXL_ITR_4K 0x007A
232#define IXL_ITR_DYNAMIC 0x8000
233#define IXL_LOW_LATENCY 0
234#define IXL_AVE_LATENCY 1
235#define IXL_BULK_LATENCY 2
236
237/* MacVlan Flags */
238#define IXL_FILTER_USED (u16)(1 << 0)
239#define IXL_FILTER_VLAN (u16)(1 << 1)
240#define IXL_FILTER_ADD (u16)(1 << 2)
241#define IXL_FILTER_DEL (u16)(1 << 3)
242#define IXL_FILTER_MC (u16)(1 << 4)
243
244/* used in the vlan field of the filter when not a vlan */
245#define IXL_VLAN_ANY -1
246
247#define CSUM_OFFLOAD_IPV4 (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
248#define CSUM_OFFLOAD_IPV6 (CSUM_TCP_IPV6|CSUM_UDP_IPV6|CSUM_SCTP_IPV6)
249#define CSUM_OFFLOAD (CSUM_OFFLOAD_IPV4|CSUM_OFFLOAD_IPV6|CSUM_TSO)
250
251/* Misc flags for ixl_vsi.flags */
252#define IXL_FLAGS_KEEP_TSO4 (1 << 0)
253#define IXL_FLAGS_KEEP_TSO6 (1 << 1)
254
255#define IXL_TX_LOCK(_sc) mtx_lock(&(_sc)->mtx)
256#define IXL_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
257#define IXL_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
258#define IXL_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->mtx)
259#define IXL_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
260
261#define IXL_RX_LOCK(_sc) mtx_lock(&(_sc)->mtx)
262#define IXL_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
263#define IXL_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
264
265/*
266 *****************************************************************************
267 * vendor_info_array
268 *
269 * This array contains the list of Subvendor/Subdevice IDs on which the driver
270 * should load.
271 *
272 *****************************************************************************
273 */
274typedef struct _ixl_vendor_info_t {
275 unsigned int vendor_id;
276 unsigned int device_id;
277 unsigned int subvendor_id;
278 unsigned int subdevice_id;
279 unsigned int index;
280} ixl_vendor_info_t;
281
282
283struct ixl_tx_buf {
284 u32 eop_index;
285 struct mbuf *m_head;
286 bus_dmamap_t map;
287 bus_dma_tag_t tag;
288};
289
290struct ixl_rx_buf {
291 struct mbuf *m_head;
292 struct mbuf *m_pack;
293 struct mbuf *fmp;
294 bus_dmamap_t hmap;
295 bus_dmamap_t pmap;
296#ifdef DEV_NETMAP
297 u64 addr;
298#endif
299};
300
301/*
302** This struct has multiple uses, multicast
303** addresses, vlans, and mac filters all use it.
304*/
305struct ixl_mac_filter {
306 SLIST_ENTRY(ixl_mac_filter) next;
307 u8 macaddr[ETHER_ADDR_LEN];
308 s16 vlan;
309 u16 flags;
310};
311
312
313/*
314 * The Transmit ring control struct
315 */
316struct tx_ring {
317 struct ixl_queue *que;
318 struct mtx mtx;
319 u32 tail;
320 struct i40e_tx_desc *base;
321 struct i40e_dma_mem dma;
322 u16 next_avail;
323 u16 next_to_clean;
324 u16 atr_rate;
325 u16 atr_count;
326 u16 itr;
327 u16 latency;
328 struct ixl_tx_buf *buffers;
329 volatile u16 avail;
330 u32 cmd;
331 bus_dma_tag_t tx_tag;
332 bus_dma_tag_t tso_tag;
333 char mtx_name[16];
334 struct buf_ring *br;
335
336 /* Used for Dynamic ITR calculation */
337 u32 packets;
338 u32 bytes;
339
340 /* Soft Stats */
341 u64 tx_bytes;
342 u64 no_desc;
343 u64 total_packets;
344};
345
346
347/*
348 * The Receive ring control struct
349 */
350struct rx_ring {
351 struct ixl_queue *que;
352 struct mtx mtx;
353 union i40e_rx_desc *base;
354 struct i40e_dma_mem dma;
355 struct lro_ctrl lro;
356 bool lro_enabled;
357 bool hdr_split;
358 bool discard;
359 u16 next_refresh;
360 u16 next_check;
361 u16 itr;
362 u16 latency;
363 char mtx_name[16];
364 struct ixl_rx_buf *buffers;
365 u32 mbuf_sz;
366 u32 tail;
367 bus_dma_tag_t htag;
368 bus_dma_tag_t ptag;
369
370 /* Used for Dynamic ITR calculation */
371 u32 packets;
372 u32 bytes;
373
374 /* Soft stats */
375 u64 split;
376 u64 rx_packets;
377 u64 rx_bytes;
378 u64 discarded;
379 u64 not_done;
380};
381
382/*
383** Driver queue struct: this is the interrupt container
384** for the associated tx and rx ring pair.
385*/
386struct ixl_queue {
387 struct ixl_vsi *vsi;
388 u32 me;
389 u32 msix; /* This queue's MSIX vector */
390 u32 eims; /* This queue's EIMS bit */
391 struct resource *res;
392 void *tag;
393 int num_desc; /* both tx and rx */
394 int busy;
395 struct tx_ring txr;
396 struct rx_ring rxr;
397 struct task task;
398 struct task tx_task;
399 struct taskqueue *tq;
400
401 /* Queue stats */
402 u64 irqs;
403 u64 tso;
404 u64 mbuf_defrag_failed;
405 u64 mbuf_hdr_failed;
406 u64 mbuf_pkt_failed;
407 u64 tx_map_avail;
408 u64 tx_dma_setup;
409 u64 dropped_pkts;
410};
411
412/*
413** Virtual Station interface:
414** there would be one of these per traffic class/type
415** for now just one, and its embedded in the pf
416*/
417SLIST_HEAD(ixl_ftl_head, ixl_mac_filter);
418struct ixl_vsi {
419 void *back;
420 struct ifnet *ifp;
421 struct device *dev;
422 struct i40e_hw *hw;
423 struct ifmedia media;
424 u64 que_mask;
425 int id;
426 u16 msix_base; /* station base MSIX vector */
427 u16 num_queues;
428 u16 rx_itr_setting;
429 u16 tx_itr_setting;
430 struct ixl_queue *queues; /* head of queues */
431 bool link_active;
432 u16 seid;
433 u16 max_frame_size;
434 u32 link_speed;
435 bool link_up;
436 u32 fc; /* local flow ctrl setting */
437
438 /* MAC/VLAN Filter list */
439 struct ixl_ftl_head ftl;
440
441 struct i40e_aqc_vsi_properties_data info;
442
443 eventhandler_tag vlan_attach;
444 eventhandler_tag vlan_detach;
445 u16 num_vlans;
446
447 /* Per-VSI stats from hardware */
448 struct i40e_eth_stats eth_stats;
449 struct i40e_eth_stats eth_stats_offsets;
450 bool stat_offsets_loaded;
451
452 /* Driver statistics */
453 u64 hw_filters_del;
454 u64 hw_filters_add;
455
456 /* Misc. */
457 u64 active_queues;
458 u64 flags;
459};
460
461/*
462** Find the number of unrefreshed RX descriptors
463*/
464static inline u16
465ixl_rx_unrefreshed(struct ixl_queue *que)
466{
467 struct rx_ring *rxr = &que->rxr;
468
469 if (rxr->next_check > rxr->next_refresh)
470 return (rxr->next_check - rxr->next_refresh - 1);
471 else
472 return ((que->num_desc + rxr->next_check) -
473 rxr->next_refresh - 1);
474}
475
476/*
477** Find the next available unused filter
478*/
479static inline struct ixl_mac_filter *
480ixl_get_filter(struct ixl_vsi *vsi)
481{
482 struct ixl_mac_filter *f;
483
484 /* create a new empty filter */
485 f = malloc(sizeof(struct ixl_mac_filter),
486 M_DEVBUF, M_NOWAIT | M_ZERO);
487 SLIST_INSERT_HEAD(&vsi->ftl, f, next);
488
489 return (f);
490}
491
492/*
493** Compare two ethernet addresses
494*/
495static inline bool
496cmp_etheraddr(u8 *ea1, u8 *ea2)
497{
498 bool cmp = FALSE;
499
500 if ((ea1[0] == ea2[0]) && (ea1[1] == ea2[1]) &&
501 (ea1[2] == ea2[2]) && (ea1[3] == ea2[3]) &&
502 (ea1[4] == ea2[4]) && (ea1[5] == ea2[5]))
503 cmp = TRUE;
504
505 return (cmp);
506}
507
508/*
509 * Info for stats sysctls
510 */
511struct ixl_sysctl_info {
512 u64 *stat;
513 char *name;
514 char *description;
515};
516
517extern int ixl_atr_rate;
518
519/*
520** ixl_fw_version_str - format the FW and NVM version strings
521*/
522static inline char *
523ixl_fw_version_str(struct i40e_hw *hw)
524{
525 static char buf[32];
526
527 snprintf(buf, sizeof(buf),
528 "f%d.%d a%d.%d n%02x.%02x e%08x",
529 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
530 hw->aq.api_maj_ver, hw->aq.api_min_ver,
531 (hw->nvm.version & IXL_NVM_VERSION_HI_MASK) >>
532 IXL_NVM_VERSION_HI_SHIFT,
533 (hw->nvm.version & IXL_NVM_VERSION_LO_MASK) >>
534 IXL_NVM_VERSION_LO_SHIFT,
535 hw->nvm.eetrack);
536 return buf;
537}
538
539/*********************************************************************
540 * TXRX Function prototypes
541 *********************************************************************/
542int ixl_allocate_tx_data(struct ixl_queue *);
543int ixl_allocate_rx_data(struct ixl_queue *);
544void ixl_init_tx_ring(struct ixl_queue *);
545int ixl_init_rx_ring(struct ixl_queue *);
546bool ixl_rxeof(struct ixl_queue *, int);
547bool ixl_txeof(struct ixl_queue *);
548int ixl_mq_start(struct ifnet *, struct mbuf *);
549int ixl_mq_start_locked(struct ifnet *, struct tx_ring *);
550void ixl_deferred_mq_start(void *, int);
551void ixl_qflush(struct ifnet *);
552void ixl_free_vsi(struct ixl_vsi *);
553void ixl_free_que_tx(struct ixl_queue *);
554void ixl_free_que_rx(struct ixl_queue *);
555#ifdef IXL_FDIR
556void ixl_atr(struct ixl_queue *, struct tcphdr *, int);
557#endif
558
559#endif /* _IXL_H_ */
2
3 Copyright (c) 2013-2014, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
--- 15 unchanged lines hidden (view full) ---
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD$*/
34
35
36#ifndef _IXL_H_
37#define _IXL_H_
38
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/buf_ring.h>
43#include <sys/mbuf.h>
44#include <sys/protosw.h>
45#include <sys/socket.h>
46#include <sys/malloc.h>
47#include <sys/kernel.h>
48#include <sys/module.h>
49#include <sys/sockio.h>
50
51#include <net/if.h>
52#include <net/if_arp.h>
53#include <net/bpf.h>
54#include <net/ethernet.h>
55#include <net/if_dl.h>
56#include <net/if_media.h>
57
58#include <net/bpf.h>
59#include <net/if_types.h>
60#include <net/if_vlan_var.h>
61
62#include <netinet/in_systm.h>
63#include <netinet/in.h>
64#include <netinet/if_ether.h>
--- 16 unchanged lines hidden (view full) ---
81#include <dev/pci/pcivar.h>
82#include <dev/pci/pcireg.h>
83#include <sys/proc.h>
84#include <sys/sysctl.h>
85#include <sys/endian.h>
86#include <sys/taskqueue.h>
87#include <sys/pcpu.h>
88#include <sys/smp.h>
89#include <machine/smp.h>
90
91#include "i40e_type.h"
92#include "i40e_prototype.h"
93
94#ifdef IXL_DEBUG
95#include <sys/sbuf.h>
96
97#define MAC_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x"
98#define MAC_FORMAT_ARGS(mac_addr) \
99 (mac_addr)[0], (mac_addr)[1], (mac_addr)[2], (mac_addr)[3], \
100 (mac_addr)[4], (mac_addr)[5]
101#define ON_OFF_STR(is_set) ((is_set) ? "On" : "Off")
102
103
104#define _DBG_PRINTF(S, ...) printf("%s: " S "\n", __func__, ##__VA_ARGS__)
105#define _DEV_DBG_PRINTF(dev, S, ...) device_printf(dev, "%s: " S "\n", __func__, ##__VA_ARGS__)
106#define _IF_DBG_PRINTF(ifp, S, ...) if_printf(ifp, "%s: " S "\n", __func__, ##__VA_ARGS__)
107
108/* Defines for printing generic debug information */
109#define DPRINTF(...) _DBG_PRINTF(__VA_ARGS__)
110#define DDPRINTF(...) _DEV_DBG_PRINTF(__VA_ARGS__)
111#define IDPRINTF(...) _IF_DBG_PRINTF(__VA_ARGS__)
112
113/* Defines for printing specific debug information */
114#define DEBUG_INIT 1
115#define DEBUG_IOCTL 1
116#define DEBUG_HW 1
117
118#define INIT_DEBUGOUT(...) if (DEBUG_INIT) _DBG_PRINTF(__VA_ARGS__)
119#define INIT_DBG_DEV(...) if (DEBUG_INIT) _DEV_DBG_PRINTF(__VA_ARGS__)
120#define INIT_DBG_IF(...) if (DEBUG_INIT) _IF_DBG_PRINTF(__VA_ARGS__)
121
122#define IOCTL_DEBUGOUT(...) if (DEBUG_IOCTL) _DBG_PRINTF(__VA_ARGS__)
123#define IOCTL_DBG_IF2(ifp, S, ...) if (DEBUG_IOCTL) \
124 if_printf(ifp, S "\n", ##__VA_ARGS__)
125#define IOCTL_DBG_IF(...) if (DEBUG_IOCTL) _IF_DBG_PRINTF(__VA_ARGS__)
126
127#define HW_DEBUGOUT(...) if (DEBUG_HW) _DBG_PRINTF(__VA_ARGS__)
128
129#else
130#define DEBUG_INIT 0
131#define DEBUG_IOCTL 0
132#define DEBUG_HW 0
133
134#define DPRINTF(...)
135#define DDPRINTF(...)
136#define IDPRINTF(...)
137
138#define INIT_DEBUGOUT(...)
139#define INIT_DBG_DEV(...)
140#define INIT_DBG_IF(...)
141#define IOCTL_DEBUGOUT(...)
142#define IOCTL_DBG_IF2(...)
143#define IOCTL_DBG_IF(...)
144#define HW_DEBUGOUT(...)
145#endif
146
147/* Tunables */
148
149/*
150 * Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the
151 * number of tx/rx descriptors allocated by the driver. Increasing this
152 * value allows the driver to queue more operations. Each descriptor is 16
153 * or 32 bytes (configurable in FVL)
154 */
155#define DEFAULT_RING 1024
156#define PERFORM_RING 2048
157#define MAX_RING 4096
158#define MIN_RING 32
159
160/*
161** Default number of entries in Tx queue buf_ring.
162*/
163#define DEFAULT_TXBRSZ (4096 * 4096)
164
165/* Alignment for rings */
166#define DBA_ALIGN 128
167
168/*
169 * This parameter controls the maximum no of times the driver will loop in
170 * the isr. Minimum Value = 1
171 */
172#define MAX_LOOP 10
173
174/*
175 * This is the max watchdog interval, ie. the time that can
176 * pass between any two TX clean operations, such only happening
177 * when the TX hardware is functioning.
178 */
179#define IXL_WATCHDOG (10 * hz)
180
181/*
182 * This parameters control when the driver calls the routine to reclaim
183 * transmit descriptors.
184 */
185#define IXL_TX_CLEANUP_THRESHOLD (que->num_desc / 8)
186#define IXL_TX_OP_THRESHOLD (que->num_desc / 32)
187
188/* Flow control constants */
189#define IXL_FC_PAUSE 0xFFFF
190#define IXL_FC_HI 0x20000
191#define IXL_FC_LO 0x10000
192
193#define MAX_MULTICAST_ADDR 128
194
195#define IXL_BAR 3
196#define IXL_ADM_LIMIT 2
197#define IXL_TSO_SIZE 65535
198#define IXL_TX_BUF_SZ ((u32) 1514)
199#define IXL_AQ_BUF_SZ ((u32) 4096)
200#define IXL_RX_HDR 128
201#define IXL_AQ_LEN 256
202#define IXL_AQ_BUFSZ 4096
203#define IXL_RX_LIMIT 512
204#define IXL_RX_ITR 0
205#define IXL_TX_ITR 1
206#define IXL_ITR_NONE 3
207#define IXL_QUEUE_EOL 0x7FF
208#define IXL_MAX_FRAME 0x2600
209#define IXL_MAX_TX_SEGS 8
210#define IXL_MAX_TSO_SEGS 66
211#define IXL_SPARSE_CHAIN 6
212#define IXL_QUEUE_HUNG 0x80000000
213
214/* ERJ: hardware can support ~1.5k filters between all functions */
215#define IXL_MAX_FILTERS 256
216#define IXL_MAX_TX_BUSY 10
217
218#define IXL_NVM_VERSION_LO_SHIFT 0
219#define IXL_NVM_VERSION_LO_MASK (0xff << IXL_NVM_VERSION_LO_SHIFT)
220#define IXL_NVM_VERSION_HI_SHIFT 12
221#define IXL_NVM_VERSION_HI_MASK (0xf << IXL_NVM_VERSION_HI_SHIFT)
222
223
224/*
225 * Interrupt Moderation parameters
226 */
227#define IXL_MAX_ITR 0x07FF
228#define IXL_ITR_100K 0x0005
229#define IXL_ITR_20K 0x0019
230#define IXL_ITR_8K 0x003E
231#define IXL_ITR_4K 0x007A
232#define IXL_ITR_DYNAMIC 0x8000
233#define IXL_LOW_LATENCY 0
234#define IXL_AVE_LATENCY 1
235#define IXL_BULK_LATENCY 2
236
237/* MacVlan Flags */
238#define IXL_FILTER_USED (u16)(1 << 0)
239#define IXL_FILTER_VLAN (u16)(1 << 1)
240#define IXL_FILTER_ADD (u16)(1 << 2)
241#define IXL_FILTER_DEL (u16)(1 << 3)
242#define IXL_FILTER_MC (u16)(1 << 4)
243
244/* used in the vlan field of the filter when not a vlan */
245#define IXL_VLAN_ANY -1
246
247#define CSUM_OFFLOAD_IPV4 (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
248#define CSUM_OFFLOAD_IPV6 (CSUM_TCP_IPV6|CSUM_UDP_IPV6|CSUM_SCTP_IPV6)
249#define CSUM_OFFLOAD (CSUM_OFFLOAD_IPV4|CSUM_OFFLOAD_IPV6|CSUM_TSO)
250
251/* Misc flags for ixl_vsi.flags */
252#define IXL_FLAGS_KEEP_TSO4 (1 << 0)
253#define IXL_FLAGS_KEEP_TSO6 (1 << 1)
254
255#define IXL_TX_LOCK(_sc) mtx_lock(&(_sc)->mtx)
256#define IXL_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
257#define IXL_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
258#define IXL_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->mtx)
259#define IXL_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
260
261#define IXL_RX_LOCK(_sc) mtx_lock(&(_sc)->mtx)
262#define IXL_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
263#define IXL_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
264
265/*
266 *****************************************************************************
267 * vendor_info_array
268 *
269 * This array contains the list of Subvendor/Subdevice IDs on which the driver
270 * should load.
271 *
272 *****************************************************************************
273 */
274typedef struct _ixl_vendor_info_t {
275 unsigned int vendor_id;
276 unsigned int device_id;
277 unsigned int subvendor_id;
278 unsigned int subdevice_id;
279 unsigned int index;
280} ixl_vendor_info_t;
281
282
283struct ixl_tx_buf {
284 u32 eop_index;
285 struct mbuf *m_head;
286 bus_dmamap_t map;
287 bus_dma_tag_t tag;
288};
289
290struct ixl_rx_buf {
291 struct mbuf *m_head;
292 struct mbuf *m_pack;
293 struct mbuf *fmp;
294 bus_dmamap_t hmap;
295 bus_dmamap_t pmap;
296#ifdef DEV_NETMAP
297 u64 addr;
298#endif
299};
300
301/*
302** This struct has multiple uses, multicast
303** addresses, vlans, and mac filters all use it.
304*/
305struct ixl_mac_filter {
306 SLIST_ENTRY(ixl_mac_filter) next;
307 u8 macaddr[ETHER_ADDR_LEN];
308 s16 vlan;
309 u16 flags;
310};
311
312
313/*
314 * The Transmit ring control struct
315 */
316struct tx_ring {
317 struct ixl_queue *que;
318 struct mtx mtx;
319 u32 tail;
320 struct i40e_tx_desc *base;
321 struct i40e_dma_mem dma;
322 u16 next_avail;
323 u16 next_to_clean;
324 u16 atr_rate;
325 u16 atr_count;
326 u16 itr;
327 u16 latency;
328 struct ixl_tx_buf *buffers;
329 volatile u16 avail;
330 u32 cmd;
331 bus_dma_tag_t tx_tag;
332 bus_dma_tag_t tso_tag;
333 char mtx_name[16];
334 struct buf_ring *br;
335
336 /* Used for Dynamic ITR calculation */
337 u32 packets;
338 u32 bytes;
339
340 /* Soft Stats */
341 u64 tx_bytes;
342 u64 no_desc;
343 u64 total_packets;
344};
345
346
347/*
348 * The Receive ring control struct
349 */
350struct rx_ring {
351 struct ixl_queue *que;
352 struct mtx mtx;
353 union i40e_rx_desc *base;
354 struct i40e_dma_mem dma;
355 struct lro_ctrl lro;
356 bool lro_enabled;
357 bool hdr_split;
358 bool discard;
359 u16 next_refresh;
360 u16 next_check;
361 u16 itr;
362 u16 latency;
363 char mtx_name[16];
364 struct ixl_rx_buf *buffers;
365 u32 mbuf_sz;
366 u32 tail;
367 bus_dma_tag_t htag;
368 bus_dma_tag_t ptag;
369
370 /* Used for Dynamic ITR calculation */
371 u32 packets;
372 u32 bytes;
373
374 /* Soft stats */
375 u64 split;
376 u64 rx_packets;
377 u64 rx_bytes;
378 u64 discarded;
379 u64 not_done;
380};
381
382/*
383** Driver queue struct: this is the interrupt container
384** for the associated tx and rx ring pair.
385*/
386struct ixl_queue {
387 struct ixl_vsi *vsi;
388 u32 me;
389 u32 msix; /* This queue's MSIX vector */
390 u32 eims; /* This queue's EIMS bit */
391 struct resource *res;
392 void *tag;
393 int num_desc; /* both tx and rx */
394 int busy;
395 struct tx_ring txr;
396 struct rx_ring rxr;
397 struct task task;
398 struct task tx_task;
399 struct taskqueue *tq;
400
401 /* Queue stats */
402 u64 irqs;
403 u64 tso;
404 u64 mbuf_defrag_failed;
405 u64 mbuf_hdr_failed;
406 u64 mbuf_pkt_failed;
407 u64 tx_map_avail;
408 u64 tx_dma_setup;
409 u64 dropped_pkts;
410};
411
412/*
413** Virtual Station interface:
414** there would be one of these per traffic class/type
415** for now just one, and its embedded in the pf
416*/
417SLIST_HEAD(ixl_ftl_head, ixl_mac_filter);
418struct ixl_vsi {
419 void *back;
420 struct ifnet *ifp;
421 struct device *dev;
422 struct i40e_hw *hw;
423 struct ifmedia media;
424 u64 que_mask;
425 int id;
426 u16 msix_base; /* station base MSIX vector */
427 u16 num_queues;
428 u16 rx_itr_setting;
429 u16 tx_itr_setting;
430 struct ixl_queue *queues; /* head of queues */
431 bool link_active;
432 u16 seid;
433 u16 max_frame_size;
434 u32 link_speed;
435 bool link_up;
436 u32 fc; /* local flow ctrl setting */
437
438 /* MAC/VLAN Filter list */
439 struct ixl_ftl_head ftl;
440
441 struct i40e_aqc_vsi_properties_data info;
442
443 eventhandler_tag vlan_attach;
444 eventhandler_tag vlan_detach;
445 u16 num_vlans;
446
447 /* Per-VSI stats from hardware */
448 struct i40e_eth_stats eth_stats;
449 struct i40e_eth_stats eth_stats_offsets;
450 bool stat_offsets_loaded;
451
452 /* Driver statistics */
453 u64 hw_filters_del;
454 u64 hw_filters_add;
455
456 /* Misc. */
457 u64 active_queues;
458 u64 flags;
459};
460
461/*
462** Find the number of unrefreshed RX descriptors
463*/
464static inline u16
465ixl_rx_unrefreshed(struct ixl_queue *que)
466{
467 struct rx_ring *rxr = &que->rxr;
468
469 if (rxr->next_check > rxr->next_refresh)
470 return (rxr->next_check - rxr->next_refresh - 1);
471 else
472 return ((que->num_desc + rxr->next_check) -
473 rxr->next_refresh - 1);
474}
475
476/*
477** Find the next available unused filter
478*/
479static inline struct ixl_mac_filter *
480ixl_get_filter(struct ixl_vsi *vsi)
481{
482 struct ixl_mac_filter *f;
483
484 /* create a new empty filter */
485 f = malloc(sizeof(struct ixl_mac_filter),
486 M_DEVBUF, M_NOWAIT | M_ZERO);
487 SLIST_INSERT_HEAD(&vsi->ftl, f, next);
488
489 return (f);
490}
491
492/*
493** Compare two ethernet addresses
494*/
495static inline bool
496cmp_etheraddr(u8 *ea1, u8 *ea2)
497{
498 bool cmp = FALSE;
499
500 if ((ea1[0] == ea2[0]) && (ea1[1] == ea2[1]) &&
501 (ea1[2] == ea2[2]) && (ea1[3] == ea2[3]) &&
502 (ea1[4] == ea2[4]) && (ea1[5] == ea2[5]))
503 cmp = TRUE;
504
505 return (cmp);
506}
507
508/*
509 * Info for stats sysctls
510 */
511struct ixl_sysctl_info {
512 u64 *stat;
513 char *name;
514 char *description;
515};
516
517extern int ixl_atr_rate;
518
519/*
520** ixl_fw_version_str - format the FW and NVM version strings
521*/
522static inline char *
523ixl_fw_version_str(struct i40e_hw *hw)
524{
525 static char buf[32];
526
527 snprintf(buf, sizeof(buf),
528 "f%d.%d a%d.%d n%02x.%02x e%08x",
529 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
530 hw->aq.api_maj_ver, hw->aq.api_min_ver,
531 (hw->nvm.version & IXL_NVM_VERSION_HI_MASK) >>
532 IXL_NVM_VERSION_HI_SHIFT,
533 (hw->nvm.version & IXL_NVM_VERSION_LO_MASK) >>
534 IXL_NVM_VERSION_LO_SHIFT,
535 hw->nvm.eetrack);
536 return buf;
537}
538
539/*********************************************************************
540 * TXRX Function prototypes
541 *********************************************************************/
542int ixl_allocate_tx_data(struct ixl_queue *);
543int ixl_allocate_rx_data(struct ixl_queue *);
544void ixl_init_tx_ring(struct ixl_queue *);
545int ixl_init_rx_ring(struct ixl_queue *);
546bool ixl_rxeof(struct ixl_queue *, int);
547bool ixl_txeof(struct ixl_queue *);
548int ixl_mq_start(struct ifnet *, struct mbuf *);
549int ixl_mq_start_locked(struct ifnet *, struct tx_ring *);
550void ixl_deferred_mq_start(void *, int);
551void ixl_qflush(struct ifnet *);
552void ixl_free_vsi(struct ixl_vsi *);
553void ixl_free_que_tx(struct ixl_queue *);
554void ixl_free_que_rx(struct ixl_queue *);
555#ifdef IXL_FDIR
556void ixl_atr(struct ixl_queue *, struct tcphdr *, int);
557#endif
558
559#endif /* _IXL_H_ */