ixl.h (9f99061e) | ixl.h (61ae650d) |
---|---|
1/****************************************************************************** 2 | 1/****************************************************************************** 2 |
3 Copyright (c) 2013-2018, Intel Corporation | 3 Copyright (c) 2013-2014, Intel Corporation |
4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 15 unchanged lines hidden (view full) --- 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 | 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 15 unchanged lines hidden (view full) --- 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 |
35 |
|
35#ifndef _IXL_H_ 36#define _IXL_H_ 37 | 36#ifndef _IXL_H_ 37#define _IXL_H_ 38 |
38#include "opt_inet.h" 39#include "opt_inet6.h" 40#include "opt_rss.h" 41#include "opt_ixl.h" | |
42 43#include <sys/param.h> 44#include <sys/systm.h> 45#include <sys/buf_ring.h> 46#include <sys/mbuf.h> 47#include <sys/protosw.h> 48#include <sys/socket.h> 49#include <sys/malloc.h> 50#include <sys/kernel.h> 51#include <sys/module.h> 52#include <sys/sockio.h> | 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/buf_ring.h> 43#include <sys/mbuf.h> 44#include <sys/protosw.h> 45#include <sys/socket.h> 46#include <sys/malloc.h> 47#include <sys/kernel.h> 48#include <sys/module.h> 49#include <sys/sockio.h> |
53#include <sys/eventhandler.h> 54#include <sys/syslog.h> 55#include <sys/priv.h> 56#include <sys/bitstring.h> | |
57 58#include <net/if.h> | 50 51#include <net/if.h> |
59#include <net/if_var.h> | |
60#include <net/if_arp.h> 61#include <net/bpf.h> 62#include <net/ethernet.h> 63#include <net/if_dl.h> 64#include <net/if_media.h> | 52#include <net/if_arp.h> 53#include <net/bpf.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> |
65#include <net/iflib.h> | |
66 67#include <net/bpf.h> 68#include <net/if_types.h> 69#include <net/if_vlan_var.h> 70 71#include <netinet/in_systm.h> 72#include <netinet/in.h> 73#include <netinet/if_ether.h> --- 16 unchanged lines hidden (view full) --- 90#include <dev/pci/pcivar.h> 91#include <dev/pci/pcireg.h> 92#include <sys/proc.h> 93#include <sys/sysctl.h> 94#include <sys/endian.h> 95#include <sys/taskqueue.h> 96#include <sys/pcpu.h> 97#include <sys/smp.h> | 57 58#include <net/bpf.h> 59#include <net/if_types.h> 60#include <net/if_vlan_var.h> 61 62#include <netinet/in_systm.h> 63#include <netinet/in.h> 64#include <netinet/if_ether.h> --- 16 unchanged lines hidden (view full) --- 81#include <dev/pci/pcivar.h> 82#include <dev/pci/pcireg.h> 83#include <sys/proc.h> 84#include <sys/sysctl.h> 85#include <sys/endian.h> 86#include <sys/taskqueue.h> 87#include <sys/pcpu.h> 88#include <sys/smp.h> |
98#include <sys/sbuf.h> | |
99#include <machine/smp.h> | 89#include <machine/smp.h> |
100#include <machine/stdarg.h> | |
101 | 90 |
102#ifdef RSS 103#include <net/rss_config.h> 104#include <netinet/in_rss.h> 105#endif 106 107#include "ifdi_if.h" | |
108#include "i40e_type.h" 109#include "i40e_prototype.h" | 91#include "i40e_type.h" 92#include "i40e_prototype.h" |
110#include "ixl_debug.h" | |
111 | 93 |
112#define PVIDV(vendor, devid, name) \ 113 PVID(vendor, devid, name " - " IXL_DRIVER_VERSION_STRING) | 94#ifdef IXL_DEBUG 95#include <sys/sbuf.h> |
114 | 96 |
97#define MAC_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x" 98#define MAC_FORMAT_ARGS(mac_addr) \ 99 (mac_addr)[0], (mac_addr)[1], (mac_addr)[2], (mac_addr)[3], \ 100 (mac_addr)[4], (mac_addr)[5] 101#define ON_OFF_STR(is_set) ((is_set) ? "On" : "Off") 102 103 104#define _DBG_PRINTF(S, ...) printf("%s: " S "\n", __func__, ##__VA_ARGS__) 105#define _DEV_DBG_PRINTF(dev, S, ...) device_printf(dev, "%s: " S "\n", __func__, ##__VA_ARGS__) 106#define _IF_DBG_PRINTF(ifp, S, ...) if_printf(ifp, "%s: " S "\n", __func__, ##__VA_ARGS__) 107 108/* Defines for printing generic debug information */ 109#define DPRINTF(...) _DBG_PRINTF(__VA_ARGS__) 110#define DDPRINTF(...) _DEV_DBG_PRINTF(__VA_ARGS__) 111#define IDPRINTF(...) _IF_DBG_PRINTF(__VA_ARGS__) 112 113/* Defines for printing specific debug information */ 114#define DEBUG_INIT 1 115#define DEBUG_IOCTL 1 116#define DEBUG_HW 1 117 118#define INIT_DEBUGOUT(...) if (DEBUG_INIT) _DBG_PRINTF(__VA_ARGS__) 119#define INIT_DBG_DEV(...) if (DEBUG_INIT) _DEV_DBG_PRINTF(__VA_ARGS__) 120#define INIT_DBG_IF(...) if (DEBUG_INIT) _IF_DBG_PRINTF(__VA_ARGS__) 121 122#define IOCTL_DEBUGOUT(...) if (DEBUG_IOCTL) _DBG_PRINTF(__VA_ARGS__) 123#define IOCTL_DBG_IF2(ifp, S, ...) if (DEBUG_IOCTL) \ 124 if_printf(ifp, S "\n", ##__VA_ARGS__) 125#define IOCTL_DBG_IF(...) if (DEBUG_IOCTL) _IF_DBG_PRINTF(__VA_ARGS__) 126 127#define HW_DEBUGOUT(...) if (DEBUG_HW) _DBG_PRINTF(__VA_ARGS__) 128 129#else 130#define DEBUG_INIT 0 131#define DEBUG_IOCTL 0 132#define DEBUG_HW 0 133 134#define DPRINTF(...) 135#define DDPRINTF(...) 136#define IDPRINTF(...) 137 138#define INIT_DEBUGOUT(...) 139#define INIT_DBG_DEV(...) 140#define INIT_DBG_IF(...) 141#define IOCTL_DEBUGOUT(...) 142#define IOCTL_DBG_IF2(...) 143#define IOCTL_DBG_IF(...) 144#define HW_DEBUGOUT(...) 145#endif 146 |
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115/* Tunables */ 116 117/* 118 * Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the 119 * number of tx/rx descriptors allocated by the driver. Increasing this | 147/* Tunables */ 148 149/* 150 * Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the 151 * number of tx/rx descriptors allocated by the driver. Increasing this |
120 * value allows the driver to queue more operations. 121 * 122 * Tx descriptors are always 16 bytes, but Rx descriptors can be 32 bytes. 123 * The driver currently always uses 32 byte Rx descriptors. | 152 * value allows the driver to queue more operations. Each descriptor is 16 153 * or 32 bytes (configurable in FVL) |
124 */ | 154 */ |
125#define IXL_DEFAULT_RING 1024 126#define IXL_MAX_RING 4096 127#define IXL_MIN_RING 64 128#define IXL_RING_INCREMENT 32 | 155#define DEFAULT_RING 1024 156#define PERFORM_RING 2048 157#define MAX_RING 4096 158#define MIN_RING 32 |
129 | 159 |
130#define IXL_AQ_LEN 256 131#define IXL_AQ_LEN_MAX 1024 | 160/* 161** Default number of entries in Tx queue buf_ring. 162*/ 163#define DEFAULT_TXBRSZ (4096 * 4096) |
132 133/* Alignment for rings */ | 164 165/* Alignment for rings */ |
134#define DBA_ALIGN 128 | 166#define DBA_ALIGN 128 |
135 | 167 |
168/* 169 * This parameter controls the maximum no of times the driver will loop in 170 * the isr. Minimum Value = 1 171 */ 172#define MAX_LOOP 10 173 174/* 175 * This is the max watchdog interval, ie. the time that can 176 * pass between any two TX clean operations, such only happening 177 * when the TX hardware is functioning. 178 */ 179#define IXL_WATCHDOG (10 * hz) 180 181/* 182 * This parameters control when the driver calls the routine to reclaim 183 * transmit descriptors. 184 */ 185#define IXL_TX_CLEANUP_THRESHOLD (que->num_desc / 8) 186#define IXL_TX_OP_THRESHOLD (que->num_desc / 32) 187 188/* Flow control constants */ 189#define IXL_FC_PAUSE 0xFFFF 190#define IXL_FC_HI 0x20000 191#define IXL_FC_LO 0x10000 192 |
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136#define MAX_MULTICAST_ADDR 128 137 | 193#define MAX_MULTICAST_ADDR 128 194 |
138#define IXL_MSIX_BAR 3 | 195#define IXL_BAR 3 |
139#define IXL_ADM_LIMIT 2 | 196#define IXL_ADM_LIMIT 2 |
140#define IXL_TSO_SIZE ((255*1024)-1) | 197#define IXL_TSO_SIZE 65535 |
141#define IXL_TX_BUF_SZ ((u32) 1514) 142#define IXL_AQ_BUF_SZ ((u32) 4096) | 198#define IXL_TX_BUF_SZ ((u32) 1514) 199#define IXL_AQ_BUF_SZ ((u32) 4096) |
200#define IXL_RX_HDR 128 201#define IXL_AQ_LEN 256 202#define IXL_AQ_BUFSZ 4096 203#define IXL_RX_LIMIT 512 |
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143#define IXL_RX_ITR 0 144#define IXL_TX_ITR 1 145#define IXL_ITR_NONE 3 146#define IXL_QUEUE_EOL 0x7FF | 204#define IXL_RX_ITR 0 205#define IXL_TX_ITR 1 206#define IXL_ITR_NONE 3 207#define IXL_QUEUE_EOL 0x7FF |
147#define IXL_MIN_FRAME 17 148#define IXL_MAX_FRAME 9728 149#define IXL_MAX_TX_SEGS 8 150#define IXL_MAX_RX_SEGS 5 151#define IXL_MAX_TSO_SEGS 128 152#define IXL_SPARSE_CHAIN 7 153#define IXL_MIN_TSO_MSS 64 154#define IXL_MAX_TSO_MSS 9668 155#define IXL_MAX_DMA_SEG_SIZE ((16 * 1024) - 1) | 208#define IXL_MAX_FRAME 0x2600 209#define IXL_MAX_TX_SEGS 8 210#define IXL_MAX_TSO_SEGS 66 211#define IXL_SPARSE_CHAIN 6 212#define IXL_QUEUE_HUNG 0x80000000 |
156 | 213 |
157#define IXL_RSS_KEY_SIZE_REG 13 158#define IXL_RSS_KEY_SIZE (IXL_RSS_KEY_SIZE_REG * 4) 159#define IXL_RSS_VSI_LUT_SIZE 64 /* X722 -> VSI, X710 -> VF */ 160#define IXL_RSS_VSI_LUT_ENTRY_MASK 0x3F 161#define IXL_RSS_VF_LUT_ENTRY_MASK 0xF | 214/* ERJ: hardware can support ~1.5k filters between all functions */ 215#define IXL_MAX_FILTERS 256 216#define IXL_MAX_TX_BUSY 10 |
162 | 217 |
163#define IXL_VF_MAX_BUFFER 0x3F80 164#define IXL_VF_MAX_HDR_BUFFER 0x840 165#define IXL_VF_MAX_FRAME 0x3FFF 166 167/* ERJ: hardware can support ~2k (SW5+) filters between all functions */ 168#define IXL_MAX_FILTERS 256 169 | |
170#define IXL_NVM_VERSION_LO_SHIFT 0 171#define IXL_NVM_VERSION_LO_MASK (0xff << IXL_NVM_VERSION_LO_SHIFT) 172#define IXL_NVM_VERSION_HI_SHIFT 12 173#define IXL_NVM_VERSION_HI_MASK (0xf << IXL_NVM_VERSION_HI_SHIFT) 174 | 218#define IXL_NVM_VERSION_LO_SHIFT 0 219#define IXL_NVM_VERSION_LO_MASK (0xff << IXL_NVM_VERSION_LO_SHIFT) 220#define IXL_NVM_VERSION_HI_SHIFT 12 221#define IXL_NVM_VERSION_HI_MASK (0xf << IXL_NVM_VERSION_HI_SHIFT) 222 |
223 |
|
175/* | 224/* |
176 * Interrupt Moderation parameters 177 * Multiply ITR values by 2 for real ITR value | 225 * Interrupt Moderation parameters |
178 */ | 226 */ |
179#define IXL_MAX_ITR 0x0FF0 | 227#define IXL_MAX_ITR 0x07FF |
180#define IXL_ITR_100K 0x0005 181#define IXL_ITR_20K 0x0019 182#define IXL_ITR_8K 0x003E 183#define IXL_ITR_4K 0x007A | 228#define IXL_ITR_100K 0x0005 229#define IXL_ITR_20K 0x0019 230#define IXL_ITR_8K 0x003E 231#define IXL_ITR_4K 0x007A |
184#define IXL_ITR_1K 0x01F4 | |
185#define IXL_ITR_DYNAMIC 0x8000 186#define IXL_LOW_LATENCY 0 187#define IXL_AVE_LATENCY 1 188#define IXL_BULK_LATENCY 2 189 190/* MacVlan Flags */ | 232#define IXL_ITR_DYNAMIC 0x8000 233#define IXL_LOW_LATENCY 0 234#define IXL_AVE_LATENCY 1 235#define IXL_BULK_LATENCY 2 236 237/* MacVlan Flags */ |
191#define IXL_FILTER_VLAN (u16)(1 << 0) 192#define IXL_FILTER_MC (u16)(1 << 1) | 238#define IXL_FILTER_USED (u16)(1 << 0) 239#define IXL_FILTER_VLAN (u16)(1 << 1) 240#define IXL_FILTER_ADD (u16)(1 << 2) 241#define IXL_FILTER_DEL (u16)(1 << 3) 242#define IXL_FILTER_MC (u16)(1 << 4) |
193 194/* used in the vlan field of the filter when not a vlan */ 195#define IXL_VLAN_ANY -1 196 | 243 244/* used in the vlan field of the filter when not a vlan */ 245#define IXL_VLAN_ANY -1 246 |
197/* Maximum number of MAC/VLAN filters supported by HW */ 198#define IXL_MAX_VLAN_FILTERS 256 199 | |
200#define CSUM_OFFLOAD_IPV4 (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 201#define CSUM_OFFLOAD_IPV6 (CSUM_TCP_IPV6|CSUM_UDP_IPV6|CSUM_SCTP_IPV6) 202#define CSUM_OFFLOAD (CSUM_OFFLOAD_IPV4|CSUM_OFFLOAD_IPV6|CSUM_TSO) 203 204/* Misc flags for ixl_vsi.flags */ 205#define IXL_FLAGS_KEEP_TSO4 (1 << 0) 206#define IXL_FLAGS_KEEP_TSO6 (1 << 1) | 247#define CSUM_OFFLOAD_IPV4 (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 248#define CSUM_OFFLOAD_IPV6 (CSUM_TCP_IPV6|CSUM_UDP_IPV6|CSUM_SCTP_IPV6) 249#define CSUM_OFFLOAD (CSUM_OFFLOAD_IPV4|CSUM_OFFLOAD_IPV6|CSUM_TSO) 250 251/* Misc flags for ixl_vsi.flags */ 252#define IXL_FLAGS_KEEP_TSO4 (1 << 0) 253#define IXL_FLAGS_KEEP_TSO6 (1 << 1) |
207#define IXL_FLAGS_USES_MSIX (1 << 2) 208#define IXL_FLAGS_IS_VF (1 << 3) | |
209 | 254 |
210#define IXL_VSI_IS_PF(v) ((v->flags & IXL_FLAGS_IS_VF) == 0) 211#define IXL_VSI_IS_VF(v) ((v->flags & IXL_FLAGS_IS_VF) != 0) | 255#define IXL_TX_LOCK(_sc) mtx_lock(&(_sc)->mtx) 256#define IXL_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 257#define IXL_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 258#define IXL_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->mtx) 259#define IXL_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) |
212 | 260 |
213#define IXL_VF_RESET_TIMEOUT 100 | 261#define IXL_RX_LOCK(_sc) mtx_lock(&(_sc)->mtx) 262#define IXL_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 263#define IXL_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) |
214 | 264 |
215#define IXL_VSI_DATA_PORT 0x01 216 217#define IAVF_MAX_QUEUES 16 218#define IXL_MAX_VSI_QUEUES (2 * (I40E_VSILAN_QTABLE_MAX_INDEX + 1)) 219 220#define IXL_RX_CTX_BASE_UNITS 128 221#define IXL_TX_CTX_BASE_UNITS 128 222 223#define IXL_PF_PCI_CIAA_VF_DEVICE_STATUS 0xAA 224 225#define IXL_PF_PCI_CIAD_VF_TRANS_PENDING_MASK 0x20 226 227#define IXL_GLGEN_VFLRSTAT_INDEX(glb_vf) ((glb_vf) / 32) 228#define IXL_GLGEN_VFLRSTAT_MASK(glb_vf) (1 << ((glb_vf) % 32)) 229 230#define IXL_MAX_ITR_IDX 3 231 232#define IXL_END_OF_INTR_LNKLST 0x7FF 233 234#define IXL_DEFAULT_RSS_HENA_BASE (\ 235 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 236 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 237 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 238 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 239 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 240 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 241 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 242 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 243 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 244 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 245 BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) 246 247#define IXL_DEFAULT_RSS_HENA_XL710 IXL_DEFAULT_RSS_HENA_BASE 248 249#define IXL_DEFAULT_RSS_HENA_X722 (\ 250 IXL_DEFAULT_RSS_HENA_BASE | \ 251 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ 252 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ 253 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ 254 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ 255 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ 256 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK)) 257 258#define IXL_CAPS \ 259 (IFCAP_TSO4 | IFCAP_TSO6 | \ 260 IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6 | \ 261 IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6 | \ 262 IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO | \ 263 IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM | \ 264 IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU | IFCAP_LRO) 265 266#define IXL_CSUM_TCP \ 267 (CSUM_IP_TCP|CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP6_TCP) 268#define IXL_CSUM_UDP \ 269 (CSUM_IP_UDP|CSUM_IP6_UDP) 270#define IXL_CSUM_SCTP \ 271 (CSUM_IP_SCTP|CSUM_IP6_SCTP) 272#define IXL_CSUM_IPV4 \ 273 (CSUM_IP|CSUM_IP_TSO) 274 275/* Pre-11 counter(9) compatibility */ 276#if __FreeBSD_version >= 1100036 277#define IXL_SET_IPACKETS(vsi, count) (vsi)->ipackets = (count) 278#define IXL_SET_IERRORS(vsi, count) (vsi)->ierrors = (count) 279#define IXL_SET_OPACKETS(vsi, count) (vsi)->opackets = (count) 280#define IXL_SET_OERRORS(vsi, count) (vsi)->oerrors = (count) 281#define IXL_SET_COLLISIONS(vsi, count) /* Do nothing; collisions is always 0. */ 282#define IXL_SET_IBYTES(vsi, count) (vsi)->ibytes = (count) 283#define IXL_SET_OBYTES(vsi, count) (vsi)->obytes = (count) 284#define IXL_SET_IMCASTS(vsi, count) (vsi)->imcasts = (count) 285#define IXL_SET_OMCASTS(vsi, count) (vsi)->omcasts = (count) 286#define IXL_SET_IQDROPS(vsi, count) (vsi)->iqdrops = (count) 287#define IXL_SET_OQDROPS(vsi, count) (vsi)->oqdrops = (count) 288#define IXL_SET_NOPROTO(vsi, count) (vsi)->noproto = (count) 289#else 290#define IXL_SET_IPACKETS(vsi, count) (vsi)->ifp->if_ipackets = (count) 291#define IXL_SET_IERRORS(vsi, count) (vsi)->ifp->if_ierrors = (count) 292#define IXL_SET_OPACKETS(vsi, count) (vsi)->ifp->if_opackets = (count) 293#define IXL_SET_OERRORS(vsi, count) (vsi)->ifp->if_oerrors = (count) 294#define IXL_SET_COLLISIONS(vsi, count) (vsi)->ifp->if_collisions = (count) 295#define IXL_SET_IBYTES(vsi, count) (vsi)->ifp->if_ibytes = (count) 296#define IXL_SET_OBYTES(vsi, count) (vsi)->ifp->if_obytes = (count) 297#define IXL_SET_IMCASTS(vsi, count) (vsi)->ifp->if_imcasts = (count) 298#define IXL_SET_OMCASTS(vsi, count) (vsi)->ifp->if_omcasts = (count) 299#define IXL_SET_IQDROPS(vsi, count) (vsi)->ifp->if_iqdrops = (count) 300#define IXL_SET_OQDROPS(vsi, odrops) (vsi)->ifp->if_snd.ifq_drops = (odrops) 301#define IXL_SET_NOPROTO(vsi, count) (vsi)->noproto = (count) 302#endif 303 304/* For stats sysctl naming */ 305#define IXL_QUEUE_NAME_LEN 32 306 307MALLOC_DECLARE(M_IXL); 308 309#define IXL_DEV_ERR(_dev, _format, ...) \ 310 device_printf(_dev, "%s: " _format " (%s:%d)\n", __func__, ##__VA_ARGS__, __FILE__, __LINE__) 311 | |
312/* 313 ***************************************************************************** 314 * vendor_info_array | 265/* 266 ***************************************************************************** 267 * vendor_info_array |
315 * | 268 * |
316 * This array contains the list of Subvendor/Subdevice IDs on which the driver 317 * should load. | 269 * This array contains the list of Subvendor/Subdevice IDs on which the driver 270 * should load. |
318 * | 271 * |
319 ***************************************************************************** 320 */ 321typedef struct _ixl_vendor_info_t { 322 unsigned int vendor_id; 323 unsigned int device_id; 324 unsigned int subvendor_id; 325 unsigned int subdevice_id; 326 unsigned int index; 327} ixl_vendor_info_t; 328 | 272 ***************************************************************************** 273 */ 274typedef struct _ixl_vendor_info_t { 275 unsigned int vendor_id; 276 unsigned int device_id; 277 unsigned int subvendor_id; 278 unsigned int subdevice_id; 279 unsigned int index; 280} ixl_vendor_info_t; 281 |
282 283struct ixl_tx_buf { 284 u32 eop_index; 285 struct mbuf *m_head; 286 bus_dmamap_t map; 287 bus_dma_tag_t tag; 288}; 289 290struct ixl_rx_buf { 291 struct mbuf *m_head; 292 struct mbuf *m_pack; 293 struct mbuf *fmp; 294 bus_dmamap_t hmap; 295 bus_dmamap_t pmap; 296#ifdef DEV_NETMAP 297 u64 addr; 298#endif 299}; 300 |
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329/* 330** This struct has multiple uses, multicast 331** addresses, vlans, and mac filters all use it. 332*/ 333struct ixl_mac_filter { | 301/* 302** This struct has multiple uses, multicast 303** addresses, vlans, and mac filters all use it. 304*/ 305struct ixl_mac_filter { |
334 LIST_ENTRY(ixl_mac_filter) ftle; | 306 SLIST_ENTRY(ixl_mac_filter) next; |
335 u8 macaddr[ETHER_ADDR_LEN]; 336 s16 vlan; 337 u16 flags; 338}; 339 | 307 u8 macaddr[ETHER_ADDR_LEN]; 308 s16 vlan; 309 u16 flags; 310}; 311 |
312 |
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340/* 341 * The Transmit ring control struct 342 */ 343struct tx_ring { | 313/* 314 * The Transmit ring control struct 315 */ 316struct tx_ring { |
344 struct ixl_tx_queue *que; | 317 struct ixl_queue *que; 318 struct mtx mtx; |
345 u32 tail; | 319 u32 tail; |
346 struct i40e_tx_desc *tx_base; 347 u64 tx_paddr; 348 u32 latency; 349 u32 packets; 350 u32 me; 351 /* 352 * For reporting completed packet status 353 * in descriptor writeback mode 354 */ 355 qidx_t *tx_rsq; 356 qidx_t tx_rs_cidx; 357 qidx_t tx_rs_pidx; 358 qidx_t tx_cidx_processed; | 320 struct i40e_tx_desc *base; 321 struct i40e_dma_mem dma; 322 u16 next_avail; 323 u16 next_to_clean; 324 u16 atr_rate; 325 u16 atr_count; 326 u16 itr; 327 u16 latency; 328 struct ixl_tx_buf *buffers; 329 volatile u16 avail; 330 u32 cmd; 331 bus_dma_tag_t tx_tag; 332 bus_dma_tag_t tso_tag; 333 char mtx_name[16]; 334 struct buf_ring *br; |
359 360 /* Used for Dynamic ITR calculation */ | 335 336 /* Used for Dynamic ITR calculation */ |
361 u32 itr; | 337 u32 packets; |
362 u32 bytes; 363 364 /* Soft Stats */ 365 u64 tx_bytes; | 338 u32 bytes; 339 340 /* Soft Stats */ 341 u64 tx_bytes; |
366 u64 tx_packets; 367 u64 mss_too_small; | 342 u64 no_desc; 343 u64 total_packets; |
368}; 369 370 371/* 372 * The Receive ring control struct 373 */ 374struct rx_ring { | 344}; 345 346 347/* 348 * The Receive ring control struct 349 */ 350struct rx_ring { |
375 struct ixl_rx_queue *que; 376 union i40e_rx_desc *rx_base; 377 uint64_t rx_paddr; | 351 struct ixl_queue *que; 352 struct mtx mtx; 353 union i40e_rx_desc *base; 354 struct i40e_dma_mem dma; 355 struct lro_ctrl lro; 356 bool lro_enabled; 357 bool hdr_split; |
378 bool discard; | 358 bool discard; |
379 u32 itr; 380 u32 latency; | 359 u16 next_refresh; 360 u16 next_check; 361 u16 itr; 362 u16 latency; 363 char mtx_name[16]; 364 struct ixl_rx_buf *buffers; |
381 u32 mbuf_sz; 382 u32 tail; | 365 u32 mbuf_sz; 366 u32 tail; |
383 u32 me; | 367 bus_dma_tag_t htag; 368 bus_dma_tag_t ptag; |
384 385 /* Used for Dynamic ITR calculation */ 386 u32 packets; 387 u32 bytes; 388 389 /* Soft stats */ | 369 370 /* Used for Dynamic ITR calculation */ 371 u32 packets; 372 u32 bytes; 373 374 /* Soft stats */ |
375 u64 split; |
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390 u64 rx_packets; 391 u64 rx_bytes; | 376 u64 rx_packets; 377 u64 rx_bytes; |
392 u64 desc_errs; 393 u64 csum_errs; | 378 u64 discarded; 379 u64 not_done; |
394}; 395 396/* | 380}; 381 382/* |
397** Driver queue structs | 383** Driver queue struct: this is the interrupt container 384** for the associated tx and rx ring pair. |
398*/ | 385*/ |
399struct ixl_tx_queue { | 386struct ixl_queue { |
400 struct ixl_vsi *vsi; | 387 struct ixl_vsi *vsi; |
388 u32 me; 389 u32 msix; /* This queue's MSIX vector */ 390 u32 eims; /* This queue's EIMS bit */ 391 struct resource *res; 392 void *tag; 393 int num_desc; /* both tx and rx */ 394 int busy; |
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401 struct tx_ring txr; | 395 struct tx_ring txr; |
402 struct if_irq que_irq; 403 u32 msix; 404 /* Stats */ | 396 struct rx_ring rxr; 397 struct task task; 398 struct task tx_task; 399 struct taskqueue *tq; 400 401 /* Queue stats */ |
405 u64 irqs; 406 u64 tso; | 402 u64 irqs; 403 u64 tso; |
404 u64 mbuf_defrag_failed; 405 u64 mbuf_hdr_failed; 406 u64 mbuf_pkt_failed; 407 u64 tx_map_avail; 408 u64 tx_dma_setup; 409 u64 dropped_pkts; |
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407}; 408 | 410}; 411 |
409struct ixl_rx_queue { 410 struct ixl_vsi *vsi; 411 struct rx_ring rxr; 412 struct if_irq que_irq; 413 u32 msix; /* This queue's MSIX vector */ 414 /* Stats */ 415 u64 irqs; 416}; 417 | |
418/* | 412/* |
419** Virtual Station Interface | 413** Virtual Station interface: 414** there would be one of these per traffic class/type 415** for now just one, and its embedded in the pf |
420*/ | 416*/ |
421LIST_HEAD(ixl_ftl_head, ixl_mac_filter); | 417SLIST_HEAD(ixl_ftl_head, ixl_mac_filter); |
422struct ixl_vsi { | 418struct ixl_vsi { |
423 if_ctx_t ctx; 424 if_softc_ctx_t shared; | 419 void *back; |
425 struct ifnet *ifp; | 420 struct ifnet *ifp; |
426 device_t dev; | 421 struct device *dev; |
427 struct i40e_hw *hw; | 422 struct i40e_hw *hw; |
428 struct ifmedia *media; 429 430 int num_rx_queues; 431 int num_tx_queues; 432 433 void *back; 434 enum i40e_vsi_type type; | 423 struct ifmedia media; 424 u64 que_mask; |
435 int id; | 425 int id; |
436 u32 rx_itr_setting; 437 u32 tx_itr_setting; 438 bool enable_head_writeback; 439 440 u16 vsi_num; | 426 u16 msix_base; /* station base MSIX vector */ 427 u16 num_queues; 428 u16 rx_itr_setting; 429 u16 tx_itr_setting; 430 struct ixl_queue *queues; /* head of queues */ |
441 bool link_active; 442 u16 seid; | 431 bool link_active; 432 u16 seid; |
443 u16 uplink_seid; 444 u16 downlink_seid; 445 446 struct ixl_tx_queue *tx_queues; /* TX queue array */ 447 struct ixl_rx_queue *rx_queues; /* RX queue array */ 448 struct if_irq irq; | 433 u16 max_frame_size; |
449 u32 link_speed; | 434 u32 link_speed; |
435 bool link_up; 436 u32 fc; /* local flow ctrl setting */ |
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450 451 /* MAC/VLAN Filter list */ | 437 438 /* MAC/VLAN Filter list */ |
452 struct ixl_ftl_head ftl; 453 u16 num_macs; 454 u64 num_hw_filters; | 439 struct ixl_ftl_head ftl; |
455 | 440 |
456 /* Contains readylist & stat counter id */ | |
457 struct i40e_aqc_vsi_properties_data info; 458 | 441 struct i40e_aqc_vsi_properties_data info; 442 |
459#define IXL_VLANS_MAP_LEN EVL_VLID_MASK + 1 460 bitstr_t bit_decl(vlans_map, IXL_VLANS_MAP_LEN); | 443 eventhandler_tag vlan_attach; 444 eventhandler_tag vlan_detach; |
461 u16 num_vlans; 462 463 /* Per-VSI stats from hardware */ 464 struct i40e_eth_stats eth_stats; 465 struct i40e_eth_stats eth_stats_offsets; | 445 u16 num_vlans; 446 447 /* Per-VSI stats from hardware */ 448 struct i40e_eth_stats eth_stats; 449 struct i40e_eth_stats eth_stats_offsets; |
466 bool stat_offsets_loaded; 467 /* VSI stat counters */ 468 u64 ipackets; 469 u64 ierrors; 470 u64 opackets; 471 u64 oerrors; 472 u64 ibytes; 473 u64 obytes; 474 u64 imcasts; 475 u64 omcasts; 476 u64 iqdrops; 477 u64 oqdrops; 478 u64 noproto; | 450 bool stat_offsets_loaded; |
479 | 451 |
452 /* Driver statistics */ 453 u64 hw_filters_del; 454 u64 hw_filters_add; 455 |
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480 /* Misc. */ | 456 /* Misc. */ |
481 u64 flags; 482 /* Stats sysctls for this VSI */ 483 struct sysctl_oid *vsi_node; 484 struct sysctl_ctx_list sysctl_ctx; | 457 u64 active_queues; 458 u64 flags; |
485}; 486 | 459}; 460 |
487struct ixl_add_maddr_arg { 488 struct ixl_ftl_head to_add; 489 struct ixl_vsi *vsi; 490}; | 461/* 462** Find the number of unrefreshed RX descriptors 463*/ 464static inline u16 465ixl_rx_unrefreshed(struct ixl_queue *que) 466{ 467 struct rx_ring *rxr = &que->rxr; 468 469 if (rxr->next_check > rxr->next_refresh) 470 return (rxr->next_check - rxr->next_refresh - 1); 471 else 472 return ((que->num_desc + rxr->next_check) - 473 rxr->next_refresh - 1); 474} |
491 492/* | 475 476/* |
493** Compare two ethernet addresses | 477** Find the next available unused filter |
494*/ | 478*/ |
495static inline bool 496ixl_ether_is_equal(const u8 *ea1, const u8 *ea2) | 479static inline struct ixl_mac_filter * 480ixl_get_filter(struct ixl_vsi *vsi) |
497{ | 481{ |
498 return (bcmp(ea1, ea2, ETHER_ADDR_LEN) == 0); | 482 struct ixl_mac_filter *f; 483 484 /* create a new empty filter */ 485 f = malloc(sizeof(struct ixl_mac_filter), 486 M_DEVBUF, M_NOWAIT | M_ZERO); 487 SLIST_INSERT_HEAD(&vsi->ftl, f, next); 488 489 return (f); |
499} 500 501/* | 490} 491 492/* |
502 * Return next largest power of 2, unsigned 503 * 504 * Public domain, from Bit Twiddling Hacks 505 */ 506static inline u32 507next_power_of_two(u32 n) 508{ 509 n--; 510 n |= n >> 1; 511 n |= n >> 2; 512 n |= n >> 4; 513 n |= n >> 8; 514 n |= n >> 16; 515 n++; | 493** Compare two ethernet addresses 494*/ 495static inline bool 496cmp_etheraddr(u8 *ea1, u8 *ea2) 497{ 498 bool cmp = FALSE; |
516 | 499 |
517 /* Next power of two > 0 is 1 */ 518 n += (n == 0); | 500 if ((ea1[0] == ea2[0]) && (ea1[1] == ea2[1]) && 501 (ea1[2] == ea2[2]) && (ea1[3] == ea2[3]) && 502 (ea1[4] == ea2[4]) && (ea1[5] == ea2[5])) 503 cmp = TRUE; |
519 | 504 |
520 return (n); 521} | 505 return (cmp); 506} |
522 523/* 524 * Info for stats sysctls 525 */ 526struct ixl_sysctl_info { 527 u64 *stat; 528 char *name; 529 char *description; 530}; 531 | 507 508/* 509 * Info for stats sysctls 510 */ 511struct ixl_sysctl_info { 512 u64 *stat; 513 char *name; 514 char *description; 515}; 516 |
532extern const uint8_t ixl_bcast_addr[ETHER_ADDR_LEN]; | 517extern int ixl_atr_rate; |
533 | 518 |
534/* Common function prototypes between PF/VF driver */ 535void ixl_debug_core(device_t dev, u32 enabled_mask, u32 mask, char *fmt, ...); 536void ixl_init_tx_ring(struct ixl_vsi *vsi, struct ixl_tx_queue *que); 537void ixl_get_default_rss_key(u32 *); 538const char * i40e_vc_stat_str(struct i40e_hw *hw, 539 enum virtchnl_status_code stat_err); 540void ixl_init_tx_rsqs(struct ixl_vsi *vsi); 541void ixl_init_tx_cidx(struct ixl_vsi *vsi); 542u64 ixl_max_vc_speed_to_value(u8 link_speeds); 543void ixl_add_vsi_sysctls(device_t dev, struct ixl_vsi *vsi, 544 struct sysctl_ctx_list *ctx, const char *sysctl_name); 545void ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *ctx, 546 struct sysctl_oid_list *child, 547 struct i40e_eth_stats *eth_stats); 548void ixl_vsi_add_queues_stats(struct ixl_vsi *vsi, 549 struct sysctl_ctx_list *ctx); | 519/* 520** ixl_fw_version_str - format the FW and NVM version strings 521*/ 522static inline char * 523ixl_fw_version_str(struct i40e_hw *hw) 524{ 525 static char buf[32]; 526 527 snprintf(buf, sizeof(buf), 528 "f%d.%d a%d.%d n%02x.%02x e%08x", 529 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, 530 hw->aq.api_maj_ver, hw->aq.api_min_ver, 531 (hw->nvm.version & IXL_NVM_VERSION_HI_MASK) >> 532 IXL_NVM_VERSION_HI_SHIFT, 533 (hw->nvm.version & IXL_NVM_VERSION_LO_MASK) >> 534 IXL_NVM_VERSION_LO_SHIFT, 535 hw->nvm.eetrack); 536 return buf; 537} 538 539/********************************************************************* 540 * TXRX Function prototypes 541 *********************************************************************/ 542int ixl_allocate_tx_data(struct ixl_queue *); 543int ixl_allocate_rx_data(struct ixl_queue *); 544void ixl_init_tx_ring(struct ixl_queue *); 545int ixl_init_rx_ring(struct ixl_queue *); 546bool ixl_rxeof(struct ixl_queue *, int); 547bool ixl_txeof(struct ixl_queue *); 548int ixl_mq_start(struct ifnet *, struct mbuf *); 549int ixl_mq_start_locked(struct ifnet *, struct tx_ring *); 550void ixl_deferred_mq_start(void *, int); 551void ixl_qflush(struct ifnet *); 552void ixl_free_vsi(struct ixl_vsi *); 553void ixl_free_que_tx(struct ixl_queue *); 554void ixl_free_que_rx(struct ixl_queue *); 555#ifdef IXL_FDIR 556void ixl_atr(struct ixl_queue *, struct tcphdr *, int); 557#endif 558 |
550#endif /* _IXL_H_ */ | 559#endif /* _IXL_H_ */ |