efx_phy.c (685dc743) | efx_phy.c (e948693e) |
---|---|
1/*- | 1/*- |
2 * SPDX-License-Identifier: BSD-2-Clause | 2 * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved. |
3 * | 3 * |
4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * | |
7 * Redistribution and use in source and binary forms, with or without | 4 * Redistribution and use in source and binary forms, with or without |
8 * modification, are permitted provided that the following conditions are met: | 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. |
9 * | 12 * |
10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. | 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. |
31 */ 32 | 24 */ 25 |
33#include <sys/cdefs.h> | 26#include "efsys.h" |
34#include "efx.h" | 27#include "efx.h" |
28#include "efx_types.h" 29#include "efx_regs.h" |
|
35#include "efx_impl.h" | 30#include "efx_impl.h" |
31#if EFSYS_OPT_FALCON 32#include "falcon_nvram.h" 33#endif |
|
36 | 34 |
35#if EFSYS_OPT_MAC_FALCON_XMAC 36#include "falcon_xmac.h" 37#endif 38 39#if EFSYS_OPT_MAC_FALCON_GMAC 40#include "falcon_gmac.h" 41#endif 42 43#if EFSYS_OPT_PHY_NULL 44#include "nullphy.h" 45#endif 46 47#if EFSYS_OPT_PHY_QT2022C2 48#include "qt2022c2.h" 49#endif 50 51#if EFSYS_OPT_PHY_SFX7101 52#include "sfx7101.h" 53#endif 54 55#if EFSYS_OPT_PHY_TXC43128 56#include "txc43128.h" 57#endif 58 59#if EFSYS_OPT_PHY_SFT9001 60#include "sft9001.h" 61#endif 62 63#if EFSYS_OPT_PHY_QT2025C 64#include "qt2025c.h" 65#endif 66 67#if EFSYS_OPT_PHY_NULL 68static efx_phy_ops_t __cs __efx_phy_null_ops = { 69 NULL, /* epo_power */ 70 nullphy_reset, /* epo_reset */ 71 nullphy_reconfigure, /* epo_reconfigure */ 72 nullphy_verify, /* epo_verify */ 73 NULL, /* epo_uplink_check */ 74 nullphy_downlink_check, /* epo_downlink_check */ 75 nullphy_oui_get, /* epo_oui_get */ 76#if EFSYS_OPT_PHY_STATS 77 nullphy_stats_update, /* epo_stats_update */ 78#endif /* EFSYS_OPT_PHY_STATS */ 79#if EFSYS_OPT_PHY_PROPS 80#if EFSYS_OPT_NAMES 81 nullphy_prop_name, /* epo_prop_name */ 82#endif 83 nullphy_prop_get, /* epo_prop_get */ 84 nullphy_prop_set, /* epo_prop_set */ 85#endif /* EFSYS_OPT_PHY_PROPS */ 86#if EFSYS_OPT_PHY_BIST 87 NULL, /* epo_bist_start */ 88 NULL, /* epo_bist_poll */ 89 NULL, /* epo_bist_stop */ 90#endif /* EFSYS_OPT_PHY_BIST */ 91}; 92#endif /* EFSYS_OPT_PHY_NULL */ 93 94#if EFSYS_OPT_PHY_QT2022C2 95static efx_phy_ops_t __cs __efx_phy_qt2022c2_ops = { 96 NULL, /* epo_power */ 97 qt2022c2_reset, /* epo_reset */ 98 qt2022c2_reconfigure, /* epo_reconfigure */ 99 qt2022c2_verify, /* epo_verify */ 100 qt2022c2_uplink_check, /* epo_uplink_check */ 101 qt2022c2_downlink_check, /* epo_downlink_check */ 102 qt2022c2_oui_get, /* epo_oui_get */ 103#if EFSYS_OPT_PHY_STATS 104 qt2022c2_stats_update, /* epo_stats_update */ 105#endif /* EFSYS_OPT_PHY_STATS */ 106#if EFSYS_OPT_PHY_PROPS 107#if EFSYS_OPT_NAMES 108 qt2022c2_prop_name, /* epo_prop_name */ 109#endif 110 qt2022c2_prop_get, /* epo_prop_get */ 111 qt2022c2_prop_set, /* epo_prop_set */ 112#endif /* EFSYS_OPT_PHY_PROPS */ 113#if EFSYS_OPT_PHY_BIST 114 NULL, /* epo_bist_start */ 115 NULL, /* epo_bist_poll */ 116 NULL, /* epo_bist_stop */ 117#endif /* EFSYS_OPT_PHY_BIST */ 118}; 119#endif /* EFSYS_OPT_PHY_QT2022C2 */ 120 121#if EFSYS_OPT_PHY_SFX7101 122static efx_phy_ops_t __cs __efx_phy_sfx7101_ops = { 123 sfx7101_power, /* epo_power */ 124 sfx7101_reset, /* epo_reset */ 125 sfx7101_reconfigure, /* epo_reconfigure */ 126 sfx7101_verify, /* epo_verify */ 127 sfx7101_uplink_check, /* epo_uplink_check */ 128 sfx7101_downlink_check, /* epo_downlink_check */ 129 sfx7101_oui_get, /* epo_oui_get */ 130#if EFSYS_OPT_PHY_STATS 131 sfx7101_stats_update, /* epo_stats_update */ 132#endif /* EFSYS_OPT_PHY_STATS */ 133#if EFSYS_OPT_PHY_PROPS 134#if EFSYS_OPT_NAMES 135 sfx7101_prop_name, /* epo_prop_name */ 136#endif 137 sfx7101_prop_get, /* epo_prop_get */ 138 sfx7101_prop_set, /* epo_prop_set */ 139#endif /* EFSYS_OPT_PHY_PROPS */ 140#if EFSYS_OPT_PHY_BIST 141 NULL, /* epo_bist_start */ 142 NULL, /* epo_bist_poll */ 143 NULL, /* epo_bist_stop */ 144#endif /* EFSYS_OPT_PHY_BIST */ 145}; 146#endif /* EFSYS_OPT_PHY_SFX7101 */ 147 148#if EFSYS_OPT_PHY_TXC43128 149static efx_phy_ops_t __cs __efx_phy_txc43128_ops = { 150 NULL, /* epo_power */ 151 txc43128_reset, /* epo_reset */ 152 txc43128_reconfigure, /* epo_reconfigure */ 153 txc43128_verify, /* epo_verify */ 154 txc43128_uplink_check, /* epo_uplink_check */ 155 txc43128_downlink_check, /* epo_downlink_check */ 156 txc43128_oui_get, /* epo_oui_get */ 157#if EFSYS_OPT_PHY_STATS 158 txc43128_stats_update, /* epo_stats_update */ 159#endif /* EFSYS_OPT_PHY_STATS */ 160#if EFSYS_OPT_PHY_PROPS 161#if EFSYS_OPT_NAMES 162 txc43128_prop_name, /* epo_prop_name */ 163#endif 164 txc43128_prop_get, /* epo_prop_get */ 165 txc43128_prop_set, /* epo_prop_set */ 166#endif /* EFSYS_OPT_PHY_PROPS */ 167#if EFSYS_OPT_PHY_BIST 168 NULL, /* epo_bist_start */ 169 NULL, /* epo_bist_poll */ 170 NULL, /* epo_bist_stop */ 171#endif /* EFSYS_OPT_PHY_BIST */ 172}; 173#endif /* EFSYS_OPT_PHY_TXC43128 */ 174 175#if EFSYS_OPT_PHY_SFT9001 176static efx_phy_ops_t __cs __efx_phy_sft9001_ops = { 177 NULL, /* epo_power */ 178 sft9001_reset, /* epo_reset */ 179 sft9001_reconfigure, /* epo_reconfigure */ 180 sft9001_verify, /* epo_verify */ 181 sft9001_uplink_check, /* epo_uplink_check */ 182 sft9001_downlink_check, /* epo_downlink_check */ 183 sft9001_oui_get, /* epo_oui_get */ 184#if EFSYS_OPT_PHY_STATS 185 sft9001_stats_update, /* epo_stats_update */ 186#endif /* EFSYS_OPT_PHY_STATS */ 187#if EFSYS_OPT_PHY_PROPS 188#if EFSYS_OPT_NAMES 189 sft9001_prop_name, /* epo_prop_name */ 190#endif 191 sft9001_prop_get, /* epo_prop_get */ 192 sft9001_prop_set, /* epo_prop_set */ 193#endif /* EFSYS_OPT_PHY_PROPS */ 194#if EFSYS_OPT_PHY_BIST 195 sft9001_bist_start, /* epo_bist_start */ 196 sft9001_bist_poll, /* epo_bist_poll */ 197 sft9001_bist_stop, /* epo_bist_stop */ 198#endif /* EFSYS_OPT_PHY_BIST */ 199}; 200#endif /* EFSYS_OPT_PHY_SFT9001 */ 201 202#if EFSYS_OPT_PHY_QT2025C 203static efx_phy_ops_t __cs __efx_phy_qt2025c_ops = { 204 NULL, /* epo_power */ 205 qt2025c_reset, /* epo_reset */ 206 qt2025c_reconfigure, /* epo_reconfigure */ 207 qt2025c_verify, /* epo_verify */ 208 qt2025c_uplink_check, /* epo_uplink_check */ 209 qt2025c_downlink_check, /* epo_downlink_check */ 210 qt2025c_oui_get, /* epo_oui_get */ 211#if EFSYS_OPT_PHY_STATS 212 qt2025c_stats_update, /* epo_stats_update */ 213#endif /* EFSYS_OPT_PHY_STATS */ 214#if EFSYS_OPT_PHY_PROPS 215#if EFSYS_OPT_NAMES 216 qt2025c_prop_name, /* epo_prop_name */ 217#endif 218 qt2025c_prop_get, /* epo_prop_get */ 219 qt2025c_prop_set, /* epo_prop_set */ 220#endif /* EFSYS_OPT_PHY_PROPS */ 221#if EFSYS_OPT_PHY_BIST 222 NULL, /* epo_bist_start */ 223 NULL, /* epo_bist_poll */ 224 NULL, /* epo_bist_stop */ 225#endif /* EFSYS_OPT_PHY_BIST */ 226}; 227#endif /* EFSYS_OPT_PHY_QT2025C */ 228 |
|
37#if EFSYS_OPT_SIENA | 229#if EFSYS_OPT_SIENA |
38static const efx_phy_ops_t __efx_phy_siena_ops = { | 230static efx_phy_ops_t __cs __efx_phy_siena_ops = { |
39 siena_phy_power, /* epo_power */ 40 NULL, /* epo_reset */ 41 siena_phy_reconfigure, /* epo_reconfigure */ 42 siena_phy_verify, /* epo_verify */ | 231 siena_phy_power, /* epo_power */ 232 NULL, /* epo_reset */ 233 siena_phy_reconfigure, /* epo_reconfigure */ 234 siena_phy_verify, /* epo_verify */ |
235 NULL, /* epo_uplink_check */ 236 NULL, /* epo_downlink_check */ |
|
43 siena_phy_oui_get, /* epo_oui_get */ | 237 siena_phy_oui_get, /* epo_oui_get */ |
44 NULL, /* epo_link_state_get */ | |
45#if EFSYS_OPT_PHY_STATS 46 siena_phy_stats_update, /* epo_stats_update */ 47#endif /* EFSYS_OPT_PHY_STATS */ | 238#if EFSYS_OPT_PHY_STATS 239 siena_phy_stats_update, /* epo_stats_update */ 240#endif /* EFSYS_OPT_PHY_STATS */ |
48#if EFSYS_OPT_BIST 49 NULL, /* epo_bist_enable_offline */ 50 siena_phy_bist_start, /* epo_bist_start */ | 241#if EFSYS_OPT_PHY_PROPS 242#if EFSYS_OPT_NAMES 243 siena_phy_prop_name, /* epo_prop_name */ 244#endif 245 siena_phy_prop_get, /* epo_prop_get */ 246 siena_phy_prop_set, /* epo_prop_set */ 247#endif /* EFSYS_OPT_PHY_PROPS */ 248#if EFSYS_OPT_PHY_BIST 249 siena_phy_bist_start, /* epo_bist_start */ |
51 siena_phy_bist_poll, /* epo_bist_poll */ 52 siena_phy_bist_stop, /* epo_bist_stop */ | 250 siena_phy_bist_poll, /* epo_bist_poll */ 251 siena_phy_bist_stop, /* epo_bist_stop */ |
53#endif /* EFSYS_OPT_BIST */ | 252#endif /* EFSYS_OPT_PHY_BIST */ |
54}; 55#endif /* EFSYS_OPT_SIENA */ 56 | 253}; 254#endif /* EFSYS_OPT_SIENA */ 255 |
57#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 58static const efx_phy_ops_t __efx_phy_ef10_ops = { 59 ef10_phy_power, /* epo_power */ 60 NULL, /* epo_reset */ 61 ef10_phy_reconfigure, /* epo_reconfigure */ 62 ef10_phy_verify, /* epo_verify */ 63 ef10_phy_oui_get, /* epo_oui_get */ 64 ef10_phy_link_state_get, /* epo_link_state_get */ 65#if EFSYS_OPT_PHY_STATS 66 ef10_phy_stats_update, /* epo_stats_update */ 67#endif /* EFSYS_OPT_PHY_STATS */ 68#if EFSYS_OPT_BIST 69 ef10_bist_enable_offline, /* epo_bist_enable_offline */ 70 ef10_bist_start, /* epo_bist_start */ 71 ef10_bist_poll, /* epo_bist_poll */ 72 ef10_bist_stop, /* epo_bist_stop */ 73#endif /* EFSYS_OPT_BIST */ 74}; 75#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ 76 77 __checkReturn efx_rc_t | 256 __checkReturn int |
78efx_phy_probe( 79 __in efx_nic_t *enp) 80{ 81 efx_port_t *epp = &(enp->en_port); 82 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); | 257efx_phy_probe( 258 __in efx_nic_t *enp) 259{ 260 efx_port_t *epp = &(enp->en_port); 261 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); |
83 const efx_phy_ops_t *epop; 84 efx_rc_t rc; | 262 efx_phy_ops_t *epop; 263 int rc; |
85 86 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 87 88 epp->ep_port = encp->enc_port; 89 epp->ep_phy_type = encp->enc_phy_type; 90 91 /* Hook in operations structure */ 92 switch (enp->en_family) { | 264 265 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 266 267 epp->ep_port = encp->enc_port; 268 epp->ep_phy_type = encp->enc_phy_type; 269 270 /* Hook in operations structure */ 271 switch (enp->en_family) { |
272#if EFSYS_OPT_FALCON 273 case EFX_FAMILY_FALCON: 274 switch (epp->ep_phy_type) { 275#if EFSYS_OPT_PHY_NULL 276 case PHY_TYPE_NONE_DECODE: 277 epop = (efx_phy_ops_t *)&__efx_phy_null_ops; 278 break; 279#endif 280#if EFSYS_OPT_PHY_QT2022C2 281 case PHY_TYPE_QT2022C2_DECODE: 282 epop = (efx_phy_ops_t *)&__efx_phy_qt2022c2_ops; 283 break; 284#endif 285#if EFSYS_OPT_PHY_SFX7101 286 case PHY_TYPE_SFX7101_DECODE: 287 epop = (efx_phy_ops_t *)&__efx_phy_sfx7101_ops; 288 break; 289#endif 290#if EFSYS_OPT_PHY_TXC43128 291 case PHY_TYPE_TXC43128_DECODE: 292 epop = (efx_phy_ops_t *)&__efx_phy_txc43128_ops; 293 break; 294#endif 295#if EFSYS_OPT_PHY_SFT9001 296 case PHY_TYPE_SFT9001A_DECODE: 297 case PHY_TYPE_SFT9001B_DECODE: 298 epop = (efx_phy_ops_t *)&__efx_phy_sft9001_ops; 299 break; 300#endif 301#if EFSYS_OPT_PHY_QT2025C 302 case EFX_PHY_QT2025C: 303 epop = (efx_phy_ops_t *)&__efx_phy_qt2025c_ops; 304 break; 305#endif 306 default: 307 rc = ENOTSUP; 308 goto fail1; 309 } 310 break; 311#endif /* EFSYS_OPT_FALCON */ |
|
93#if EFSYS_OPT_SIENA 94 case EFX_FAMILY_SIENA: | 312#if EFSYS_OPT_SIENA 313 case EFX_FAMILY_SIENA: |
95 epop = &__efx_phy_siena_ops; | 314 epop = (efx_phy_ops_t *)&__efx_phy_siena_ops; |
96 break; 97#endif /* EFSYS_OPT_SIENA */ | 315 break; 316#endif /* EFSYS_OPT_SIENA */ |
98 99#if EFSYS_OPT_HUNTINGTON 100 case EFX_FAMILY_HUNTINGTON: 101 epop = &__efx_phy_ef10_ops; 102 break; 103#endif /* EFSYS_OPT_HUNTINGTON */ 104 105#if EFSYS_OPT_MEDFORD 106 case EFX_FAMILY_MEDFORD: 107 epop = &__efx_phy_ef10_ops; 108 break; 109#endif /* EFSYS_OPT_MEDFORD */ 110 111#if EFSYS_OPT_MEDFORD2 112 case EFX_FAMILY_MEDFORD2: 113 epop = &__efx_phy_ef10_ops; 114 break; 115#endif /* EFSYS_OPT_MEDFORD2 */ 116 | |
117 default: 118 rc = ENOTSUP; 119 goto fail1; 120 } 121 122 epp->ep_epop = epop; 123 124 return (0); 125 126fail1: | 317 default: 318 rc = ENOTSUP; 319 goto fail1; 320 } 321 322 epp->ep_epop = epop; 323 324 return (0); 325 326fail1: |
127 EFSYS_PROBE1(fail1, efx_rc_t, rc); | 327 EFSYS_PROBE1(fail1, int, rc); |
128 129 epp->ep_port = 0; 130 epp->ep_phy_type = 0; 131 132 return (rc); 133} 134 | 328 329 epp->ep_port = 0; 330 epp->ep_phy_type = 0; 331 332 return (rc); 333} 334 |
135 __checkReturn efx_rc_t | 335 __checkReturn int |
136efx_phy_verify( 137 __in efx_nic_t *enp) 138{ 139 efx_port_t *epp = &(enp->en_port); | 336efx_phy_verify( 337 __in efx_nic_t *enp) 338{ 339 efx_port_t *epp = &(enp->en_port); |
140 const efx_phy_ops_t *epop = epp->ep_epop; | 340 efx_phy_ops_t *epop = epp->ep_epop; |
141 142 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 143 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 144 145 return (epop->epo_verify(enp)); 146} 147 148#if EFSYS_OPT_PHY_LED_CONTROL 149 | 341 342 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 343 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 344 345 return (epop->epo_verify(enp)); 346} 347 348#if EFSYS_OPT_PHY_LED_CONTROL 349 |
150 __checkReturn efx_rc_t | 350 __checkReturn int |
151efx_phy_led_set( 152 __in efx_nic_t *enp, 153 __in efx_phy_led_mode_t mode) 154{ 155 efx_nic_cfg_t *encp = (&enp->en_nic_cfg); 156 efx_port_t *epp = &(enp->en_port); | 351efx_phy_led_set( 352 __in efx_nic_t *enp, 353 __in efx_phy_led_mode_t mode) 354{ 355 efx_nic_cfg_t *encp = (&enp->en_nic_cfg); 356 efx_port_t *epp = &(enp->en_port); |
157 const efx_phy_ops_t *epop = epp->ep_epop; | 357 efx_phy_ops_t *epop = epp->ep_epop; |
158 uint32_t mask; | 358 uint32_t mask; |
159 efx_rc_t rc; | 359 int rc; |
160 161 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 162 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 163 164 if (epp->ep_phy_led_mode == mode) 165 goto done; 166 167 mask = (1 << EFX_PHY_LED_DEFAULT); --- 11 unchanged lines hidden (view full) --- 179 goto fail2; 180 181done: 182 return (0); 183 184fail2: 185 EFSYS_PROBE(fail2); 186fail1: | 360 361 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 362 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 363 364 if (epp->ep_phy_led_mode == mode) 365 goto done; 366 367 mask = (1 << EFX_PHY_LED_DEFAULT); --- 11 unchanged lines hidden (view full) --- 379 goto fail2; 380 381done: 382 return (0); 383 384fail2: 385 EFSYS_PROBE(fail2); 386fail1: |
187 EFSYS_PROBE1(fail1, efx_rc_t, rc); | 387 EFSYS_PROBE1(fail1, int, rc); |
188 189 return (rc); 190} 191#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 192 193 void 194efx_phy_adv_cap_get( 195 __in efx_nic_t *enp, --- 12 unchanged lines hidden (view full) --- 208 case EFX_PHY_CAP_DEFAULT: 209 *maskp = epp->ep_default_adv_cap_mask; 210 break; 211 case EFX_PHY_CAP_PERM: 212 *maskp = epp->ep_phy_cap_mask; 213 break; 214 default: 215 EFSYS_ASSERT(B_FALSE); | 388 389 return (rc); 390} 391#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 392 393 void 394efx_phy_adv_cap_get( 395 __in efx_nic_t *enp, --- 12 unchanged lines hidden (view full) --- 408 case EFX_PHY_CAP_DEFAULT: 409 *maskp = epp->ep_default_adv_cap_mask; 410 break; 411 case EFX_PHY_CAP_PERM: 412 *maskp = epp->ep_phy_cap_mask; 413 break; 414 default: 415 EFSYS_ASSERT(B_FALSE); |
216 *maskp = 0; | |
217 break; 218 } 219} 220 | 416 break; 417 } 418} 419 |
221 __checkReturn efx_rc_t | 420 __checkReturn int |
222efx_phy_adv_cap_set( 223 __in efx_nic_t *enp, 224 __in uint32_t mask) 225{ 226 efx_port_t *epp = &(enp->en_port); | 421efx_phy_adv_cap_set( 422 __in efx_nic_t *enp, 423 __in uint32_t mask) 424{ 425 efx_port_t *epp = &(enp->en_port); |
227 const efx_phy_ops_t *epop = epp->ep_epop; 228 uint32_t old_mask; 229 efx_rc_t rc; | 426 efx_phy_ops_t *epop = epp->ep_epop; 427 int rc; |
230 231 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 232 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 233 234 if ((mask & ~epp->ep_phy_cap_mask) != 0) { 235 rc = ENOTSUP; 236 goto fail1; 237 } 238 239 if (epp->ep_adv_cap_mask == mask) 240 goto done; 241 | 428 429 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 430 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 431 432 if ((mask & ~epp->ep_phy_cap_mask) != 0) { 433 rc = ENOTSUP; 434 goto fail1; 435 } 436 437 if (epp->ep_adv_cap_mask == mask) 438 goto done; 439 |
242 old_mask = epp->ep_adv_cap_mask; | |
243 epp->ep_adv_cap_mask = mask; 244 245 if ((rc = epop->epo_reconfigure(enp)) != 0) 246 goto fail2; 247 248done: 249 return (0); 250 251fail2: 252 EFSYS_PROBE(fail2); | 440 epp->ep_adv_cap_mask = mask; 441 442 if ((rc = epop->epo_reconfigure(enp)) != 0) 443 goto fail2; 444 445done: 446 return (0); 447 448fail2: 449 EFSYS_PROBE(fail2); |
253 254 epp->ep_adv_cap_mask = old_mask; 255 /* Reconfigure for robustness */ 256 if (epop->epo_reconfigure(enp) != 0) { 257 /* 258 * We may have an inconsistent view of our advertised speed 259 * capabilities. 260 */ 261 EFSYS_ASSERT(0); 262 } 263 | |
264fail1: | 450fail1: |
265 EFSYS_PROBE1(fail1, efx_rc_t, rc); | 451 EFSYS_PROBE1(fail1, int, rc); |
266 267 return (rc); 268} 269 270 void 271efx_phy_lp_cap_get( 272 __in efx_nic_t *enp, 273 __out uint32_t *maskp) 274{ 275 efx_port_t *epp = &(enp->en_port); 276 277 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 278 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 279 280 *maskp = epp->ep_lp_cap_mask; 281} 282 | 452 453 return (rc); 454} 455 456 void 457efx_phy_lp_cap_get( 458 __in efx_nic_t *enp, 459 __out uint32_t *maskp) 460{ 461 efx_port_t *epp = &(enp->en_port); 462 463 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 464 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 465 466 *maskp = epp->ep_lp_cap_mask; 467} 468 |
283 __checkReturn efx_rc_t | 469 __checkReturn int |
284efx_phy_oui_get( 285 __in efx_nic_t *enp, 286 __out uint32_t *ouip) 287{ 288 efx_port_t *epp = &(enp->en_port); | 470efx_phy_oui_get( 471 __in efx_nic_t *enp, 472 __out uint32_t *ouip) 473{ 474 efx_port_t *epp = &(enp->en_port); |
289 const efx_phy_ops_t *epop = epp->ep_epop; | 475 efx_phy_ops_t *epop = epp->ep_epop; |
290 291 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 292 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 293 294 return (epop->epo_oui_get(enp, ouip)); 295} 296 297 void --- 7 unchanged lines hidden (view full) --- 305 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 306 307 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID) 308 *typep = epp->ep_module_type; 309 else 310 *typep = epp->ep_fixed_port_type; 311} 312 | 476 477 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 478 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 479 480 return (epop->epo_oui_get(enp, ouip)); 481} 482 483 void --- 7 unchanged lines hidden (view full) --- 491 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 492 493 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID) 494 *typep = epp->ep_module_type; 495 else 496 *typep = epp->ep_fixed_port_type; 497} 498 |
313 __checkReturn efx_rc_t 314efx_phy_module_get_info( 315 __in efx_nic_t *enp, 316 __in uint8_t dev_addr, 317 __in size_t offset, 318 __in size_t len, 319 __out_bcount(len) uint8_t *data) 320{ 321 efx_rc_t rc; 322 323 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 324 EFSYS_ASSERT(data != NULL); 325 326 if ((offset > EFX_PHY_MEDIA_INFO_MAX_OFFSET) || 327 ((offset + len) > EFX_PHY_MEDIA_INFO_MAX_OFFSET)) { 328 rc = EINVAL; 329 goto fail1; 330 } 331 332 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr, 333 offset, len, data)) != 0) 334 goto fail2; 335 336 return (0); 337 338fail2: 339 EFSYS_PROBE(fail2); 340fail1: 341 EFSYS_PROBE1(fail1, efx_rc_t, rc); 342 343 return (rc); 344} 345 346 __checkReturn efx_rc_t 347efx_phy_fec_type_get( 348 __in efx_nic_t *enp, 349 __out efx_phy_fec_type_t *typep) 350{ 351 efx_rc_t rc; 352 efx_phy_link_state_t epls; 353 354 if ((rc = efx_phy_link_state_get(enp, &epls)) != 0) 355 goto fail1; 356 357 *typep = epls.epls_fec; 358 359 return (0); 360 361fail1: 362 EFSYS_PROBE1(fail1, efx_rc_t, rc); 363 364 return (rc); 365} 366 367 __checkReturn efx_rc_t 368efx_phy_link_state_get( 369 __in efx_nic_t *enp, 370 __out efx_phy_link_state_t *eplsp) 371{ 372 efx_port_t *epp = &(enp->en_port); 373 const efx_phy_ops_t *epop = epp->ep_epop; 374 efx_rc_t rc; 375 376 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 377 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); 378 379 if (epop->epo_link_state_get == NULL) { 380 rc = ENOTSUP; 381 goto fail1; 382 } 383 384 if ((rc = epop->epo_link_state_get(enp, eplsp)) != 0) 385 goto fail2; 386 387 return (0); 388 389fail2: 390 EFSYS_PROBE(fail2); 391fail1: 392 EFSYS_PROBE1(fail1, efx_rc_t, rc); 393 394 return (rc); 395} 396 | |
397#if EFSYS_OPT_PHY_STATS 398 399#if EFSYS_OPT_NAMES 400 | 499#if EFSYS_OPT_PHY_STATS 500 501#if EFSYS_OPT_NAMES 502 |
401/* START MKCONFIG GENERATED PhyStatNamesBlock af9ffa24da3bc100 */ 402static const char * const __efx_phy_stat_name[] = { | 503/* START MKCONFIG GENERATED PhyStatNamesBlock 271268f3da0e804f */ 504static const char __cs * __cs __efx_phy_stat_name[] = { |
403 "oui", 404 "pma_pmd_link_up", 405 "pma_pmd_rx_fault", 406 "pma_pmd_tx_fault", 407 "pma_pmd_rev_a", 408 "pma_pmd_rev_b", 409 "pma_pmd_rev_c", 410 "pma_pmd_rev_d", --- 34 unchanged lines hidden (view full) --- 445 "pcs_fw_build_yy", 446 "pcs_fw_build_mm", 447 "pcs_fw_build_dd", 448 "pcs_op_mode", 449}; 450 451/* END MKCONFIG GENERATED PhyStatNamesBlock */ 452 | 505 "oui", 506 "pma_pmd_link_up", 507 "pma_pmd_rx_fault", 508 "pma_pmd_tx_fault", 509 "pma_pmd_rev_a", 510 "pma_pmd_rev_b", 511 "pma_pmd_rev_c", 512 "pma_pmd_rev_d", --- 34 unchanged lines hidden (view full) --- 547 "pcs_fw_build_yy", 548 "pcs_fw_build_mm", 549 "pcs_fw_build_dd", 550 "pcs_op_mode", 551}; 552 553/* END MKCONFIG GENERATED PhyStatNamesBlock */ 554 |
453 const char * | 555 const char __cs * |
454efx_phy_stat_name( 455 __in efx_nic_t *enp, 456 __in efx_phy_stat_t type) 457{ 458 _NOTE(ARGUNUSED(enp)) 459 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 460 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS); 461 462 return (__efx_phy_stat_name[type]); 463} 464 465#endif /* EFSYS_OPT_NAMES */ 466 | 556efx_phy_stat_name( 557 __in efx_nic_t *enp, 558 __in efx_phy_stat_t type) 559{ 560 _NOTE(ARGUNUSED(enp)) 561 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 562 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS); 563 564 return (__efx_phy_stat_name[type]); 565} 566 567#endif /* EFSYS_OPT_NAMES */ 568 |
467 __checkReturn efx_rc_t | 569 __checkReturn int |
468efx_phy_stats_update( 469 __in efx_nic_t *enp, 470 __in efsys_mem_t *esmp, | 570efx_phy_stats_update( 571 __in efx_nic_t *enp, 572 __in efsys_mem_t *esmp, |
471 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat) | 573 __out_ecount(EFX_PHY_NSTATS) uint32_t *stat) |
472{ 473 efx_port_t *epp = &(enp->en_port); | 574{ 575 efx_port_t *epp = &(enp->en_port); |
474 const efx_phy_ops_t *epop = epp->ep_epop; | 576 efx_phy_ops_t *epop = epp->ep_epop; |
475 476 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 477 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 478 479 return (epop->epo_stats_update(enp, esmp, stat)); 480} 481 482#endif /* EFSYS_OPT_PHY_STATS */ 483 | 577 578 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 579 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 580 581 return (epop->epo_stats_update(enp, esmp, stat)); 582} 583 584#endif /* EFSYS_OPT_PHY_STATS */ 585 |
484#if EFSYS_OPT_BIST | 586#if EFSYS_OPT_PHY_PROPS |
485 | 587 |
486 __checkReturn efx_rc_t 487efx_bist_enable_offline( 488 __in efx_nic_t *enp) | 588#if EFSYS_OPT_NAMES 589 const char __cs * 590efx_phy_prop_name( 591 __in efx_nic_t *enp, 592 __in unsigned int id) |
489{ 490 efx_port_t *epp = &(enp->en_port); | 593{ 594 efx_port_t *epp = &(enp->en_port); |
491 const efx_phy_ops_t *epop = epp->ep_epop; 492 efx_rc_t rc; | 595 efx_phy_ops_t *epop = epp->ep_epop; |
493 494 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); | 596 597 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); |
598 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); |
|
495 | 599 |
496 if (epop->epo_bist_enable_offline == NULL) { 497 rc = ENOTSUP; 498 goto fail1; 499 } | 600 return (epop->epo_prop_name(enp, id)); 601} 602#endif /* EFSYS_OPT_NAMES */ |
500 | 603 |
501 if ((rc = epop->epo_bist_enable_offline(enp)) != 0) 502 goto fail2; | 604 __checkReturn int 605efx_phy_prop_get( 606 __in efx_nic_t *enp, 607 __in unsigned int id, 608 __in uint32_t flags, 609 __out uint32_t *valp) 610{ 611 efx_port_t *epp = &(enp->en_port); 612 efx_phy_ops_t *epop = epp->ep_epop; |
503 | 613 |
504 return (0); | 614 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 615 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); |
505 | 616 |
506fail2: 507 EFSYS_PROBE(fail2); 508fail1: 509 EFSYS_PROBE1(fail1, efx_rc_t, rc); | 617 return (epop->epo_prop_get(enp, id, flags, valp)); 618} |
510 | 619 |
511 return (rc); | 620 __checkReturn int 621efx_phy_prop_set( 622 __in efx_nic_t *enp, 623 __in unsigned int id, 624 __in uint32_t val) 625{ 626 efx_port_t *epp = &(enp->en_port); 627 efx_phy_ops_t *epop = epp->ep_epop; |
512 | 628 |
629 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 630 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); 631 632 return (epop->epo_prop_set(enp, id, val)); |
|
513} | 633} |
634#endif /* EFSYS_OPT_PHY_STATS */ |
|
514 | 635 |
515 __checkReturn efx_rc_t 516efx_bist_start( | 636#if EFSYS_OPT_PHY_BIST 637 638 __checkReturn int 639efx_phy_bist_start( |
517 __in efx_nic_t *enp, | 640 __in efx_nic_t *enp, |
518 __in efx_bist_type_t type) | 641 __in efx_phy_bist_type_t type) |
519{ 520 efx_port_t *epp = &(enp->en_port); | 642{ 643 efx_port_t *epp = &(enp->en_port); |
521 const efx_phy_ops_t *epop = epp->ep_epop; 522 efx_rc_t rc; | 644 efx_phy_ops_t *epop = epp->ep_epop; 645 int rc; |
523 524 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); | 646 647 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); |
648 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); |
|
525 | 649 |
526 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN); 527 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES); 528 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN); | 650 EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN); 651 EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES); 652 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_PHY_BIST_TYPE_UNKNOWN); |
529 530 if (epop->epo_bist_start == NULL) { 531 rc = ENOTSUP; 532 goto fail1; 533 } 534 535 if ((rc = epop->epo_bist_start(enp, type)) != 0) 536 goto fail2; 537 538 epp->ep_current_bist = type; 539 540 return (0); 541 542fail2: 543 EFSYS_PROBE(fail2); 544fail1: | 653 654 if (epop->epo_bist_start == NULL) { 655 rc = ENOTSUP; 656 goto fail1; 657 } 658 659 if ((rc = epop->epo_bist_start(enp, type)) != 0) 660 goto fail2; 661 662 epp->ep_current_bist = type; 663 664 return (0); 665 666fail2: 667 EFSYS_PROBE(fail2); 668fail1: |
545 EFSYS_PROBE1(fail1, efx_rc_t, rc); | 669 EFSYS_PROBE1(fail1, int, rc); |
546 547 return (rc); 548} 549 | 670 671 return (rc); 672} 673 |
550 __checkReturn efx_rc_t 551efx_bist_poll( | 674 __checkReturn int 675efx_phy_bist_poll( |
552 __in efx_nic_t *enp, | 676 __in efx_nic_t *enp, |
553 __in efx_bist_type_t type, 554 __out efx_bist_result_t *resultp, | 677 __in efx_phy_bist_type_t type, 678 __out efx_phy_bist_result_t *resultp, |
555 __out_opt uint32_t *value_maskp, 556 __out_ecount_opt(count) unsigned long *valuesp, 557 __in size_t count) 558{ 559 efx_port_t *epp = &(enp->en_port); | 679 __out_opt uint32_t *value_maskp, 680 __out_ecount_opt(count) unsigned long *valuesp, 681 __in size_t count) 682{ 683 efx_port_t *epp = &(enp->en_port); |
560 const efx_phy_ops_t *epop = epp->ep_epop; 561 efx_rc_t rc; | 684 efx_phy_ops_t *epop = epp->ep_epop; 685 int rc; |
562 563 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); | 686 687 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); |
688 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); |
|
564 | 689 |
565 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN); 566 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES); | 690 EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN); 691 EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES); |
567 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type); 568 569 EFSYS_ASSERT(epop->epo_bist_poll != NULL); 570 if (epop->epo_bist_poll == NULL) { 571 rc = ENOTSUP; 572 goto fail1; 573 } 574 575 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp, 576 valuesp, count)) != 0) 577 goto fail2; 578 579 return (0); 580 581fail2: 582 EFSYS_PROBE(fail2); 583fail1: | 692 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type); 693 694 EFSYS_ASSERT(epop->epo_bist_poll != NULL); 695 if (epop->epo_bist_poll == NULL) { 696 rc = ENOTSUP; 697 goto fail1; 698 } 699 700 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp, 701 valuesp, count)) != 0) 702 goto fail2; 703 704 return (0); 705 706fail2: 707 EFSYS_PROBE(fail2); 708fail1: |
584 EFSYS_PROBE1(fail1, efx_rc_t, rc); | 709 EFSYS_PROBE1(fail1, int, rc); |
585 586 return (rc); 587} 588 589 void | 710 711 return (rc); 712} 713 714 void |
590efx_bist_stop( | 715efx_phy_bist_stop( |
591 __in efx_nic_t *enp, | 716 __in efx_nic_t *enp, |
592 __in efx_bist_type_t type) | 717 __in efx_phy_bist_type_t type) |
593{ 594 efx_port_t *epp = &(enp->en_port); | 718{ 719 efx_port_t *epp = &(enp->en_port); |
595 const efx_phy_ops_t *epop = epp->ep_epop; | 720 efx_phy_ops_t *epop = epp->ep_epop; |
596 597 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); | 721 722 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); |
723 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); |
|
598 | 724 |
599 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN); 600 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES); | 725 EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN); 726 EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES); |
601 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type); 602 603 EFSYS_ASSERT(epop->epo_bist_stop != NULL); 604 605 if (epop->epo_bist_stop != NULL) 606 epop->epo_bist_stop(enp, type); 607 | 727 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type); 728 729 EFSYS_ASSERT(epop->epo_bist_stop != NULL); 730 731 if (epop->epo_bist_stop != NULL) 732 epop->epo_bist_stop(enp, type); 733 |
608 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN; | 734 epp->ep_current_bist = EFX_PHY_BIST_TYPE_UNKNOWN; |
609} 610 | 735} 736 |
611#endif /* EFSYS_OPT_BIST */ | 737#endif /* EFSYS_OPT_PHY_BIST */ |
612 void 613efx_phy_unprobe( 614 __in efx_nic_t *enp) 615{ 616 efx_port_t *epp = &(enp->en_port); 617 618 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 619 620 epp->ep_epop = NULL; 621 622 epp->ep_adv_cap_mask = 0; 623 624 epp->ep_port = 0; 625 epp->ep_phy_type = 0; 626} | 738 void 739efx_phy_unprobe( 740 __in efx_nic_t *enp) 741{ 742 efx_port_t *epp = &(enp->en_port); 743 744 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); 745 746 epp->ep_epop = NULL; 747 748 epp->ep_adv_cap_mask = 0; 749 750 epp->ep_port = 0; 751 epp->ep_phy_type = 0; 752} |