2c2
< * SPDX-License-Identifier: BSD-2-Clause
---
> * Copyright 2007-2010 Solarflare Communications Inc. All rights reserved.
4,6d3
< * Copyright (c) 2007-2016 Solarflare Communications Inc.
< * All rights reserved.
< *
8c5,11
< * modification, are permitted provided that the following conditions are met:
---
> * modification, are permitted provided that the following conditions
> * are met:
> * 1. Redistributions of source code must retain the above copyright
> * notice, this list of conditions and the following disclaimer.
> * 2. Redistributions in binary form must reproduce the above copyright
> * notice, this list of conditions and the following disclaimer in the
> * documentation and/or other materials provided with the distribution.
10,30c13,23
< * 1. Redistributions of source code must retain the above copyright notice,
< * this list of conditions and the following disclaimer.
< * 2. Redistributions in binary form must reproduce the above copyright notice,
< * this list of conditions and the following disclaimer in the documentation
< * and/or other materials provided with the distribution.
< *
< * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
< * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
< * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
< * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
< * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
< * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
< * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
< * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
< * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
< * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
< * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
< *
< * The views and conclusions contained in the software and documentation are
< * those of the authors and should not be interpreted as representing official
< * policies, either expressed or implied, of the FreeBSD Project.
---
> * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
> * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> * SUCH DAMAGE.
50a44
>
61a56
>
92a88
>
123a120
>
134a132
>
149a148
>
160a160
>
171a172
>
184a186
>
195a198
>
212a216
>
223a228
>
240a246
>
251a258
>
268a276
>
279a288
>
290a300
>
301a312
>
320a332
>
331a344
>
342a356
>
353,356d366
< #define PCFE_DZ_INTPIN_INTD 4
< #define PCFE_DZ_INTPIN_INTC 3
< #define PCFE_DZ_INTPIN_INTB 2
< #define PCFE_DZ_INTPIN_INTA 1
357a368
>
363,364c374,375
< #define PCR_AZ_PM_CAP_ID_REG 0x00000040
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_PM_CAP_ID_REG 0x00000040
> /* falcona0,falconb0,sienaa0=pci_f0_config */
365a377,379
> #define PCR_DZ_PM_CAP_ID_REG 0x00000080
> /* hunta0=pci_f0_config */
>
368a383
>
374,375c389,390
< #define PCR_AZ_PM_NXT_PTR_REG 0x00000041
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_PM_NXT_PTR_REG 0x00000041
> /* falcona0,falconb0,sienaa0=pci_f0_config */
376a392,394
> #define PCR_DZ_PM_NXT_PTR_REG 0x00000081
> /* hunta0=pci_f0_config */
>
379a398
>
385,386c404,405
< #define PCR_AZ_PM_CAP_REG 0x00000042
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_PM_CAP_REG 0x00000042
> /* falcona0,falconb0,sienaa0=pci_f0_config */
387a407,409
> #define PCR_DZ_PM_CAP_REG 0x00000082
> /* hunta0=pci_f0_config */
>
402a425
>
408,409c431,432
< #define PCR_AZ_PM_CS_REG 0x00000044
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_PM_CS_REG 0x00000044
> /* falcona0,falconb0,sienaa0=pci_f0_config */
410a434,436
> #define PCR_DZ_PM_CS_REG 0x00000084
> /* hunta0=pci_f0_config */
>
423a450
>
429,430c456,457
< #define PCR_AZ_MSI_CAP_ID_REG 0x00000050
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_CAP_ID_REG 0x00000050
> /* falcona0,falconb0,sienaa0=pci_f0_config */
431a459,461
> #define PCR_DZ_MSI_CAP_ID_REG 0x00000090
> /* hunta0=pci_f0_config */
>
434a465
>
440,441c471,472
< #define PCR_AZ_MSI_NXT_PTR_REG 0x00000051
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_NXT_PTR_REG 0x00000051
> /* falcona0,falconb0,sienaa0=pci_f0_config */
442a474,476
> #define PCR_DZ_MSI_NXT_PTR_REG 0x00000091
> /* hunta0=pci_f0_config */
>
445a480
>
451,452c486,487
< #define PCR_AZ_MSI_CTL_REG 0x00000052
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_CTL_REG 0x00000052
> /* falcona0,falconb0,sienaa0=pci_f0_config */
453a489,491
> #define PCR_DZ_MSI_CTL_REG 0x00000092
> /* hunta0=pci_f0_config */
>
462a501
>
468,469c507,508
< #define PCR_AZ_MSI_ADR_LO_REG 0x00000054
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_ADR_LO_REG 0x00000054
> /* falcona0,falconb0,sienaa0=pci_f0_config */
470a510,512
> #define PCR_DZ_MSI_ADR_LO_REG 0x00000094
> /* hunta0=pci_f0_config */
>
473a516
>
474a518,556
> * PC_VPD_CAP_CTL_REG(8bit):
> * VPD control and capabilities register
> */
>
> #define PCR_DZ_VPD_CAP_CTL_REG 0x00000054
> /* hunta0=pci_f0_config */
>
> #define PCR_CC_VPD_CAP_CTL_REG 0x000000d0
> /* sienaa0=pci_f0_config */
>
> #define PCRF_CZ_VPD_FLAG_LBN 31
> #define PCRF_CZ_VPD_FLAG_WIDTH 1
> #define PCRF_CZ_VPD_ADDR_LBN 16
> #define PCRF_CZ_VPD_ADDR_WIDTH 15
> #define PCRF_CZ_VPD_NXT_PTR_LBN 8
> #define PCRF_CZ_VPD_NXT_PTR_WIDTH 8
> #define PCRF_CZ_VPD_CAP_ID_LBN 0
> #define PCRF_CZ_VPD_CAP_ID_WIDTH 8
>
>
> /*
> * PC_VPD_CAP_DATA_REG(32bit):
> * documentation to be written for sum_PC_VPD_CAP_DATA_REG
> */
>
> #define PCR_DZ_VPD_CAP_DATA_REG 0x00000058
> /* hunta0=pci_f0_config */
>
> #define PCR_AB_VPD_CAP_DATA_REG 0x000000b4
> /* falcona0,falconb0=pci_f0_config */
>
> #define PCR_CC_VPD_CAP_DATA_REG 0x000000d4
> /* sienaa0=pci_f0_config */
>
> #define PCRF_AZ_VPD_DATA_LBN 0
> #define PCRF_AZ_VPD_DATA_WIDTH 32
>
>
> /*
479,480c561,562
< #define PCR_AZ_MSI_ADR_HI_REG 0x00000058
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_ADR_HI_REG 0x00000058
> /* falcona0,falconb0,sienaa0=pci_f0_config */
481a564,566
> #define PCR_DZ_MSI_ADR_HI_REG 0x00000098
> /* hunta0=pci_f0_config */
>
484a570
>
490,491c576,577
< #define PCR_AZ_MSI_DAT_REG 0x0000005c
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_DAT_REG 0x0000005c
> /* falcona0,falconb0,sienaa0=pci_f0_config */
492a579,581
> #define PCR_DZ_MSI_DAT_REG 0x0000009c
> /* hunta0=pci_f0_config */
>
495a585
>
504,505c594,595
< #define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_PCIE_CAP_LIST_REG 0x00000070
> /* sienaa0=pci_f0_config */
506a597,599
> #define PCR_DZ_PCIE_CAP_LIST_REG 0x000000c0
> /* hunta0=pci_f0_config */
>
511a605
>
520,521c614,615
< #define PCR_CZ_PCIE_CAP_REG 0x00000072
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_PCIE_CAP_REG 0x00000072
> /* sienaa0=pci_f0_config */
522a617,619
> #define PCR_DZ_PCIE_CAP_REG 0x000000c2
> /* hunta0=pci_f0_config */
>
531a629
>
540,541c638,639
< #define PCR_CZ_DEV_CAP_REG 0x00000074
< /* sienaa0=pci_f0_config,hunta0=pci_f0_config */
---
> #define PCR_CC_DEV_CAP_REG 0x00000074
> /* sienaa0=pci_f0_config */
542a641,643
> #define PCR_DZ_DEV_CAP_REG 0x000000c4
> /* hunta0=pci_f0_config */
>
567a669
>
576,577c678,679
< #define PCR_CZ_DEV_CTL_REG 0x00000078
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_DEV_CTL_REG 0x00000078
> /* sienaa0=pci_f0_config */
578a681,683
> #define PCR_DZ_DEV_CTL_REG 0x000000c8
> /* hunta0=pci_f0_config */
>
588a694
> #define PCFE_DZ_OTHER other
606a713
> #define PCFE_DZ_OTHER other
617a725
>
626,627c734,735
< #define PCR_CZ_DEV_STAT_REG 0x0000007a
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_DEV_STAT_REG 0x0000007a
> /* sienaa0=pci_f0_config */
628a737,739
> #define PCR_DZ_DEV_STAT_REG 0x000000ca
> /* hunta0=pci_f0_config */
>
641a753
>
650,651c762,763
< #define PCR_CZ_LNK_CAP_REG 0x0000007c
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_LNK_CAP_REG 0x0000007c
> /* sienaa0=pci_f0_config */
652a765,767
> #define PCR_DZ_LNK_CAP_REG 0x000000cc
> /* hunta0=pci_f0_config */
>
655,656d769
< #define PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22
< #define PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1
675a789
>
684,685c798,799
< #define PCR_CZ_LNK_CTL_REG 0x00000080
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_LNK_CTL_REG 0x00000080
> /* sienaa0=pci_f0_config */
686a801,803
> #define PCR_DZ_LNK_CTL_REG 0x000000d0
> /* hunta0=pci_f0_config */
>
701a819
>
710,711c828,829
< #define PCR_CZ_LNK_STAT_REG 0x00000082
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_LNK_STAT_REG 0x00000082
> /* sienaa0=pci_f0_config */
712a831,833
> #define PCR_DZ_LNK_STAT_REG 0x000000d2
> /* hunta0=pci_f0_config */
>
723a845
>
752a875
>
779a903
>
802a927
>
816a942
>
830a957
>
849,852d975
< /*
< * PC_MSIX_TBL_BASE_REG(32bit):
< * MSIX Capability Vector Table Base
< */
854,864d976
< #define PCR_BB_MSIX_TBL_BASE_REG 0x00000094
< /* falconb0=pci_f0_config */
<
< #define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4
< /* sienaa0,hunta0=pci_f0_config */
<
< #define PCRF_BZ_MSIX_TBL_OFF_LBN 3
< #define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29
< #define PCRF_BZ_MSIX_TBL_BIR_LBN 0
< #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3
<
866c978
< * PC_DEV_CAP2_REG(32bit):
---
> * PC_DEV_CAP2_REG(16bit):
870,871c982,983
< #define PCR_CZ_DEV_CAP2_REG 0x00000094
< /* sienaa0=pci_f0_config,hunta0=pci_f0_config */
---
> #define PCR_CC_DEV_CAP2_REG 0x00000094
> /* sienaa0=pci_f0_config */
873,882c985,989
< #define PCRF_DZ_OBFF_SUPPORTED_LBN 18
< #define PCRF_DZ_OBFF_SUPPORTED_WIDTH 2
< #define PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12
< #define PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2
< #define PCRF_DZ_LTR_M_SUPPORTED_LBN 11
< #define PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1
< #define PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4
< #define PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1
< #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4
< #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1
---
> #define PCR_DZ_DEV_CAP2_REG 0x000000e4
> /* hunta0=pci_f0_config */
>
> #define PCRF_CZ_CMPL_TIMEOUT_DIS_LBN 4
> #define PCRF_CZ_CMPL_TIMEOUT_DIS_WIDTH 1
894a1002
>
895a1004,1020
> * PC_MSIX_TBL_BASE_REG(32bit):
> * MSIX Capability Vector Table Base
> */
>
> #define PCR_BB_MSIX_TBL_BASE_REG 0x00000094
> /* falconb0=pci_f0_config */
>
> #define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4
> /* sienaa0,hunta0=pci_f0_config */
>
> #define PCRF_BZ_MSIX_TBL_OFF_LBN 3
> #define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29
> #define PCRF_BZ_MSIX_TBL_BIR_LBN 0
> #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3
>
>
> /*
900,901c1025,1026
< #define PCR_CZ_DEV_CTL2_REG 0x00000098
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_DEV_CTL2_REG 0x00000098
> /* sienaa0=pci_f0_config */
903,910c1028,1030
< #define PCRF_DZ_OBFF_ENABLE_LBN 13
< #define PCRF_DZ_OBFF_ENABLE_WIDTH 2
< #define PCRF_DZ_LTR_ENABLE_LBN 10
< #define PCRF_DZ_LTR_ENABLE_WIDTH 1
< #define PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9
< #define PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1
< #define PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8
< #define PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1
---
> #define PCR_DZ_DEV_CTL2_REG 0x000000e8
> /* hunta0=pci_f0_config */
>
915a1036
>
932,935d1052
< /*
< * PC_LNK_CAP2_REG(32bit):
< * PCIe Link Capability 2
< */
937,942d1053
< #define PCR_DZ_LNK_CAP2_REG 0x0000009c
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LNK_SPEED_SUP_LBN 1
< #define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7
<
948,949c1059,1060
< #define PCR_CZ_LNK_CTL2_REG 0x000000a0
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_LNK_CTL2_REG 0x000000a0
> /* sienaa0=pci_f0_config */
950a1062,1064
> #define PCR_DZ_LNK_CTL2_REG 0x000000f0
> /* hunta0=pci_f0_config */
>
967,969d1080
< #define PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3
< #define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2
< #define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1
970a1082
>
976,977c1088,1089
< #define PCR_CZ_LNK_STAT2_REG 0x000000a2
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_LNK_STAT2_REG 0x000000a2
> /* sienaa0=pci_f0_config */
978a1091,1093
> #define PCR_DZ_LNK_STAT2_REG 0x000000f2
> /* hunta0=pci_f0_config */
>
981a1097
>
992a1109
>
1003a1121
>
1017,1020d1134
< /*
< * PC_VPD_CAP_DATA_REG(32bit):
< * documentation to be written for sum_PC_VPD_CAP_DATA_REG
< */
1022,1030d1135
< #define PCR_AB_VPD_CAP_DATA_REG 0x000000b4
< /* falcona0,falconb0=pci_f0_config */
<
< #define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4
< /* sienaa0,hunta0=pci_f0_config */
<
< #define PCRF_AZ_VPD_DATA_LBN 0
< #define PCRF_AZ_VPD_DATA_WIDTH 32
<
1032,1048d1136
< * PC_VPD_CAP_CTL_REG(8bit):
< * VPD control and capabilities register
< */
<
< #define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0
< /* sienaa0,hunta0=pci_f0_config */
<
< #define PCRF_CZ_VPD_FLAG_LBN 31
< #define PCRF_CZ_VPD_FLAG_WIDTH 1
< #define PCRF_CZ_VPD_ADDR_LBN 16
< #define PCRF_CZ_VPD_ADDR_WIDTH 15
< #define PCRF_CZ_VPD_NXT_PTR_LBN 8
< #define PCRF_CZ_VPD_NXT_PTR_WIDTH 8
< #define PCRF_CZ_VPD_CAP_ID_LBN 0
< #define PCRF_CZ_VPD_CAP_ID_WIDTH 8
<
< /*
1062a1151
>
1093a1183
>
1102,1105d1191
< #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24
< #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1
< #define PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22
< #define PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1
1128a1215
>
1159a1247
>
1180a1269
>
1201a1291
>
1220a1311
>
1231a1323
>
1237,1238c1329,1330
< #define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_DEVSN_CAP_HDR_REG 0x00000130
> /* hunta0=pci_f0_config */
1239a1332,1334
> #define PCR_CC_DEVSN_CAP_HDR_REG 0x00000140
> /* sienaa0=pci_f0_config */
>
1246a1342
>
1252,1253c1348,1349
< #define PCR_CZ_DEVSN_DWORD0_REG 0x00000144
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_DEVSN_DWORD0_REG 0x00000134
> /* hunta0=pci_f0_config */
1254a1351,1353
> #define PCR_CC_DEVSN_DWORD0_REG 0x00000144
> /* sienaa0=pci_f0_config */
>
1257a1357
>
1263,1264c1363,1364
< #define PCR_CZ_DEVSN_DWORD1_REG 0x00000148
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_DEVSN_DWORD1_REG 0x00000138
> /* hunta0=pci_f0_config */
1265a1366,1368
> #define PCR_CC_DEVSN_DWORD1_REG 0x00000148
> /* sienaa0=pci_f0_config */
>
1268a1372
>
1274,1275c1378,1379
< #define PCR_CZ_ARI_CAP_HDR_REG 0x00000150
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_ARI_CAP_HDR_REG 0x00000140
> /* hunta0=pci_f0_config */
1276a1381,1383
> #define PCR_CC_ARI_CAP_HDR_REG 0x00000150
> /* sienaa0=pci_f0_config */
>
1283a1391
>
1289,1290c1397,1398
< #define PCR_CZ_ARI_CAP_REG 0x00000154
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_ARI_CAP_REG 0x00000144
> /* hunta0=pci_f0_config */
1291a1400,1402
> #define PCR_CC_ARI_CAP_REG 0x00000154
> /* sienaa0=pci_f0_config */
>
1298a1410
>
1304,1305c1416,1417
< #define PCR_CZ_ARI_CTL_REG 0x00000156
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_ARI_CTL_REG 0x00000146
> /* hunta0=pci_f0_config */
1306a1419,1421
> #define PCR_CC_ARI_CTL_REG 0x00000156
> /* sienaa0=pci_f0_config */
>
1314,1317d1428
< /*
< * PC_SEC_PCIE_CAP_REG(32bit):
< * Secondary PCIE Capability Register
< */
1319,1328d1429
< #define PCR_DZ_SEC_PCIE_CAP_REG 0x00000160
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_SEC_NXT_PTR_LBN 20
< #define PCRF_DZ_SEC_NXT_PTR_WIDTH 12
< #define PCRF_DZ_SEC_VERSION_LBN 16
< #define PCRF_DZ_SEC_VERSION_WIDTH 4
< #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0
< #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16
<
1337c1438
< #define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180
---
> #define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000200
1346a1448
>
1355c1457
< #define PCR_DZ_SRIOV_CAP_REG 0x00000184
---
> #define PCR_DZ_SRIOV_CAP_REG 0x00000204
1360,1361d1461
< #define PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1
< #define PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1
1365,1368d1464
< /*
< * PC_LINK_CONTROL3_REG(32bit):
< * Link Control 3.
< */
1370,1377d1465
< #define PCR_DZ_LINK_CONTROL3_REG 0x00000164
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LINK_EQ_INT_EN_LBN 1
< #define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1
< #define PCRF_DZ_PERFORM_EQL_LBN 0
< #define PCRF_DZ_PERFORM_EQL_WIDTH 1
<
1379,1389d1466
< * PC_LANE_ERROR_STAT_REG(32bit):
< * Lane Error Status Register.
< */
<
< #define PCR_DZ_LANE_ERROR_STAT_REG 0x00000168
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LANE_STATUS_LBN 0
< #define PCRF_DZ_LANE_STATUS_WIDTH 8
<
< /*
1397c1474
< #define PCR_DZ_SRIOV_CTL_REG 0x00000188
---
> #define PCR_DZ_SRIOV_CTL_REG 0x00000208
1410a1488
>
1419c1497
< #define PCR_DZ_SRIOV_STAT_REG 0x0000018a
---
> #define PCR_DZ_SRIOV_STAT_REG 0x0000020a
1425,1428d1502
< /*
< * PC_LANE01_EQU_CONTROL_REG(32bit):
< * Lanes 0,1 Equalization Control Register.
< */
1430,1437d1503
< #define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LANE1_EQ_CTRL_LBN 16
< #define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16
< #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0
< #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16
<
1446c1512
< #define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c
---
> #define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000020c
1451a1518
>
1460c1527
< #define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e
---
> #define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000020e
1465a1533
>
1474c1542
< #define PCR_DZ_SRIOV_NUMVFS_REG 0x00000190
---
> #define PCR_DZ_SRIOV_NUMVFS_REG 0x00000210
1480,1483d1547
< /*
< * PC_LANE23_EQU_CONTROL_REG(32bit):
< * Lanes 2,3 Equalization Control Register.
< */
1485,1492d1548
< #define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LANE3_EQ_CTRL_LBN 16
< #define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16
< #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0
< #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16
<
1501c1557
< #define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192
---
> #define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000212
1506a1563
>
1515c1572
< #define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194
---
> #define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000214
1521,1524d1577
< /*
< * PC_LANE45_EQU_CONTROL_REG(32bit):
< * Lanes 4,5 Equalization Control Register.
< */
1526,1533d1578
< #define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LANE5_EQ_CTRL_LBN 16
< #define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16
< #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0
< #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16
<
1542c1587
< #define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196
---
> #define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000216
1548,1551d1592
< /*
< * PC_LANE67_EQU_CONTROL_REG(32bit):
< * Lanes 6,7 Equalization Control Register.
< */
1553,1560d1593
< #define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LANE7_EQ_CTRL_LBN 16
< #define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16
< #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0
< #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16
<
1569c1602
< #define PCR_DZ_SRIOV_DEVID_REG 0x0000019a
---
> #define PCR_DZ_SRIOV_DEVID_REG 0x0000021a
1574a1608
>
1583c1617
< #define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c
---
> #define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000021c
1588a1623
>
1597c1632
< #define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0
---
> #define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x00000220
1602a1638
>
1611c1647
< #define PCR_DZ_SRIOV_BAR0_REG 0x000001a4
---
> #define PCR_DZ_SRIOV_BAR0_REG 0x00000224
1616,1623c1652,1653
< #define PCRF_DZ_VF_BAR0_ADDRESS_LBN 4
< #define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28
< #define PCRF_DZ_VF_BAR0_PREF_LBN 3
< #define PCRF_DZ_VF_BAR0_PREF_WIDTH 1
< #define PCRF_DZ_VF_BAR0_TYPE_LBN 1
< #define PCRF_DZ_VF_BAR0_TYPE_WIDTH 2
< #define PCRF_DZ_VF_BAR0_IOM_LBN 0
< #define PCRF_DZ_VF_BAR0_IOM_WIDTH 1
---
> #define PCRF_DZ_VF_BAR0_ADDRESS_LBN 0
> #define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 32
1624a1655
>
1633c1664
< #define PCR_DZ_SRIOV_BAR1_REG 0x000001a8
---
> #define PCR_DZ_SRIOV_BAR1_REG 0x00000228
1640a1672
>
1649c1681
< #define PCR_DZ_SRIOV_BAR2_REG 0x000001ac
---
> #define PCR_DZ_SRIOV_BAR2_REG 0x0000022c
1654,1661c1686,1687
< #define PCRF_DZ_VF_BAR2_ADDRESS_LBN 4
< #define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28
< #define PCRF_DZ_VF_BAR2_PREF_LBN 3
< #define PCRF_DZ_VF_BAR2_PREF_WIDTH 1
< #define PCRF_DZ_VF_BAR2_TYPE_LBN 1
< #define PCRF_DZ_VF_BAR2_TYPE_WIDTH 2
< #define PCRF_DZ_VF_BAR2_IOM_LBN 0
< #define PCRF_DZ_VF_BAR2_IOM_WIDTH 1
---
> #define PCRF_DZ_VF_BAR2_ADDRESS_LBN 0
> #define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 32
1662a1689
>
1671c1698
< #define PCR_DZ_SRIOV_BAR3_REG 0x000001b0
---
> #define PCR_DZ_SRIOV_BAR3_REG 0x00000230
1678a1706
>
1687c1715
< #define PCR_DZ_SRIOV_BAR4_REG 0x000001b4
---
> #define PCR_DZ_SRIOV_BAR4_REG 0x00000234
1694a1723
>
1703c1732
< #define PCR_DZ_SRIOV_BAR5_REG 0x000001b8
---
> #define PCR_DZ_SRIOV_BAR5_REG 0x00000238
1711,1714d1739
< /*
< * PC_SRIOV_RSVD_REG(16bit):
< * Reserved register
< */
1716,1721d1740
< #define PCR_DZ_SRIOV_RSVD_REG 0x00000198
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_VF_RSVD_LBN 0
< #define PCRF_DZ_VF_RSVD_WIDTH 16
<
1730c1749
< #define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc
---
> #define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000023c
1737a1757
>
1738a1759,1792
> * PC_LTR_CAP_HDR_REG(32bit):
> * Latency Tolerance Reporting Cap Header Reg
> */
>
> #define PCR_DZ_LTR_CAP_HDR_REG 0x00000240
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LTR_NXT_PTR_LBN 20
> #define PCRF_DZ_LTR_NXT_PTR_WIDTH 12
> #define PCRF_DZ_LTR_VERSION_LBN 16
> #define PCRF_DZ_LTR_VERSION_WIDTH 4
> #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0
> #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16
>
>
> /*
> * PC_LTR_MAX_SNOOP_REG(32bit):
> * LTR Maximum Snoop/No Snoop Register
> */
>
> #define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000244
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26
> #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3
> #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16
> #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10
> #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10
> #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3
> #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0
> #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10
>
>
> /*
1743c1797
< #define PCR_DZ_TPH_CAP_HDR_REG 0x000001c0
---
> #define PCR_DZ_TPH_CAP_HDR_REG 0x00000274
1752a1807
>
1758c1813
< #define PCR_DZ_TPH_REQ_CAP_REG 0x000001c4
---
> #define PCR_DZ_TPH_REQ_CAP_REG 0x00000278
1773a1829
>
1779c1835
< #define PCR_DZ_TPH_REQ_CTL_REG 0x000001c8
---
> #define PCR_DZ_TPH_REQ_CTL_REG 0x0000027c
1786a1843
>
1788,1789c1845,1846
< * PC_LTR_CAP_HDR_REG(32bit):
< * Latency Tolerance Reporting Cap Header Reg
---
> * PC_SEC_PCIE_CAP_REG(32bit):
> * Secondary PCIE Capability Register
1792c1849
< #define PCR_DZ_LTR_CAP_HDR_REG 0x00000290
---
> #define PCR_DZ_SEC_PCIE_CAP_REG 0x00000300
1795,1800c1852,1857
< #define PCRF_DZ_LTR_NXT_PTR_LBN 20
< #define PCRF_DZ_LTR_NXT_PTR_WIDTH 12
< #define PCRF_DZ_LTR_VERSION_LBN 16
< #define PCRF_DZ_LTR_VERSION_WIDTH 4
< #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0
< #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16
---
> #define PCRF_DZ_SEC_NXT_PTR_LBN 20
> #define PCRF_DZ_SEC_NXT_PTR_WIDTH 12
> #define PCRF_DZ_SEC_VERSION_LBN 16
> #define PCRF_DZ_SEC_VERSION_WIDTH 4
> #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0
> #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16
1801a1859
>
1803,1804c1861,1862
< * PC_LTR_MAX_SNOOP_REG(32bit):
< * LTR Maximum Snoop/No Snoop Register
---
> * PC_LINK_CONTROL3_REG(32bit):
> * Link Control 3.
1807c1865
< #define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294
---
> #define PCR_DZ_LINK_CONTROL3_REG 0x00000304
1810,1817c1868,1871
< #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26
< #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3
< #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16
< #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10
< #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10
< #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3
< #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0
< #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10
---
> #define PCRF_DZ_LINK_EQ_INT_EN_LBN 1
> #define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1
> #define PCRF_DZ_PERFORM_EQL_LBN 0
> #define PCRF_DZ_PERFORM_EQL_WIDTH 1
1818a1873
>
1819a1875,1942
> * PC_LANE_ERROR_STAT_REG(32bit):
> * Lane Error Status Register.
> */
>
> #define PCR_DZ_LANE_ERROR_STAT_REG 0x00000308
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LANE_STATUS_LBN 0
> #define PCRF_DZ_LANE_STATUS_WIDTH 8
>
>
> /*
> * PC_LANE01_EQU_CONTROL_REG(32bit):
> * Lanes 0,1 Equalization Control Register.
> */
>
> #define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000030c
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LANE1_EQ_CTRL_LBN 16
> #define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16
> #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0
> #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16
>
>
> /*
> * PC_LANE23_EQU_CONTROL_REG(32bit):
> * Lanes 2,3 Equalization Control Register.
> */
>
> #define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000310
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LANE3_EQ_CTRL_LBN 16
> #define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16
> #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0
> #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16
>
>
> /*
> * PC_LANE45_EQU_CONTROL_REG(32bit):
> * Lanes 4,5 Equalization Control Register.
> */
>
> #define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000314
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LANE5_EQ_CTRL_LBN 16
> #define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16
> #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0
> #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16
>
>
> /*
> * PC_LANE67_EQU_CONTROL_REG(32bit):
> * Lanes 6,7 Equalization Control Register.
> */
>
> #define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000318
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LANE7_EQ_CTRL_LBN 16
> #define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16
> #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0
> #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16
>
>
> /*
1831a1955
>
1848a1973
>
1863a1989
>
1886a2013
>
1923a2051
>
1946a2075
>
1973a2103
>
1992a2123
>
2008,2011d2138
< /*
< * PC_FLT_MSK_REG(32bit):
< * Filter Mask Register 2
< */
2013,2018d2139
< #define PCR_CC_FLT_MSK_REG 0x00000720
< /* sienaa0=pci_f0_config */
<
< #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0
< #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32
<
2038a2160
>
2039a2162,2173
> * PC_FLT_MSK_REG(32bit):
> * Filter Mask Register 2
> */
>
> #define PCR_CC_FLT_MSK_REG 0x00000720
> /* sienaa0=pci_f0_config */
>
> #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0
> #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32
>
>
> /*
2066a2201
>
2085a2221
>
2104a2241
>
2117a2255
>
2130a2269
>
2143a2283
>
2158a2299
>
2166a2308,2309
>
>
2174a2318,2319
>
>
2182a2328,2329
>
>
2190a2338,2339
>
>
2198a2348,2349
>
>
2219a2371
>
< * SPDX-License-Identifier: BSD-2-Clause
---
> * Copyright 2007-2010 Solarflare Communications Inc. All rights reserved.
4,6d3
< * Copyright (c) 2007-2016 Solarflare Communications Inc.
< * All rights reserved.
< *
8c5,11
< * modification, are permitted provided that the following conditions are met:
---
> * modification, are permitted provided that the following conditions
> * are met:
> * 1. Redistributions of source code must retain the above copyright
> * notice, this list of conditions and the following disclaimer.
> * 2. Redistributions in binary form must reproduce the above copyright
> * notice, this list of conditions and the following disclaimer in the
> * documentation and/or other materials provided with the distribution.
10,30c13,23
< * 1. Redistributions of source code must retain the above copyright notice,
< * this list of conditions and the following disclaimer.
< * 2. Redistributions in binary form must reproduce the above copyright notice,
< * this list of conditions and the following disclaimer in the documentation
< * and/or other materials provided with the distribution.
< *
< * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
< * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
< * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
< * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
< * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
< * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
< * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
< * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
< * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
< * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
< * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
< *
< * The views and conclusions contained in the software and documentation are
< * those of the authors and should not be interpreted as representing official
< * policies, either expressed or implied, of the FreeBSD Project.
---
> * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
> * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
> * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> * SUCH DAMAGE.
50a44
>
61a56
>
92a88
>
123a120
>
134a132
>
149a148
>
160a160
>
171a172
>
184a186
>
195a198
>
212a216
>
223a228
>
240a246
>
251a258
>
268a276
>
279a288
>
290a300
>
301a312
>
320a332
>
331a344
>
342a356
>
353,356d366
< #define PCFE_DZ_INTPIN_INTD 4
< #define PCFE_DZ_INTPIN_INTC 3
< #define PCFE_DZ_INTPIN_INTB 2
< #define PCFE_DZ_INTPIN_INTA 1
357a368
>
363,364c374,375
< #define PCR_AZ_PM_CAP_ID_REG 0x00000040
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_PM_CAP_ID_REG 0x00000040
> /* falcona0,falconb0,sienaa0=pci_f0_config */
365a377,379
> #define PCR_DZ_PM_CAP_ID_REG 0x00000080
> /* hunta0=pci_f0_config */
>
368a383
>
374,375c389,390
< #define PCR_AZ_PM_NXT_PTR_REG 0x00000041
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_PM_NXT_PTR_REG 0x00000041
> /* falcona0,falconb0,sienaa0=pci_f0_config */
376a392,394
> #define PCR_DZ_PM_NXT_PTR_REG 0x00000081
> /* hunta0=pci_f0_config */
>
379a398
>
385,386c404,405
< #define PCR_AZ_PM_CAP_REG 0x00000042
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_PM_CAP_REG 0x00000042
> /* falcona0,falconb0,sienaa0=pci_f0_config */
387a407,409
> #define PCR_DZ_PM_CAP_REG 0x00000082
> /* hunta0=pci_f0_config */
>
402a425
>
408,409c431,432
< #define PCR_AZ_PM_CS_REG 0x00000044
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_PM_CS_REG 0x00000044
> /* falcona0,falconb0,sienaa0=pci_f0_config */
410a434,436
> #define PCR_DZ_PM_CS_REG 0x00000084
> /* hunta0=pci_f0_config */
>
423a450
>
429,430c456,457
< #define PCR_AZ_MSI_CAP_ID_REG 0x00000050
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_CAP_ID_REG 0x00000050
> /* falcona0,falconb0,sienaa0=pci_f0_config */
431a459,461
> #define PCR_DZ_MSI_CAP_ID_REG 0x00000090
> /* hunta0=pci_f0_config */
>
434a465
>
440,441c471,472
< #define PCR_AZ_MSI_NXT_PTR_REG 0x00000051
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_NXT_PTR_REG 0x00000051
> /* falcona0,falconb0,sienaa0=pci_f0_config */
442a474,476
> #define PCR_DZ_MSI_NXT_PTR_REG 0x00000091
> /* hunta0=pci_f0_config */
>
445a480
>
451,452c486,487
< #define PCR_AZ_MSI_CTL_REG 0x00000052
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_CTL_REG 0x00000052
> /* falcona0,falconb0,sienaa0=pci_f0_config */
453a489,491
> #define PCR_DZ_MSI_CTL_REG 0x00000092
> /* hunta0=pci_f0_config */
>
462a501
>
468,469c507,508
< #define PCR_AZ_MSI_ADR_LO_REG 0x00000054
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_ADR_LO_REG 0x00000054
> /* falcona0,falconb0,sienaa0=pci_f0_config */
470a510,512
> #define PCR_DZ_MSI_ADR_LO_REG 0x00000094
> /* hunta0=pci_f0_config */
>
473a516
>
474a518,556
> * PC_VPD_CAP_CTL_REG(8bit):
> * VPD control and capabilities register
> */
>
> #define PCR_DZ_VPD_CAP_CTL_REG 0x00000054
> /* hunta0=pci_f0_config */
>
> #define PCR_CC_VPD_CAP_CTL_REG 0x000000d0
> /* sienaa0=pci_f0_config */
>
> #define PCRF_CZ_VPD_FLAG_LBN 31
> #define PCRF_CZ_VPD_FLAG_WIDTH 1
> #define PCRF_CZ_VPD_ADDR_LBN 16
> #define PCRF_CZ_VPD_ADDR_WIDTH 15
> #define PCRF_CZ_VPD_NXT_PTR_LBN 8
> #define PCRF_CZ_VPD_NXT_PTR_WIDTH 8
> #define PCRF_CZ_VPD_CAP_ID_LBN 0
> #define PCRF_CZ_VPD_CAP_ID_WIDTH 8
>
>
> /*
> * PC_VPD_CAP_DATA_REG(32bit):
> * documentation to be written for sum_PC_VPD_CAP_DATA_REG
> */
>
> #define PCR_DZ_VPD_CAP_DATA_REG 0x00000058
> /* hunta0=pci_f0_config */
>
> #define PCR_AB_VPD_CAP_DATA_REG 0x000000b4
> /* falcona0,falconb0=pci_f0_config */
>
> #define PCR_CC_VPD_CAP_DATA_REG 0x000000d4
> /* sienaa0=pci_f0_config */
>
> #define PCRF_AZ_VPD_DATA_LBN 0
> #define PCRF_AZ_VPD_DATA_WIDTH 32
>
>
> /*
479,480c561,562
< #define PCR_AZ_MSI_ADR_HI_REG 0x00000058
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_ADR_HI_REG 0x00000058
> /* falcona0,falconb0,sienaa0=pci_f0_config */
481a564,566
> #define PCR_DZ_MSI_ADR_HI_REG 0x00000098
> /* hunta0=pci_f0_config */
>
484a570
>
490,491c576,577
< #define PCR_AZ_MSI_DAT_REG 0x0000005c
< /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */
---
> #define PCR_AC_MSI_DAT_REG 0x0000005c
> /* falcona0,falconb0,sienaa0=pci_f0_config */
492a579,581
> #define PCR_DZ_MSI_DAT_REG 0x0000009c
> /* hunta0=pci_f0_config */
>
495a585
>
504,505c594,595
< #define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_PCIE_CAP_LIST_REG 0x00000070
> /* sienaa0=pci_f0_config */
506a597,599
> #define PCR_DZ_PCIE_CAP_LIST_REG 0x000000c0
> /* hunta0=pci_f0_config */
>
511a605
>
520,521c614,615
< #define PCR_CZ_PCIE_CAP_REG 0x00000072
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_PCIE_CAP_REG 0x00000072
> /* sienaa0=pci_f0_config */
522a617,619
> #define PCR_DZ_PCIE_CAP_REG 0x000000c2
> /* hunta0=pci_f0_config */
>
531a629
>
540,541c638,639
< #define PCR_CZ_DEV_CAP_REG 0x00000074
< /* sienaa0=pci_f0_config,hunta0=pci_f0_config */
---
> #define PCR_CC_DEV_CAP_REG 0x00000074
> /* sienaa0=pci_f0_config */
542a641,643
> #define PCR_DZ_DEV_CAP_REG 0x000000c4
> /* hunta0=pci_f0_config */
>
567a669
>
576,577c678,679
< #define PCR_CZ_DEV_CTL_REG 0x00000078
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_DEV_CTL_REG 0x00000078
> /* sienaa0=pci_f0_config */
578a681,683
> #define PCR_DZ_DEV_CTL_REG 0x000000c8
> /* hunta0=pci_f0_config */
>
588a694
> #define PCFE_DZ_OTHER other
606a713
> #define PCFE_DZ_OTHER other
617a725
>
626,627c734,735
< #define PCR_CZ_DEV_STAT_REG 0x0000007a
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_DEV_STAT_REG 0x0000007a
> /* sienaa0=pci_f0_config */
628a737,739
> #define PCR_DZ_DEV_STAT_REG 0x000000ca
> /* hunta0=pci_f0_config */
>
641a753
>
650,651c762,763
< #define PCR_CZ_LNK_CAP_REG 0x0000007c
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_LNK_CAP_REG 0x0000007c
> /* sienaa0=pci_f0_config */
652a765,767
> #define PCR_DZ_LNK_CAP_REG 0x000000cc
> /* hunta0=pci_f0_config */
>
655,656d769
< #define PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22
< #define PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1
675a789
>
684,685c798,799
< #define PCR_CZ_LNK_CTL_REG 0x00000080
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_LNK_CTL_REG 0x00000080
> /* sienaa0=pci_f0_config */
686a801,803
> #define PCR_DZ_LNK_CTL_REG 0x000000d0
> /* hunta0=pci_f0_config */
>
701a819
>
710,711c828,829
< #define PCR_CZ_LNK_STAT_REG 0x00000082
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_LNK_STAT_REG 0x00000082
> /* sienaa0=pci_f0_config */
712a831,833
> #define PCR_DZ_LNK_STAT_REG 0x000000d2
> /* hunta0=pci_f0_config */
>
723a845
>
752a875
>
779a903
>
802a927
>
816a942
>
830a957
>
849,852d975
< /*
< * PC_MSIX_TBL_BASE_REG(32bit):
< * MSIX Capability Vector Table Base
< */
854,864d976
< #define PCR_BB_MSIX_TBL_BASE_REG 0x00000094
< /* falconb0=pci_f0_config */
<
< #define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4
< /* sienaa0,hunta0=pci_f0_config */
<
< #define PCRF_BZ_MSIX_TBL_OFF_LBN 3
< #define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29
< #define PCRF_BZ_MSIX_TBL_BIR_LBN 0
< #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3
<
866c978
< * PC_DEV_CAP2_REG(32bit):
---
> * PC_DEV_CAP2_REG(16bit):
870,871c982,983
< #define PCR_CZ_DEV_CAP2_REG 0x00000094
< /* sienaa0=pci_f0_config,hunta0=pci_f0_config */
---
> #define PCR_CC_DEV_CAP2_REG 0x00000094
> /* sienaa0=pci_f0_config */
873,882c985,989
< #define PCRF_DZ_OBFF_SUPPORTED_LBN 18
< #define PCRF_DZ_OBFF_SUPPORTED_WIDTH 2
< #define PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12
< #define PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2
< #define PCRF_DZ_LTR_M_SUPPORTED_LBN 11
< #define PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1
< #define PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4
< #define PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1
< #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4
< #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1
---
> #define PCR_DZ_DEV_CAP2_REG 0x000000e4
> /* hunta0=pci_f0_config */
>
> #define PCRF_CZ_CMPL_TIMEOUT_DIS_LBN 4
> #define PCRF_CZ_CMPL_TIMEOUT_DIS_WIDTH 1
894a1002
>
895a1004,1020
> * PC_MSIX_TBL_BASE_REG(32bit):
> * MSIX Capability Vector Table Base
> */
>
> #define PCR_BB_MSIX_TBL_BASE_REG 0x00000094
> /* falconb0=pci_f0_config */
>
> #define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4
> /* sienaa0,hunta0=pci_f0_config */
>
> #define PCRF_BZ_MSIX_TBL_OFF_LBN 3
> #define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29
> #define PCRF_BZ_MSIX_TBL_BIR_LBN 0
> #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3
>
>
> /*
900,901c1025,1026
< #define PCR_CZ_DEV_CTL2_REG 0x00000098
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_DEV_CTL2_REG 0x00000098
> /* sienaa0=pci_f0_config */
903,910c1028,1030
< #define PCRF_DZ_OBFF_ENABLE_LBN 13
< #define PCRF_DZ_OBFF_ENABLE_WIDTH 2
< #define PCRF_DZ_LTR_ENABLE_LBN 10
< #define PCRF_DZ_LTR_ENABLE_WIDTH 1
< #define PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9
< #define PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1
< #define PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8
< #define PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1
---
> #define PCR_DZ_DEV_CTL2_REG 0x000000e8
> /* hunta0=pci_f0_config */
>
915a1036
>
932,935d1052
< /*
< * PC_LNK_CAP2_REG(32bit):
< * PCIe Link Capability 2
< */
937,942d1053
< #define PCR_DZ_LNK_CAP2_REG 0x0000009c
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LNK_SPEED_SUP_LBN 1
< #define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7
<
948,949c1059,1060
< #define PCR_CZ_LNK_CTL2_REG 0x000000a0
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_LNK_CTL2_REG 0x000000a0
> /* sienaa0=pci_f0_config */
950a1062,1064
> #define PCR_DZ_LNK_CTL2_REG 0x000000f0
> /* hunta0=pci_f0_config */
>
967,969d1080
< #define PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3
< #define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2
< #define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1
970a1082
>
976,977c1088,1089
< #define PCR_CZ_LNK_STAT2_REG 0x000000a2
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_CC_LNK_STAT2_REG 0x000000a2
> /* sienaa0=pci_f0_config */
978a1091,1093
> #define PCR_DZ_LNK_STAT2_REG 0x000000f2
> /* hunta0=pci_f0_config */
>
981a1097
>
992a1109
>
1003a1121
>
1017,1020d1134
< /*
< * PC_VPD_CAP_DATA_REG(32bit):
< * documentation to be written for sum_PC_VPD_CAP_DATA_REG
< */
1022,1030d1135
< #define PCR_AB_VPD_CAP_DATA_REG 0x000000b4
< /* falcona0,falconb0=pci_f0_config */
<
< #define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4
< /* sienaa0,hunta0=pci_f0_config */
<
< #define PCRF_AZ_VPD_DATA_LBN 0
< #define PCRF_AZ_VPD_DATA_WIDTH 32
<
1032,1048d1136
< * PC_VPD_CAP_CTL_REG(8bit):
< * VPD control and capabilities register
< */
<
< #define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0
< /* sienaa0,hunta0=pci_f0_config */
<
< #define PCRF_CZ_VPD_FLAG_LBN 31
< #define PCRF_CZ_VPD_FLAG_WIDTH 1
< #define PCRF_CZ_VPD_ADDR_LBN 16
< #define PCRF_CZ_VPD_ADDR_WIDTH 15
< #define PCRF_CZ_VPD_NXT_PTR_LBN 8
< #define PCRF_CZ_VPD_NXT_PTR_WIDTH 8
< #define PCRF_CZ_VPD_CAP_ID_LBN 0
< #define PCRF_CZ_VPD_CAP_ID_WIDTH 8
<
< /*
1062a1151
>
1093a1183
>
1102,1105d1191
< #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24
< #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1
< #define PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22
< #define PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1
1128a1215
>
1159a1247
>
1180a1269
>
1201a1291
>
1220a1311
>
1231a1323
>
1237,1238c1329,1330
< #define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_DEVSN_CAP_HDR_REG 0x00000130
> /* hunta0=pci_f0_config */
1239a1332,1334
> #define PCR_CC_DEVSN_CAP_HDR_REG 0x00000140
> /* sienaa0=pci_f0_config */
>
1246a1342
>
1252,1253c1348,1349
< #define PCR_CZ_DEVSN_DWORD0_REG 0x00000144
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_DEVSN_DWORD0_REG 0x00000134
> /* hunta0=pci_f0_config */
1254a1351,1353
> #define PCR_CC_DEVSN_DWORD0_REG 0x00000144
> /* sienaa0=pci_f0_config */
>
1257a1357
>
1263,1264c1363,1364
< #define PCR_CZ_DEVSN_DWORD1_REG 0x00000148
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_DEVSN_DWORD1_REG 0x00000138
> /* hunta0=pci_f0_config */
1265a1366,1368
> #define PCR_CC_DEVSN_DWORD1_REG 0x00000148
> /* sienaa0=pci_f0_config */
>
1268a1372
>
1274,1275c1378,1379
< #define PCR_CZ_ARI_CAP_HDR_REG 0x00000150
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_ARI_CAP_HDR_REG 0x00000140
> /* hunta0=pci_f0_config */
1276a1381,1383
> #define PCR_CC_ARI_CAP_HDR_REG 0x00000150
> /* sienaa0=pci_f0_config */
>
1283a1391
>
1289,1290c1397,1398
< #define PCR_CZ_ARI_CAP_REG 0x00000154
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_ARI_CAP_REG 0x00000144
> /* hunta0=pci_f0_config */
1291a1400,1402
> #define PCR_CC_ARI_CAP_REG 0x00000154
> /* sienaa0=pci_f0_config */
>
1298a1410
>
1304,1305c1416,1417
< #define PCR_CZ_ARI_CTL_REG 0x00000156
< /* sienaa0,hunta0=pci_f0_config */
---
> #define PCR_DZ_ARI_CTL_REG 0x00000146
> /* hunta0=pci_f0_config */
1306a1419,1421
> #define PCR_CC_ARI_CTL_REG 0x00000156
> /* sienaa0=pci_f0_config */
>
1314,1317d1428
< /*
< * PC_SEC_PCIE_CAP_REG(32bit):
< * Secondary PCIE Capability Register
< */
1319,1328d1429
< #define PCR_DZ_SEC_PCIE_CAP_REG 0x00000160
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_SEC_NXT_PTR_LBN 20
< #define PCRF_DZ_SEC_NXT_PTR_WIDTH 12
< #define PCRF_DZ_SEC_VERSION_LBN 16
< #define PCRF_DZ_SEC_VERSION_WIDTH 4
< #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0
< #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16
<
1337c1438
< #define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180
---
> #define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000200
1346a1448
>
1355c1457
< #define PCR_DZ_SRIOV_CAP_REG 0x00000184
---
> #define PCR_DZ_SRIOV_CAP_REG 0x00000204
1360,1361d1461
< #define PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1
< #define PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1
1365,1368d1464
< /*
< * PC_LINK_CONTROL3_REG(32bit):
< * Link Control 3.
< */
1370,1377d1465
< #define PCR_DZ_LINK_CONTROL3_REG 0x00000164
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LINK_EQ_INT_EN_LBN 1
< #define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1
< #define PCRF_DZ_PERFORM_EQL_LBN 0
< #define PCRF_DZ_PERFORM_EQL_WIDTH 1
<
1379,1389d1466
< * PC_LANE_ERROR_STAT_REG(32bit):
< * Lane Error Status Register.
< */
<
< #define PCR_DZ_LANE_ERROR_STAT_REG 0x00000168
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LANE_STATUS_LBN 0
< #define PCRF_DZ_LANE_STATUS_WIDTH 8
<
< /*
1397c1474
< #define PCR_DZ_SRIOV_CTL_REG 0x00000188
---
> #define PCR_DZ_SRIOV_CTL_REG 0x00000208
1410a1488
>
1419c1497
< #define PCR_DZ_SRIOV_STAT_REG 0x0000018a
---
> #define PCR_DZ_SRIOV_STAT_REG 0x0000020a
1425,1428d1502
< /*
< * PC_LANE01_EQU_CONTROL_REG(32bit):
< * Lanes 0,1 Equalization Control Register.
< */
1430,1437d1503
< #define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LANE1_EQ_CTRL_LBN 16
< #define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16
< #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0
< #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16
<
1446c1512
< #define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c
---
> #define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000020c
1451a1518
>
1460c1527
< #define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e
---
> #define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000020e
1465a1533
>
1474c1542
< #define PCR_DZ_SRIOV_NUMVFS_REG 0x00000190
---
> #define PCR_DZ_SRIOV_NUMVFS_REG 0x00000210
1480,1483d1547
< /*
< * PC_LANE23_EQU_CONTROL_REG(32bit):
< * Lanes 2,3 Equalization Control Register.
< */
1485,1492d1548
< #define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LANE3_EQ_CTRL_LBN 16
< #define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16
< #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0
< #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16
<
1501c1557
< #define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192
---
> #define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000212
1506a1563
>
1515c1572
< #define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194
---
> #define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000214
1521,1524d1577
< /*
< * PC_LANE45_EQU_CONTROL_REG(32bit):
< * Lanes 4,5 Equalization Control Register.
< */
1526,1533d1578
< #define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LANE5_EQ_CTRL_LBN 16
< #define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16
< #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0
< #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16
<
1542c1587
< #define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196
---
> #define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000216
1548,1551d1592
< /*
< * PC_LANE67_EQU_CONTROL_REG(32bit):
< * Lanes 6,7 Equalization Control Register.
< */
1553,1560d1593
< #define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_LANE7_EQ_CTRL_LBN 16
< #define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16
< #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0
< #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16
<
1569c1602
< #define PCR_DZ_SRIOV_DEVID_REG 0x0000019a
---
> #define PCR_DZ_SRIOV_DEVID_REG 0x0000021a
1574a1608
>
1583c1617
< #define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c
---
> #define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000021c
1588a1623
>
1597c1632
< #define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0
---
> #define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x00000220
1602a1638
>
1611c1647
< #define PCR_DZ_SRIOV_BAR0_REG 0x000001a4
---
> #define PCR_DZ_SRIOV_BAR0_REG 0x00000224
1616,1623c1652,1653
< #define PCRF_DZ_VF_BAR0_ADDRESS_LBN 4
< #define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28
< #define PCRF_DZ_VF_BAR0_PREF_LBN 3
< #define PCRF_DZ_VF_BAR0_PREF_WIDTH 1
< #define PCRF_DZ_VF_BAR0_TYPE_LBN 1
< #define PCRF_DZ_VF_BAR0_TYPE_WIDTH 2
< #define PCRF_DZ_VF_BAR0_IOM_LBN 0
< #define PCRF_DZ_VF_BAR0_IOM_WIDTH 1
---
> #define PCRF_DZ_VF_BAR0_ADDRESS_LBN 0
> #define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 32
1624a1655
>
1633c1664
< #define PCR_DZ_SRIOV_BAR1_REG 0x000001a8
---
> #define PCR_DZ_SRIOV_BAR1_REG 0x00000228
1640a1672
>
1649c1681
< #define PCR_DZ_SRIOV_BAR2_REG 0x000001ac
---
> #define PCR_DZ_SRIOV_BAR2_REG 0x0000022c
1654,1661c1686,1687
< #define PCRF_DZ_VF_BAR2_ADDRESS_LBN 4
< #define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28
< #define PCRF_DZ_VF_BAR2_PREF_LBN 3
< #define PCRF_DZ_VF_BAR2_PREF_WIDTH 1
< #define PCRF_DZ_VF_BAR2_TYPE_LBN 1
< #define PCRF_DZ_VF_BAR2_TYPE_WIDTH 2
< #define PCRF_DZ_VF_BAR2_IOM_LBN 0
< #define PCRF_DZ_VF_BAR2_IOM_WIDTH 1
---
> #define PCRF_DZ_VF_BAR2_ADDRESS_LBN 0
> #define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 32
1662a1689
>
1671c1698
< #define PCR_DZ_SRIOV_BAR3_REG 0x000001b0
---
> #define PCR_DZ_SRIOV_BAR3_REG 0x00000230
1678a1706
>
1687c1715
< #define PCR_DZ_SRIOV_BAR4_REG 0x000001b4
---
> #define PCR_DZ_SRIOV_BAR4_REG 0x00000234
1694a1723
>
1703c1732
< #define PCR_DZ_SRIOV_BAR5_REG 0x000001b8
---
> #define PCR_DZ_SRIOV_BAR5_REG 0x00000238
1711,1714d1739
< /*
< * PC_SRIOV_RSVD_REG(16bit):
< * Reserved register
< */
1716,1721d1740
< #define PCR_DZ_SRIOV_RSVD_REG 0x00000198
< /* hunta0=pci_f0_config */
<
< #define PCRF_DZ_VF_RSVD_LBN 0
< #define PCRF_DZ_VF_RSVD_WIDTH 16
<
1730c1749
< #define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc
---
> #define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000023c
1737a1757
>
1738a1759,1792
> * PC_LTR_CAP_HDR_REG(32bit):
> * Latency Tolerance Reporting Cap Header Reg
> */
>
> #define PCR_DZ_LTR_CAP_HDR_REG 0x00000240
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LTR_NXT_PTR_LBN 20
> #define PCRF_DZ_LTR_NXT_PTR_WIDTH 12
> #define PCRF_DZ_LTR_VERSION_LBN 16
> #define PCRF_DZ_LTR_VERSION_WIDTH 4
> #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0
> #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16
>
>
> /*
> * PC_LTR_MAX_SNOOP_REG(32bit):
> * LTR Maximum Snoop/No Snoop Register
> */
>
> #define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000244
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26
> #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3
> #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16
> #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10
> #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10
> #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3
> #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0
> #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10
>
>
> /*
1743c1797
< #define PCR_DZ_TPH_CAP_HDR_REG 0x000001c0
---
> #define PCR_DZ_TPH_CAP_HDR_REG 0x00000274
1752a1807
>
1758c1813
< #define PCR_DZ_TPH_REQ_CAP_REG 0x000001c4
---
> #define PCR_DZ_TPH_REQ_CAP_REG 0x00000278
1773a1829
>
1779c1835
< #define PCR_DZ_TPH_REQ_CTL_REG 0x000001c8
---
> #define PCR_DZ_TPH_REQ_CTL_REG 0x0000027c
1786a1843
>
1788,1789c1845,1846
< * PC_LTR_CAP_HDR_REG(32bit):
< * Latency Tolerance Reporting Cap Header Reg
---
> * PC_SEC_PCIE_CAP_REG(32bit):
> * Secondary PCIE Capability Register
1792c1849
< #define PCR_DZ_LTR_CAP_HDR_REG 0x00000290
---
> #define PCR_DZ_SEC_PCIE_CAP_REG 0x00000300
1795,1800c1852,1857
< #define PCRF_DZ_LTR_NXT_PTR_LBN 20
< #define PCRF_DZ_LTR_NXT_PTR_WIDTH 12
< #define PCRF_DZ_LTR_VERSION_LBN 16
< #define PCRF_DZ_LTR_VERSION_WIDTH 4
< #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0
< #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16
---
> #define PCRF_DZ_SEC_NXT_PTR_LBN 20
> #define PCRF_DZ_SEC_NXT_PTR_WIDTH 12
> #define PCRF_DZ_SEC_VERSION_LBN 16
> #define PCRF_DZ_SEC_VERSION_WIDTH 4
> #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0
> #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16
1801a1859
>
1803,1804c1861,1862
< * PC_LTR_MAX_SNOOP_REG(32bit):
< * LTR Maximum Snoop/No Snoop Register
---
> * PC_LINK_CONTROL3_REG(32bit):
> * Link Control 3.
1807c1865
< #define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294
---
> #define PCR_DZ_LINK_CONTROL3_REG 0x00000304
1810,1817c1868,1871
< #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26
< #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3
< #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16
< #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10
< #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10
< #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3
< #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0
< #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10
---
> #define PCRF_DZ_LINK_EQ_INT_EN_LBN 1
> #define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1
> #define PCRF_DZ_PERFORM_EQL_LBN 0
> #define PCRF_DZ_PERFORM_EQL_WIDTH 1
1818a1873
>
1819a1875,1942
> * PC_LANE_ERROR_STAT_REG(32bit):
> * Lane Error Status Register.
> */
>
> #define PCR_DZ_LANE_ERROR_STAT_REG 0x00000308
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LANE_STATUS_LBN 0
> #define PCRF_DZ_LANE_STATUS_WIDTH 8
>
>
> /*
> * PC_LANE01_EQU_CONTROL_REG(32bit):
> * Lanes 0,1 Equalization Control Register.
> */
>
> #define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000030c
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LANE1_EQ_CTRL_LBN 16
> #define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16
> #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0
> #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16
>
>
> /*
> * PC_LANE23_EQU_CONTROL_REG(32bit):
> * Lanes 2,3 Equalization Control Register.
> */
>
> #define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000310
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LANE3_EQ_CTRL_LBN 16
> #define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16
> #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0
> #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16
>
>
> /*
> * PC_LANE45_EQU_CONTROL_REG(32bit):
> * Lanes 4,5 Equalization Control Register.
> */
>
> #define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000314
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LANE5_EQ_CTRL_LBN 16
> #define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16
> #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0
> #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16
>
>
> /*
> * PC_LANE67_EQU_CONTROL_REG(32bit):
> * Lanes 6,7 Equalization Control Register.
> */
>
> #define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000318
> /* hunta0=pci_f0_config */
>
> #define PCRF_DZ_LANE7_EQ_CTRL_LBN 16
> #define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16
> #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0
> #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16
>
>
> /*
1831a1955
>
1848a1973
>
1863a1989
>
1886a2013
>
1923a2051
>
1946a2075
>
1973a2103
>
1992a2123
>
2008,2011d2138
< /*
< * PC_FLT_MSK_REG(32bit):
< * Filter Mask Register 2
< */
2013,2018d2139
< #define PCR_CC_FLT_MSK_REG 0x00000720
< /* sienaa0=pci_f0_config */
<
< #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0
< #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32
<
2038a2160
>
2039a2162,2173
> * PC_FLT_MSK_REG(32bit):
> * Filter Mask Register 2
> */
>
> #define PCR_CC_FLT_MSK_REG 0x00000720
> /* sienaa0=pci_f0_config */
>
> #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0
> #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32
>
>
> /*
2066a2201
>
2085a2221
>
2104a2241
>
2117a2255
>
2130a2269
>
2143a2283
>
2158a2299
>
2166a2308,2309
>
>
2174a2318,2319
>
>
2182a2328,2329
>
>
2190a2338,2339
>
>
2198a2348,2349
>
>
2219a2371
>