| efx_regs_pci.h (95ee2897) | efx_regs_pci.h (e948693e) |
|---|---|
| 1/*- | 1/*- |
| 2 * SPDX-License-Identifier: BSD-2-Clause | 2 * Copyright 2007-2010 Solarflare Communications Inc. All rights reserved. |
| 3 * | 3 * |
| 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * | |
| 7 * Redistribution and use in source and binary forms, with or without | 4 * Redistribution and use in source and binary forms, with or without |
| 8 * modification, are permitted provided that the following conditions are met: | 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. |
| 9 * | 12 * |
| 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. | 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. |
| 31 */ 32 33#ifndef _SYS_EFX_REGS_PCI_H 34#define _SYS_EFX_REGS_PCI_H 35 36#ifdef __cplusplus 37extern "C" { 38#endif --- 4 unchanged lines hidden (view full) --- 43 */ 44 45#define PCR_AZ_VEND_ID_REG 0x00000000 46/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 47 48#define PCRF_AZ_VEND_ID_LBN 0 49#define PCRF_AZ_VEND_ID_WIDTH 16 50 | 24 */ 25 26#ifndef _SYS_EFX_REGS_PCI_H 27#define _SYS_EFX_REGS_PCI_H 28 29#ifdef __cplusplus 30extern "C" { 31#endif --- 4 unchanged lines hidden (view full) --- 36 */ 37 38#define PCR_AZ_VEND_ID_REG 0x00000000 39/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 40 41#define PCRF_AZ_VEND_ID_LBN 0 42#define PCRF_AZ_VEND_ID_WIDTH 16 43 |
| 44 |
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| 51/* 52 * PC_DEV_ID_REG(16bit): 53 * Device ID register 54 */ 55 56#define PCR_AZ_DEV_ID_REG 0x00000002 57/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 58 59#define PCRF_AZ_DEV_ID_LBN 0 60#define PCRF_AZ_DEV_ID_WIDTH 16 61 | 45/* 46 * PC_DEV_ID_REG(16bit): 47 * Device ID register 48 */ 49 50#define PCR_AZ_DEV_ID_REG 0x00000002 51/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 52 53#define PCRF_AZ_DEV_ID_LBN 0 54#define PCRF_AZ_DEV_ID_WIDTH 16 55 |
| 56 |
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| 62/* 63 * PC_CMD_REG(16bit): 64 * Command register 65 */ 66 67#define PCR_AZ_CMD_REG 0x00000004 68/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 69 --- 15 unchanged lines hidden (view full) --- 85#define PCRF_AZ_SPEC_CYC_WIDTH 1 86#define PCRF_AZ_MST_EN_LBN 2 87#define PCRF_AZ_MST_EN_WIDTH 1 88#define PCRF_AZ_MEM_EN_LBN 1 89#define PCRF_AZ_MEM_EN_WIDTH 1 90#define PCRF_AZ_IO_EN_LBN 0 91#define PCRF_AZ_IO_EN_WIDTH 1 92 | 57/* 58 * PC_CMD_REG(16bit): 59 * Command register 60 */ 61 62#define PCR_AZ_CMD_REG 0x00000004 63/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 64 --- 15 unchanged lines hidden (view full) --- 80#define PCRF_AZ_SPEC_CYC_WIDTH 1 81#define PCRF_AZ_MST_EN_LBN 2 82#define PCRF_AZ_MST_EN_WIDTH 1 83#define PCRF_AZ_MEM_EN_LBN 1 84#define PCRF_AZ_MEM_EN_WIDTH 1 85#define PCRF_AZ_IO_EN_LBN 0 86#define PCRF_AZ_IO_EN_WIDTH 1 87 |
| 88 |
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| 93/* 94 * PC_STAT_REG(16bit): 95 * Status register 96 */ 97 98#define PCR_AZ_STAT_REG 0x00000006 99/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 100 --- 15 unchanged lines hidden (view full) --- 116#define PCRF_AZ_FB2B_CAP_WIDTH 1 117#define PCRF_AZ_66MHZ_CAP_LBN 5 118#define PCRF_AZ_66MHZ_CAP_WIDTH 1 119#define PCRF_AZ_CAP_LIST_LBN 4 120#define PCRF_AZ_CAP_LIST_WIDTH 1 121#define PCRF_AZ_INTX_STAT_LBN 3 122#define PCRF_AZ_INTX_STAT_WIDTH 1 123 | 89/* 90 * PC_STAT_REG(16bit): 91 * Status register 92 */ 93 94#define PCR_AZ_STAT_REG 0x00000006 95/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 96 --- 15 unchanged lines hidden (view full) --- 112#define PCRF_AZ_FB2B_CAP_WIDTH 1 113#define PCRF_AZ_66MHZ_CAP_LBN 5 114#define PCRF_AZ_66MHZ_CAP_WIDTH 1 115#define PCRF_AZ_CAP_LIST_LBN 4 116#define PCRF_AZ_CAP_LIST_WIDTH 1 117#define PCRF_AZ_INTX_STAT_LBN 3 118#define PCRF_AZ_INTX_STAT_WIDTH 1 119 |
| 120 |
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| 124/* 125 * PC_REV_ID_REG(8bit): 126 * Class code & revision ID register 127 */ 128 129#define PCR_AZ_REV_ID_REG 0x00000008 130/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 131 132#define PCRF_AZ_REV_ID_LBN 0 133#define PCRF_AZ_REV_ID_WIDTH 8 134 | 121/* 122 * PC_REV_ID_REG(8bit): 123 * Class code & revision ID register 124 */ 125 126#define PCR_AZ_REV_ID_REG 0x00000008 127/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 128 129#define PCRF_AZ_REV_ID_LBN 0 130#define PCRF_AZ_REV_ID_WIDTH 8 131 |
| 132 |
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| 135/* 136 * PC_CC_REG(24bit): 137 * Class code register 138 */ 139 140#define PCR_AZ_CC_REG 0x00000009 141/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 142 143#define PCRF_AZ_BASE_CC_LBN 16 144#define PCRF_AZ_BASE_CC_WIDTH 8 145#define PCRF_AZ_SUB_CC_LBN 8 146#define PCRF_AZ_SUB_CC_WIDTH 8 147#define PCRF_AZ_PROG_IF_LBN 0 148#define PCRF_AZ_PROG_IF_WIDTH 8 149 | 133/* 134 * PC_CC_REG(24bit): 135 * Class code register 136 */ 137 138#define PCR_AZ_CC_REG 0x00000009 139/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 140 141#define PCRF_AZ_BASE_CC_LBN 16 142#define PCRF_AZ_BASE_CC_WIDTH 8 143#define PCRF_AZ_SUB_CC_LBN 8 144#define PCRF_AZ_SUB_CC_WIDTH 8 145#define PCRF_AZ_PROG_IF_LBN 0 146#define PCRF_AZ_PROG_IF_WIDTH 8 147 |
| 148 |
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| 150/* 151 * PC_CACHE_LSIZE_REG(8bit): 152 * Cache line size 153 */ 154 155#define PCR_AZ_CACHE_LSIZE_REG 0x0000000c 156/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 157 158#define PCRF_AZ_CACHE_LSIZE_LBN 0 159#define PCRF_AZ_CACHE_LSIZE_WIDTH 8 160 | 149/* 150 * PC_CACHE_LSIZE_REG(8bit): 151 * Cache line size 152 */ 153 154#define PCR_AZ_CACHE_LSIZE_REG 0x0000000c 155/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 156 157#define PCRF_AZ_CACHE_LSIZE_LBN 0 158#define PCRF_AZ_CACHE_LSIZE_WIDTH 8 159 |
| 160 |
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| 161/* 162 * PC_MST_LAT_REG(8bit): 163 * Master latency timer register 164 */ 165 166#define PCR_AZ_MST_LAT_REG 0x0000000d 167/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 168 169#define PCRF_AZ_MST_LAT_LBN 0 170#define PCRF_AZ_MST_LAT_WIDTH 8 171 | 161/* 162 * PC_MST_LAT_REG(8bit): 163 * Master latency timer register 164 */ 165 166#define PCR_AZ_MST_LAT_REG 0x0000000d 167/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 168 169#define PCRF_AZ_MST_LAT_LBN 0 170#define PCRF_AZ_MST_LAT_WIDTH 8 171 |
| 172 |
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| 172/* 173 * PC_HDR_TYPE_REG(8bit): 174 * Header type register 175 */ 176 177#define PCR_AZ_HDR_TYPE_REG 0x0000000e 178/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 179 180#define PCRF_AZ_MULT_FUNC_LBN 7 181#define PCRF_AZ_MULT_FUNC_WIDTH 1 182#define PCRF_AZ_TYPE_LBN 0 183#define PCRF_AZ_TYPE_WIDTH 7 184 | 173/* 174 * PC_HDR_TYPE_REG(8bit): 175 * Header type register 176 */ 177 178#define PCR_AZ_HDR_TYPE_REG 0x0000000e 179/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 180 181#define PCRF_AZ_MULT_FUNC_LBN 7 182#define PCRF_AZ_MULT_FUNC_WIDTH 1 183#define PCRF_AZ_TYPE_LBN 0 184#define PCRF_AZ_TYPE_WIDTH 7 185 |
| 186 |
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| 185/* 186 * PC_BIST_REG(8bit): 187 * BIST register 188 */ 189 190#define PCR_AZ_BIST_REG 0x0000000f 191/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 192 193#define PCRF_AZ_BIST_LBN 0 194#define PCRF_AZ_BIST_WIDTH 8 195 | 187/* 188 * PC_BIST_REG(8bit): 189 * BIST register 190 */ 191 192#define PCR_AZ_BIST_REG 0x0000000f 193/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 194 195#define PCRF_AZ_BIST_LBN 0 196#define PCRF_AZ_BIST_WIDTH 8 197 |
| 198 |
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| 196/* 197 * PC_BAR0_REG(32bit): 198 * Primary function base address register 0 199 */ 200 201#define PCR_AZ_BAR0_REG 0x00000010 202/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 203 204#define PCRF_AZ_BAR0_LBN 4 205#define PCRF_AZ_BAR0_WIDTH 28 206#define PCRF_AZ_BAR0_PREF_LBN 3 207#define PCRF_AZ_BAR0_PREF_WIDTH 1 208#define PCRF_AZ_BAR0_TYPE_LBN 1 209#define PCRF_AZ_BAR0_TYPE_WIDTH 2 210#define PCRF_AZ_BAR0_IOM_LBN 0 211#define PCRF_AZ_BAR0_IOM_WIDTH 1 212 | 199/* 200 * PC_BAR0_REG(32bit): 201 * Primary function base address register 0 202 */ 203 204#define PCR_AZ_BAR0_REG 0x00000010 205/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 206 207#define PCRF_AZ_BAR0_LBN 4 208#define PCRF_AZ_BAR0_WIDTH 28 209#define PCRF_AZ_BAR0_PREF_LBN 3 210#define PCRF_AZ_BAR0_PREF_WIDTH 1 211#define PCRF_AZ_BAR0_TYPE_LBN 1 212#define PCRF_AZ_BAR0_TYPE_WIDTH 2 213#define PCRF_AZ_BAR0_IOM_LBN 0 214#define PCRF_AZ_BAR0_IOM_WIDTH 1 215 |
| 216 |
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| 213/* 214 * PC_BAR1_REG(32bit): 215 * Primary function base address register 1, BAR1 is not implemented so read only. 216 */ 217 218#define PCR_DZ_BAR1_REG 0x00000014 219/* hunta0=pci_f0_config */ 220 221#define PCRF_DZ_BAR1_LBN 0 222#define PCRF_DZ_BAR1_WIDTH 32 223 | 217/* 218 * PC_BAR1_REG(32bit): 219 * Primary function base address register 1, BAR1 is not implemented so read only. 220 */ 221 222#define PCR_DZ_BAR1_REG 0x00000014 223/* hunta0=pci_f0_config */ 224 225#define PCRF_DZ_BAR1_LBN 0 226#define PCRF_DZ_BAR1_WIDTH 32 227 |
| 228 |
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| 224/* 225 * PC_BAR2_LO_REG(32bit): 226 * Primary function base address register 2 low bits 227 */ 228 229#define PCR_AZ_BAR2_LO_REG 0x00000018 230/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 231 232#define PCRF_AZ_BAR2_LO_LBN 4 233#define PCRF_AZ_BAR2_LO_WIDTH 28 234#define PCRF_AZ_BAR2_PREF_LBN 3 235#define PCRF_AZ_BAR2_PREF_WIDTH 1 236#define PCRF_AZ_BAR2_TYPE_LBN 1 237#define PCRF_AZ_BAR2_TYPE_WIDTH 2 238#define PCRF_AZ_BAR2_IOM_LBN 0 239#define PCRF_AZ_BAR2_IOM_WIDTH 1 240 | 229/* 230 * PC_BAR2_LO_REG(32bit): 231 * Primary function base address register 2 low bits 232 */ 233 234#define PCR_AZ_BAR2_LO_REG 0x00000018 235/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 236 237#define PCRF_AZ_BAR2_LO_LBN 4 238#define PCRF_AZ_BAR2_LO_WIDTH 28 239#define PCRF_AZ_BAR2_PREF_LBN 3 240#define PCRF_AZ_BAR2_PREF_WIDTH 1 241#define PCRF_AZ_BAR2_TYPE_LBN 1 242#define PCRF_AZ_BAR2_TYPE_WIDTH 2 243#define PCRF_AZ_BAR2_IOM_LBN 0 244#define PCRF_AZ_BAR2_IOM_WIDTH 1 245 |
| 246 |
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| 241/* 242 * PC_BAR2_HI_REG(32bit): 243 * Primary function base address register 2 high bits 244 */ 245 246#define PCR_AZ_BAR2_HI_REG 0x0000001c 247/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 248 249#define PCRF_AZ_BAR2_HI_LBN 0 250#define PCRF_AZ_BAR2_HI_WIDTH 32 251 | 247/* 248 * PC_BAR2_HI_REG(32bit): 249 * Primary function base address register 2 high bits 250 */ 251 252#define PCR_AZ_BAR2_HI_REG 0x0000001c 253/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 254 255#define PCRF_AZ_BAR2_HI_LBN 0 256#define PCRF_AZ_BAR2_HI_WIDTH 32 257 |
| 258 |
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| 252/* 253 * PC_BAR4_LO_REG(32bit): 254 * Primary function base address register 2 low bits 255 */ 256 257#define PCR_CZ_BAR4_LO_REG 0x00000020 258/* sienaa0,hunta0=pci_f0_config */ 259 260#define PCRF_CZ_BAR4_LO_LBN 4 261#define PCRF_CZ_BAR4_LO_WIDTH 28 262#define PCRF_CZ_BAR4_PREF_LBN 3 263#define PCRF_CZ_BAR4_PREF_WIDTH 1 264#define PCRF_CZ_BAR4_TYPE_LBN 1 265#define PCRF_CZ_BAR4_TYPE_WIDTH 2 266#define PCRF_CZ_BAR4_IOM_LBN 0 267#define PCRF_CZ_BAR4_IOM_WIDTH 1 268 | 259/* 260 * PC_BAR4_LO_REG(32bit): 261 * Primary function base address register 2 low bits 262 */ 263 264#define PCR_CZ_BAR4_LO_REG 0x00000020 265/* sienaa0,hunta0=pci_f0_config */ 266 267#define PCRF_CZ_BAR4_LO_LBN 4 268#define PCRF_CZ_BAR4_LO_WIDTH 28 269#define PCRF_CZ_BAR4_PREF_LBN 3 270#define PCRF_CZ_BAR4_PREF_WIDTH 1 271#define PCRF_CZ_BAR4_TYPE_LBN 1 272#define PCRF_CZ_BAR4_TYPE_WIDTH 2 273#define PCRF_CZ_BAR4_IOM_LBN 0 274#define PCRF_CZ_BAR4_IOM_WIDTH 1 275 |
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| 269/* 270 * PC_BAR4_HI_REG(32bit): 271 * Primary function base address register 2 high bits 272 */ 273 274#define PCR_CZ_BAR4_HI_REG 0x00000024 275/* sienaa0,hunta0=pci_f0_config */ 276 277#define PCRF_CZ_BAR4_HI_LBN 0 278#define PCRF_CZ_BAR4_HI_WIDTH 32 279 | 277/* 278 * PC_BAR4_HI_REG(32bit): 279 * Primary function base address register 2 high bits 280 */ 281 282#define PCR_CZ_BAR4_HI_REG 0x00000024 283/* sienaa0,hunta0=pci_f0_config */ 284 285#define PCRF_CZ_BAR4_HI_LBN 0 286#define PCRF_CZ_BAR4_HI_WIDTH 32 287 |
| 288 |
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| 280/* 281 * PC_SS_VEND_ID_REG(16bit): 282 * Sub-system vendor ID register 283 */ 284 285#define PCR_AZ_SS_VEND_ID_REG 0x0000002c 286/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 287 288#define PCRF_AZ_SS_VEND_ID_LBN 0 289#define PCRF_AZ_SS_VEND_ID_WIDTH 16 290 | 289/* 290 * PC_SS_VEND_ID_REG(16bit): 291 * Sub-system vendor ID register 292 */ 293 294#define PCR_AZ_SS_VEND_ID_REG 0x0000002c 295/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 296 297#define PCRF_AZ_SS_VEND_ID_LBN 0 298#define PCRF_AZ_SS_VEND_ID_WIDTH 16 299 |
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| 291/* 292 * PC_SS_ID_REG(16bit): 293 * Sub-system ID register 294 */ 295 296#define PCR_AZ_SS_ID_REG 0x0000002e 297/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 298 299#define PCRF_AZ_SS_ID_LBN 0 300#define PCRF_AZ_SS_ID_WIDTH 16 301 | 301/* 302 * PC_SS_ID_REG(16bit): 303 * Sub-system ID register 304 */ 305 306#define PCR_AZ_SS_ID_REG 0x0000002e 307/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 308 309#define PCRF_AZ_SS_ID_LBN 0 310#define PCRF_AZ_SS_ID_WIDTH 16 311 |
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| 302/* 303 * PC_EXPROM_BAR_REG(32bit): 304 * Expansion ROM base address register 305 */ 306 307#define PCR_AZ_EXPROM_BAR_REG 0x00000030 308/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 309 310#define PCRF_AZ_EXPROM_BAR_LBN 11 311#define PCRF_AZ_EXPROM_BAR_WIDTH 21 312#define PCRF_AB_EXPROM_MIN_SIZE_LBN 2 313#define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9 314#define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1 315#define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10 316#define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1 317#define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1 318#define PCRF_AZ_EXPROM_EN_LBN 0 319#define PCRF_AZ_EXPROM_EN_WIDTH 1 320 | 313/* 314 * PC_EXPROM_BAR_REG(32bit): 315 * Expansion ROM base address register 316 */ 317 318#define PCR_AZ_EXPROM_BAR_REG 0x00000030 319/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 320 321#define PCRF_AZ_EXPROM_BAR_LBN 11 322#define PCRF_AZ_EXPROM_BAR_WIDTH 21 323#define PCRF_AB_EXPROM_MIN_SIZE_LBN 2 324#define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9 325#define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1 326#define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10 327#define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1 328#define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1 329#define PCRF_AZ_EXPROM_EN_LBN 0 330#define PCRF_AZ_EXPROM_EN_WIDTH 1 331 |
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| 321/* 322 * PC_CAP_PTR_REG(8bit): 323 * Capability pointer register 324 */ 325 326#define PCR_AZ_CAP_PTR_REG 0x00000034 327/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 328 329#define PCRF_AZ_CAP_PTR_LBN 0 330#define PCRF_AZ_CAP_PTR_WIDTH 8 331 | 333/* 334 * PC_CAP_PTR_REG(8bit): 335 * Capability pointer register 336 */ 337 338#define PCR_AZ_CAP_PTR_REG 0x00000034 339/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 340 341#define PCRF_AZ_CAP_PTR_LBN 0 342#define PCRF_AZ_CAP_PTR_WIDTH 8 343 |
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| 332/* 333 * PC_INT_LINE_REG(8bit): 334 * Interrupt line register 335 */ 336 337#define PCR_AZ_INT_LINE_REG 0x0000003c 338/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 339 340#define PCRF_AZ_INT_LINE_LBN 0 341#define PCRF_AZ_INT_LINE_WIDTH 8 342 | 345/* 346 * PC_INT_LINE_REG(8bit): 347 * Interrupt line register 348 */ 349 350#define PCR_AZ_INT_LINE_REG 0x0000003c 351/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 352 353#define PCRF_AZ_INT_LINE_LBN 0 354#define PCRF_AZ_INT_LINE_WIDTH 8 355 |
| 356 |
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| 343/* 344 * PC_INT_PIN_REG(8bit): 345 * Interrupt pin register 346 */ 347 348#define PCR_AZ_INT_PIN_REG 0x0000003d 349/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 350 351#define PCRF_AZ_INT_PIN_LBN 0 352#define PCRF_AZ_INT_PIN_WIDTH 8 | 357/* 358 * PC_INT_PIN_REG(8bit): 359 * Interrupt pin register 360 */ 361 362#define PCR_AZ_INT_PIN_REG 0x0000003d 363/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 364 365#define PCRF_AZ_INT_PIN_LBN 0 366#define PCRF_AZ_INT_PIN_WIDTH 8 |
| 353#define PCFE_DZ_INTPIN_INTD 4 354#define PCFE_DZ_INTPIN_INTC 3 355#define PCFE_DZ_INTPIN_INTB 2 356#define PCFE_DZ_INTPIN_INTA 1 | |
| 357 | 367 |
| 368 |
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| 358/* 359 * PC_PM_CAP_ID_REG(8bit): 360 * Power management capability ID 361 */ 362 | 369/* 370 * PC_PM_CAP_ID_REG(8bit): 371 * Power management capability ID 372 */ 373 |
| 363#define PCR_AZ_PM_CAP_ID_REG 0x00000040 364/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ | 374#define PCR_AC_PM_CAP_ID_REG 0x00000040 375/* falcona0,falconb0,sienaa0=pci_f0_config */ |
| 365 | 376 |
| 377#define PCR_DZ_PM_CAP_ID_REG 0x00000080 378/* hunta0=pci_f0_config */ 379 |
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| 366#define PCRF_AZ_PM_CAP_ID_LBN 0 367#define PCRF_AZ_PM_CAP_ID_WIDTH 8 368 | 380#define PCRF_AZ_PM_CAP_ID_LBN 0 381#define PCRF_AZ_PM_CAP_ID_WIDTH 8 382 |
| 383 |
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| 369/* 370 * PC_PM_NXT_PTR_REG(8bit): 371 * Power management next item pointer 372 */ 373 | 384/* 385 * PC_PM_NXT_PTR_REG(8bit): 386 * Power management next item pointer 387 */ 388 |
| 374#define PCR_AZ_PM_NXT_PTR_REG 0x00000041 375/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ | 389#define PCR_AC_PM_NXT_PTR_REG 0x00000041 390/* falcona0,falconb0,sienaa0=pci_f0_config */ |
| 376 | 391 |
| 392#define PCR_DZ_PM_NXT_PTR_REG 0x00000081 393/* hunta0=pci_f0_config */ 394 |
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| 377#define PCRF_AZ_PM_NXT_PTR_LBN 0 378#define PCRF_AZ_PM_NXT_PTR_WIDTH 8 379 | 395#define PCRF_AZ_PM_NXT_PTR_LBN 0 396#define PCRF_AZ_PM_NXT_PTR_WIDTH 8 397 |
| 398 |
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| 380/* 381 * PC_PM_CAP_REG(16bit): 382 * Power management capabilities register 383 */ 384 | 399/* 400 * PC_PM_CAP_REG(16bit): 401 * Power management capabilities register 402 */ 403 |
| 385#define PCR_AZ_PM_CAP_REG 0x00000042 386/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ | 404#define PCR_AC_PM_CAP_REG 0x00000042 405/* falcona0,falconb0,sienaa0=pci_f0_config */ |
| 387 | 406 |
| 407#define PCR_DZ_PM_CAP_REG 0x00000082 408/* hunta0=pci_f0_config */ 409 |
|
| 388#define PCRF_AZ_PM_PME_SUPT_LBN 11 389#define PCRF_AZ_PM_PME_SUPT_WIDTH 5 390#define PCRF_AZ_PM_D2_SUPT_LBN 10 391#define PCRF_AZ_PM_D2_SUPT_WIDTH 1 392#define PCRF_AZ_PM_D1_SUPT_LBN 9 393#define PCRF_AZ_PM_D1_SUPT_WIDTH 1 394#define PCRF_AZ_PM_AUX_CURR_LBN 6 395#define PCRF_AZ_PM_AUX_CURR_WIDTH 3 396#define PCRF_AZ_PM_DSI_LBN 5 397#define PCRF_AZ_PM_DSI_WIDTH 1 398#define PCRF_AZ_PM_PME_CLK_LBN 3 399#define PCRF_AZ_PM_PME_CLK_WIDTH 1 400#define PCRF_AZ_PM_PME_VER_LBN 0 401#define PCRF_AZ_PM_PME_VER_WIDTH 3 402 | 410#define PCRF_AZ_PM_PME_SUPT_LBN 11 411#define PCRF_AZ_PM_PME_SUPT_WIDTH 5 412#define PCRF_AZ_PM_D2_SUPT_LBN 10 413#define PCRF_AZ_PM_D2_SUPT_WIDTH 1 414#define PCRF_AZ_PM_D1_SUPT_LBN 9 415#define PCRF_AZ_PM_D1_SUPT_WIDTH 1 416#define PCRF_AZ_PM_AUX_CURR_LBN 6 417#define PCRF_AZ_PM_AUX_CURR_WIDTH 3 418#define PCRF_AZ_PM_DSI_LBN 5 419#define PCRF_AZ_PM_DSI_WIDTH 1 420#define PCRF_AZ_PM_PME_CLK_LBN 3 421#define PCRF_AZ_PM_PME_CLK_WIDTH 1 422#define PCRF_AZ_PM_PME_VER_LBN 0 423#define PCRF_AZ_PM_PME_VER_WIDTH 3 424 |
| 425 |
|
| 403/* 404 * PC_PM_CS_REG(16bit): 405 * Power management control & status register 406 */ 407 | 426/* 427 * PC_PM_CS_REG(16bit): 428 * Power management control & status register 429 */ 430 |
| 408#define PCR_AZ_PM_CS_REG 0x00000044 409/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ | 431#define PCR_AC_PM_CS_REG 0x00000044 432/* falcona0,falconb0,sienaa0=pci_f0_config */ |
| 410 | 433 |
| 434#define PCR_DZ_PM_CS_REG 0x00000084 435/* hunta0=pci_f0_config */ 436 |
|
| 411#define PCRF_AZ_PM_PME_STAT_LBN 15 412#define PCRF_AZ_PM_PME_STAT_WIDTH 1 413#define PCRF_AZ_PM_DAT_SCALE_LBN 13 414#define PCRF_AZ_PM_DAT_SCALE_WIDTH 2 415#define PCRF_AZ_PM_DAT_SEL_LBN 9 416#define PCRF_AZ_PM_DAT_SEL_WIDTH 4 417#define PCRF_AZ_PM_PME_EN_LBN 8 418#define PCRF_AZ_PM_PME_EN_WIDTH 1 419#define PCRF_CZ_NO_SOFT_RESET_LBN 3 420#define PCRF_CZ_NO_SOFT_RESET_WIDTH 1 421#define PCRF_AZ_PM_PWR_ST_LBN 0 422#define PCRF_AZ_PM_PWR_ST_WIDTH 2 423 | 437#define PCRF_AZ_PM_PME_STAT_LBN 15 438#define PCRF_AZ_PM_PME_STAT_WIDTH 1 439#define PCRF_AZ_PM_DAT_SCALE_LBN 13 440#define PCRF_AZ_PM_DAT_SCALE_WIDTH 2 441#define PCRF_AZ_PM_DAT_SEL_LBN 9 442#define PCRF_AZ_PM_DAT_SEL_WIDTH 4 443#define PCRF_AZ_PM_PME_EN_LBN 8 444#define PCRF_AZ_PM_PME_EN_WIDTH 1 445#define PCRF_CZ_NO_SOFT_RESET_LBN 3 446#define PCRF_CZ_NO_SOFT_RESET_WIDTH 1 447#define PCRF_AZ_PM_PWR_ST_LBN 0 448#define PCRF_AZ_PM_PWR_ST_WIDTH 2 449 |
| 450 |
|
| 424/* 425 * PC_MSI_CAP_ID_REG(8bit): 426 * MSI capability ID 427 */ 428 | 451/* 452 * PC_MSI_CAP_ID_REG(8bit): 453 * MSI capability ID 454 */ 455 |
| 429#define PCR_AZ_MSI_CAP_ID_REG 0x00000050 430/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ | 456#define PCR_AC_MSI_CAP_ID_REG 0x00000050 457/* falcona0,falconb0,sienaa0=pci_f0_config */ |
| 431 | 458 |
| 459#define PCR_DZ_MSI_CAP_ID_REG 0x00000090 460/* hunta0=pci_f0_config */ 461 |
|
| 432#define PCRF_AZ_MSI_CAP_ID_LBN 0 433#define PCRF_AZ_MSI_CAP_ID_WIDTH 8 434 | 462#define PCRF_AZ_MSI_CAP_ID_LBN 0 463#define PCRF_AZ_MSI_CAP_ID_WIDTH 8 464 |
| 465 |
|
| 435/* 436 * PC_MSI_NXT_PTR_REG(8bit): 437 * MSI next item pointer 438 */ 439 | 466/* 467 * PC_MSI_NXT_PTR_REG(8bit): 468 * MSI next item pointer 469 */ 470 |
| 440#define PCR_AZ_MSI_NXT_PTR_REG 0x00000051 441/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ | 471#define PCR_AC_MSI_NXT_PTR_REG 0x00000051 472/* falcona0,falconb0,sienaa0=pci_f0_config */ |
| 442 | 473 |
| 474#define PCR_DZ_MSI_NXT_PTR_REG 0x00000091 475/* hunta0=pci_f0_config */ 476 |
|
| 443#define PCRF_AZ_MSI_NXT_PTR_LBN 0 444#define PCRF_AZ_MSI_NXT_PTR_WIDTH 8 445 | 477#define PCRF_AZ_MSI_NXT_PTR_LBN 0 478#define PCRF_AZ_MSI_NXT_PTR_WIDTH 8 479 |
| 480 |
|
| 446/* 447 * PC_MSI_CTL_REG(16bit): 448 * MSI control register 449 */ 450 | 481/* 482 * PC_MSI_CTL_REG(16bit): 483 * MSI control register 484 */ 485 |
| 451#define PCR_AZ_MSI_CTL_REG 0x00000052 452/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ | 486#define PCR_AC_MSI_CTL_REG 0x00000052 487/* falcona0,falconb0,sienaa0=pci_f0_config */ |
| 453 | 488 |
| 489#define PCR_DZ_MSI_CTL_REG 0x00000092 490/* hunta0=pci_f0_config */ 491 |
|
| 454#define PCRF_AZ_MSI_64_EN_LBN 7 455#define PCRF_AZ_MSI_64_EN_WIDTH 1 456#define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4 457#define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3 458#define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1 459#define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3 460#define PCRF_AZ_MSI_EN_LBN 0 461#define PCRF_AZ_MSI_EN_WIDTH 1 462 | 492#define PCRF_AZ_MSI_64_EN_LBN 7 493#define PCRF_AZ_MSI_64_EN_WIDTH 1 494#define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4 495#define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3 496#define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1 497#define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3 498#define PCRF_AZ_MSI_EN_LBN 0 499#define PCRF_AZ_MSI_EN_WIDTH 1 500 |
| 501 |
|
| 463/* 464 * PC_MSI_ADR_LO_REG(32bit): 465 * MSI low 32 bits address register 466 */ 467 | 502/* 503 * PC_MSI_ADR_LO_REG(32bit): 504 * MSI low 32 bits address register 505 */ 506 |
| 468#define PCR_AZ_MSI_ADR_LO_REG 0x00000054 469/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ | 507#define PCR_AC_MSI_ADR_LO_REG 0x00000054 508/* falcona0,falconb0,sienaa0=pci_f0_config */ |
| 470 | 509 |
| 510#define PCR_DZ_MSI_ADR_LO_REG 0x00000094 511/* hunta0=pci_f0_config */ 512 |
|
| 471#define PCRF_AZ_MSI_ADR_LO_LBN 2 472#define PCRF_AZ_MSI_ADR_LO_WIDTH 30 473 | 513#define PCRF_AZ_MSI_ADR_LO_LBN 2 514#define PCRF_AZ_MSI_ADR_LO_WIDTH 30 515 |
| 516 |
|
| 474/* | 517/* |
| 518 * PC_VPD_CAP_CTL_REG(8bit): 519 * VPD control and capabilities register 520 */ 521 522#define PCR_DZ_VPD_CAP_CTL_REG 0x00000054 523/* hunta0=pci_f0_config */ 524 525#define PCR_CC_VPD_CAP_CTL_REG 0x000000d0 526/* sienaa0=pci_f0_config */ 527 528#define PCRF_CZ_VPD_FLAG_LBN 31 529#define PCRF_CZ_VPD_FLAG_WIDTH 1 530#define PCRF_CZ_VPD_ADDR_LBN 16 531#define PCRF_CZ_VPD_ADDR_WIDTH 15 532#define PCRF_CZ_VPD_NXT_PTR_LBN 8 533#define PCRF_CZ_VPD_NXT_PTR_WIDTH 8 534#define PCRF_CZ_VPD_CAP_ID_LBN 0 535#define PCRF_CZ_VPD_CAP_ID_WIDTH 8 536 537 538/* 539 * PC_VPD_CAP_DATA_REG(32bit): 540 * documentation to be written for sum_PC_VPD_CAP_DATA_REG 541 */ 542 543#define PCR_DZ_VPD_CAP_DATA_REG 0x00000058 544/* hunta0=pci_f0_config */ 545 546#define PCR_AB_VPD_CAP_DATA_REG 0x000000b4 547/* falcona0,falconb0=pci_f0_config */ 548 549#define PCR_CC_VPD_CAP_DATA_REG 0x000000d4 550/* sienaa0=pci_f0_config */ 551 552#define PCRF_AZ_VPD_DATA_LBN 0 553#define PCRF_AZ_VPD_DATA_WIDTH 32 554 555 556/* |
|
| 475 * PC_MSI_ADR_HI_REG(32bit): 476 * MSI high 32 bits address register 477 */ 478 | 557 * PC_MSI_ADR_HI_REG(32bit): 558 * MSI high 32 bits address register 559 */ 560 |
| 479#define PCR_AZ_MSI_ADR_HI_REG 0x00000058 480/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ | 561#define PCR_AC_MSI_ADR_HI_REG 0x00000058 562/* falcona0,falconb0,sienaa0=pci_f0_config */ |
| 481 | 563 |
| 564#define PCR_DZ_MSI_ADR_HI_REG 0x00000098 565/* hunta0=pci_f0_config */ 566 |
|
| 482#define PCRF_AZ_MSI_ADR_HI_LBN 0 483#define PCRF_AZ_MSI_ADR_HI_WIDTH 32 484 | 567#define PCRF_AZ_MSI_ADR_HI_LBN 0 568#define PCRF_AZ_MSI_ADR_HI_WIDTH 32 569 |
| 570 |
|
| 485/* 486 * PC_MSI_DAT_REG(16bit): 487 * MSI data register 488 */ 489 | 571/* 572 * PC_MSI_DAT_REG(16bit): 573 * MSI data register 574 */ 575 |
| 490#define PCR_AZ_MSI_DAT_REG 0x0000005c 491/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ | 576#define PCR_AC_MSI_DAT_REG 0x0000005c 577/* falcona0,falconb0,sienaa0=pci_f0_config */ |
| 492 | 578 |
| 579#define PCR_DZ_MSI_DAT_REG 0x0000009c 580/* hunta0=pci_f0_config */ 581 |
|
| 493#define PCRF_AZ_MSI_DAT_LBN 0 494#define PCRF_AZ_MSI_DAT_WIDTH 16 495 | 582#define PCRF_AZ_MSI_DAT_LBN 0 583#define PCRF_AZ_MSI_DAT_WIDTH 16 584 |
| 585 |
|
| 496/* 497 * PC_PCIE_CAP_LIST_REG(16bit): 498 * PCIe capability list register 499 */ 500 501#define PCR_AB_PCIE_CAP_LIST_REG 0x00000060 502/* falcona0,falconb0=pci_f0_config */ 503 | 586/* 587 * PC_PCIE_CAP_LIST_REG(16bit): 588 * PCIe capability list register 589 */ 590 591#define PCR_AB_PCIE_CAP_LIST_REG 0x00000060 592/* falcona0,falconb0=pci_f0_config */ 593 |
| 504#define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070 505/* sienaa0,hunta0=pci_f0_config */ | 594#define PCR_CC_PCIE_CAP_LIST_REG 0x00000070 595/* sienaa0=pci_f0_config */ |
| 506 | 596 |
| 597#define PCR_DZ_PCIE_CAP_LIST_REG 0x000000c0 598/* hunta0=pci_f0_config */ 599 |
|
| 507#define PCRF_AZ_PCIE_NXT_PTR_LBN 8 508#define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8 509#define PCRF_AZ_PCIE_CAP_ID_LBN 0 510#define PCRF_AZ_PCIE_CAP_ID_WIDTH 8 511 | 600#define PCRF_AZ_PCIE_NXT_PTR_LBN 8 601#define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8 602#define PCRF_AZ_PCIE_CAP_ID_LBN 0 603#define PCRF_AZ_PCIE_CAP_ID_WIDTH 8 604 |
| 605 |
|
| 512/* 513 * PC_PCIE_CAP_REG(16bit): 514 * PCIe capability register 515 */ 516 517#define PCR_AB_PCIE_CAP_REG 0x00000062 518/* falcona0,falconb0=pci_f0_config */ 519 | 606/* 607 * PC_PCIE_CAP_REG(16bit): 608 * PCIe capability register 609 */ 610 611#define PCR_AB_PCIE_CAP_REG 0x00000062 612/* falcona0,falconb0=pci_f0_config */ 613 |
| 520#define PCR_CZ_PCIE_CAP_REG 0x00000072 521/* sienaa0,hunta0=pci_f0_config */ | 614#define PCR_CC_PCIE_CAP_REG 0x00000072 615/* sienaa0=pci_f0_config */ |
| 522 | 616 |
| 617#define PCR_DZ_PCIE_CAP_REG 0x000000c2 618/* hunta0=pci_f0_config */ 619 |
|
| 523#define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9 524#define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5 525#define PCRF_AZ_PCIE_SLOT_IMP_LBN 8 526#define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1 527#define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4 528#define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4 529#define PCRF_AZ_PCIE_CAP_VER_LBN 0 530#define PCRF_AZ_PCIE_CAP_VER_WIDTH 4 531 | 620#define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9 621#define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5 622#define PCRF_AZ_PCIE_SLOT_IMP_LBN 8 623#define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1 624#define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4 625#define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4 626#define PCRF_AZ_PCIE_CAP_VER_LBN 0 627#define PCRF_AZ_PCIE_CAP_VER_WIDTH 4 628 |
| 629 |
|
| 532/* 533 * PC_DEV_CAP_REG(32bit): 534 * PCIe device capabilities register 535 */ 536 537#define PCR_AB_DEV_CAP_REG 0x00000064 538/* falcona0,falconb0=pci_f0_config */ 539 | 630/* 631 * PC_DEV_CAP_REG(32bit): 632 * PCIe device capabilities register 633 */ 634 635#define PCR_AB_DEV_CAP_REG 0x00000064 636/* falcona0,falconb0=pci_f0_config */ 637 |
| 540#define PCR_CZ_DEV_CAP_REG 0x00000074 541/* sienaa0=pci_f0_config,hunta0=pci_f0_config */ | 638#define PCR_CC_DEV_CAP_REG 0x00000074 639/* sienaa0=pci_f0_config */ |
| 542 | 640 |
| 641#define PCR_DZ_DEV_CAP_REG 0x000000c4 642/* hunta0=pci_f0_config */ 643 |
|
| 543#define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28 544#define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1 545#define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26 546#define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2 547#define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18 548#define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8 549#define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15 550#define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1 --- 9 unchanged lines hidden (view full) --- 560#define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3 561#define PCRF_AZ_TAG_FIELD_LBN 5 562#define PCRF_AZ_TAG_FIELD_WIDTH 1 563#define PCRF_AZ_PHAN_FUNC_LBN 3 564#define PCRF_AZ_PHAN_FUNC_WIDTH 2 565#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0 566#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3 567 | 644#define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28 645#define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1 646#define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26 647#define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2 648#define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18 649#define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8 650#define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15 651#define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1 --- 9 unchanged lines hidden (view full) --- 661#define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3 662#define PCRF_AZ_TAG_FIELD_LBN 5 663#define PCRF_AZ_TAG_FIELD_WIDTH 1 664#define PCRF_AZ_PHAN_FUNC_LBN 3 665#define PCRF_AZ_PHAN_FUNC_WIDTH 2 666#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0 667#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3 668 |
| 669 |
|
| 568/* 569 * PC_DEV_CTL_REG(16bit): 570 * PCIe device control register 571 */ 572 573#define PCR_AB_DEV_CTL_REG 0x00000068 574/* falcona0,falconb0=pci_f0_config */ 575 | 670/* 671 * PC_DEV_CTL_REG(16bit): 672 * PCIe device control register 673 */ 674 675#define PCR_AB_DEV_CTL_REG 0x00000068 676/* falcona0,falconb0=pci_f0_config */ 677 |
| 576#define PCR_CZ_DEV_CTL_REG 0x00000078 577/* sienaa0,hunta0=pci_f0_config */ | 678#define PCR_CC_DEV_CTL_REG 0x00000078 679/* sienaa0=pci_f0_config */ |
| 578 | 680 |
| 681#define PCR_DZ_DEV_CTL_REG 0x000000c8 682/* hunta0=pci_f0_config */ 683 |
|
| 579#define PCRF_CZ_FN_LEVEL_RESET_LBN 15 580#define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1 581#define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12 582#define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3 583#define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5 584#define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4 585#define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3 586#define PCFE_AZ_MAX_RD_REQ_SIZE_512 2 587#define PCFE_AZ_MAX_RD_REQ_SIZE_256 1 588#define PCFE_AZ_MAX_RD_REQ_SIZE_128 0 | 684#define PCRF_CZ_FN_LEVEL_RESET_LBN 15 685#define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1 686#define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12 687#define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3 688#define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5 689#define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4 690#define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3 691#define PCFE_AZ_MAX_RD_REQ_SIZE_512 2 692#define PCFE_AZ_MAX_RD_REQ_SIZE_256 1 693#define PCFE_AZ_MAX_RD_REQ_SIZE_128 0 |
| 694#define PCFE_DZ_OTHER other |
|
| 589#define PCRF_AZ_EN_NO_SNOOP_LBN 11 590#define PCRF_AZ_EN_NO_SNOOP_WIDTH 1 591#define PCRF_AZ_AUX_PWR_PM_EN_LBN 10 592#define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1 593#define PCRF_AZ_PHAN_FUNC_EN_LBN 9 594#define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1 595#define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8 596#define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1 597#define PCRF_CZ_EXTENDED_TAG_EN_LBN 8 598#define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1 599#define PCRF_AZ_MAX_PAYL_SIZE_LBN 5 600#define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3 601#define PCFE_AZ_MAX_PAYL_SIZE_4096 5 602#define PCFE_AZ_MAX_PAYL_SIZE_2048 4 603#define PCFE_AZ_MAX_PAYL_SIZE_1024 3 604#define PCFE_AZ_MAX_PAYL_SIZE_512 2 605#define PCFE_AZ_MAX_PAYL_SIZE_256 1 606#define PCFE_AZ_MAX_PAYL_SIZE_128 0 | 695#define PCRF_AZ_EN_NO_SNOOP_LBN 11 696#define PCRF_AZ_EN_NO_SNOOP_WIDTH 1 697#define PCRF_AZ_AUX_PWR_PM_EN_LBN 10 698#define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1 699#define PCRF_AZ_PHAN_FUNC_EN_LBN 9 700#define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1 701#define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8 702#define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1 703#define PCRF_CZ_EXTENDED_TAG_EN_LBN 8 704#define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1 705#define PCRF_AZ_MAX_PAYL_SIZE_LBN 5 706#define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3 707#define PCFE_AZ_MAX_PAYL_SIZE_4096 5 708#define PCFE_AZ_MAX_PAYL_SIZE_2048 4 709#define PCFE_AZ_MAX_PAYL_SIZE_1024 3 710#define PCFE_AZ_MAX_PAYL_SIZE_512 2 711#define PCFE_AZ_MAX_PAYL_SIZE_256 1 712#define PCFE_AZ_MAX_PAYL_SIZE_128 0 |
| 713#define PCFE_DZ_OTHER other |
|
| 607#define PCRF_AZ_EN_RELAX_ORDER_LBN 4 608#define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1 609#define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3 610#define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1 611#define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2 612#define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1 613#define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1 614#define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1 615#define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0 616#define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1 617 | 714#define PCRF_AZ_EN_RELAX_ORDER_LBN 4 715#define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1 716#define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3 717#define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1 718#define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2 719#define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1 720#define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1 721#define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1 722#define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0 723#define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1 724 |
| 725 |
|
| 618/* 619 * PC_DEV_STAT_REG(16bit): 620 * PCIe device status register 621 */ 622 623#define PCR_AB_DEV_STAT_REG 0x0000006a 624/* falcona0,falconb0=pci_f0_config */ 625 | 726/* 727 * PC_DEV_STAT_REG(16bit): 728 * PCIe device status register 729 */ 730 731#define PCR_AB_DEV_STAT_REG 0x0000006a 732/* falcona0,falconb0=pci_f0_config */ 733 |
| 626#define PCR_CZ_DEV_STAT_REG 0x0000007a 627/* sienaa0,hunta0=pci_f0_config */ | 734#define PCR_CC_DEV_STAT_REG 0x0000007a 735/* sienaa0=pci_f0_config */ |
| 628 | 736 |
| 737#define PCR_DZ_DEV_STAT_REG 0x000000ca 738/* hunta0=pci_f0_config */ 739 |
|
| 629#define PCRF_AZ_TRNS_PEND_LBN 5 630#define PCRF_AZ_TRNS_PEND_WIDTH 1 631#define PCRF_AZ_AUX_PWR_DET_LBN 4 632#define PCRF_AZ_AUX_PWR_DET_WIDTH 1 633#define PCRF_AZ_UNSUP_REQ_DET_LBN 3 634#define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1 635#define PCRF_AZ_FATAL_ERR_DET_LBN 2 636#define PCRF_AZ_FATAL_ERR_DET_WIDTH 1 637#define PCRF_AZ_NONFATAL_ERR_DET_LBN 1 638#define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1 639#define PCRF_AZ_CORR_ERR_DET_LBN 0 640#define PCRF_AZ_CORR_ERR_DET_WIDTH 1 641 | 740#define PCRF_AZ_TRNS_PEND_LBN 5 741#define PCRF_AZ_TRNS_PEND_WIDTH 1 742#define PCRF_AZ_AUX_PWR_DET_LBN 4 743#define PCRF_AZ_AUX_PWR_DET_WIDTH 1 744#define PCRF_AZ_UNSUP_REQ_DET_LBN 3 745#define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1 746#define PCRF_AZ_FATAL_ERR_DET_LBN 2 747#define PCRF_AZ_FATAL_ERR_DET_WIDTH 1 748#define PCRF_AZ_NONFATAL_ERR_DET_LBN 1 749#define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1 750#define PCRF_AZ_CORR_ERR_DET_LBN 0 751#define PCRF_AZ_CORR_ERR_DET_WIDTH 1 752 |
| 753 |
|
| 642/* 643 * PC_LNK_CAP_REG(32bit): 644 * PCIe link capabilities register 645 */ 646 647#define PCR_AB_LNK_CAP_REG 0x0000006c 648/* falcona0,falconb0=pci_f0_config */ 649 | 754/* 755 * PC_LNK_CAP_REG(32bit): 756 * PCIe link capabilities register 757 */ 758 759#define PCR_AB_LNK_CAP_REG 0x0000006c 760/* falcona0,falconb0=pci_f0_config */ 761 |
| 650#define PCR_CZ_LNK_CAP_REG 0x0000007c 651/* sienaa0,hunta0=pci_f0_config */ | 762#define PCR_CC_LNK_CAP_REG 0x0000007c 763/* sienaa0=pci_f0_config */ |
| 652 | 764 |
| 765#define PCR_DZ_LNK_CAP_REG 0x000000cc 766/* hunta0=pci_f0_config */ 767 |
|
| 653#define PCRF_AZ_PORT_NUM_LBN 24 654#define PCRF_AZ_PORT_NUM_WIDTH 8 | 768#define PCRF_AZ_PORT_NUM_LBN 24 769#define PCRF_AZ_PORT_NUM_WIDTH 8 |
| 655#define PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22 656#define PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1 | |
| 657#define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21 658#define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1 659#define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20 660#define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1 661#define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19 662#define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1 663#define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18 664#define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1 665#define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15 666#define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3 667#define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12 668#define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3 669#define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10 670#define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2 671#define PCRF_AZ_MAX_LNK_WIDTH_LBN 4 672#define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6 673#define PCRF_AZ_MAX_LNK_SP_LBN 0 674#define PCRF_AZ_MAX_LNK_SP_WIDTH 4 675 | 770#define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21 771#define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1 772#define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20 773#define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1 774#define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19 775#define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1 776#define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18 777#define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1 778#define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15 779#define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3 780#define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12 781#define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3 782#define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10 783#define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2 784#define PCRF_AZ_MAX_LNK_WIDTH_LBN 4 785#define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6 786#define PCRF_AZ_MAX_LNK_SP_LBN 0 787#define PCRF_AZ_MAX_LNK_SP_WIDTH 4 788 |
| 789 |
|
| 676/* 677 * PC_LNK_CTL_REG(16bit): 678 * PCIe link control register 679 */ 680 681#define PCR_AB_LNK_CTL_REG 0x00000070 682/* falcona0,falconb0=pci_f0_config */ 683 | 790/* 791 * PC_LNK_CTL_REG(16bit): 792 * PCIe link control register 793 */ 794 795#define PCR_AB_LNK_CTL_REG 0x00000070 796/* falcona0,falconb0=pci_f0_config */ 797 |
| 684#define PCR_CZ_LNK_CTL_REG 0x00000080 685/* sienaa0,hunta0=pci_f0_config */ | 798#define PCR_CC_LNK_CTL_REG 0x00000080 799/* sienaa0=pci_f0_config */ |
| 686 | 800 |
| 801#define PCR_DZ_LNK_CTL_REG 0x000000d0 802/* hunta0=pci_f0_config */ 803 |
|
| 687#define PCRF_AZ_EXT_SYNC_LBN 7 688#define PCRF_AZ_EXT_SYNC_WIDTH 1 689#define PCRF_AZ_COMM_CLK_CFG_LBN 6 690#define PCRF_AZ_COMM_CLK_CFG_WIDTH 1 691#define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5 692#define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1 693#define PCRF_CZ_LNK_RETRAIN_LBN 5 694#define PCRF_CZ_LNK_RETRAIN_WIDTH 1 695#define PCRF_AZ_LNK_DIS_LBN 4 696#define PCRF_AZ_LNK_DIS_WIDTH 1 697#define PCRF_AZ_RD_COM_BDRY_LBN 3 698#define PCRF_AZ_RD_COM_BDRY_WIDTH 1 699#define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0 700#define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2 701 | 804#define PCRF_AZ_EXT_SYNC_LBN 7 805#define PCRF_AZ_EXT_SYNC_WIDTH 1 806#define PCRF_AZ_COMM_CLK_CFG_LBN 6 807#define PCRF_AZ_COMM_CLK_CFG_WIDTH 1 808#define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5 809#define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1 810#define PCRF_CZ_LNK_RETRAIN_LBN 5 811#define PCRF_CZ_LNK_RETRAIN_WIDTH 1 812#define PCRF_AZ_LNK_DIS_LBN 4 813#define PCRF_AZ_LNK_DIS_WIDTH 1 814#define PCRF_AZ_RD_COM_BDRY_LBN 3 815#define PCRF_AZ_RD_COM_BDRY_WIDTH 1 816#define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0 817#define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2 818 |
| 819 |
|
| 702/* 703 * PC_LNK_STAT_REG(16bit): 704 * PCIe link status register 705 */ 706 707#define PCR_AB_LNK_STAT_REG 0x00000072 708/* falcona0,falconb0=pci_f0_config */ 709 | 820/* 821 * PC_LNK_STAT_REG(16bit): 822 * PCIe link status register 823 */ 824 825#define PCR_AB_LNK_STAT_REG 0x00000072 826/* falcona0,falconb0=pci_f0_config */ 827 |
| 710#define PCR_CZ_LNK_STAT_REG 0x00000082 711/* sienaa0,hunta0=pci_f0_config */ | 828#define PCR_CC_LNK_STAT_REG 0x00000082 829/* sienaa0=pci_f0_config */ |
| 712 | 830 |
| 831#define PCR_DZ_LNK_STAT_REG 0x000000d2 832/* hunta0=pci_f0_config */ 833 |
|
| 713#define PCRF_AZ_SLOT_CLK_CFG_LBN 12 714#define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1 715#define PCRF_AZ_LNK_TRAIN_LBN 11 716#define PCRF_AZ_LNK_TRAIN_WIDTH 1 717#define PCRF_AB_TRAIN_ERR_LBN 10 718#define PCRF_AB_TRAIN_ERR_WIDTH 1 719#define PCRF_AZ_LNK_WIDTH_LBN 4 720#define PCRF_AZ_LNK_WIDTH_WIDTH 6 721#define PCRF_AZ_LNK_SP_LBN 0 722#define PCRF_AZ_LNK_SP_WIDTH 4 723 | 834#define PCRF_AZ_SLOT_CLK_CFG_LBN 12 835#define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1 836#define PCRF_AZ_LNK_TRAIN_LBN 11 837#define PCRF_AZ_LNK_TRAIN_WIDTH 1 838#define PCRF_AB_TRAIN_ERR_LBN 10 839#define PCRF_AB_TRAIN_ERR_WIDTH 1 840#define PCRF_AZ_LNK_WIDTH_LBN 4 841#define PCRF_AZ_LNK_WIDTH_WIDTH 6 842#define PCRF_AZ_LNK_SP_LBN 0 843#define PCRF_AZ_LNK_SP_WIDTH 4 844 |
| 845 |
|
| 724/* 725 * PC_SLOT_CAP_REG(32bit): 726 * PCIe slot capabilities register 727 */ 728 729#define PCR_AB_SLOT_CAP_REG 0x00000074 730/* falcona0,falconb0=pci_f0_config */ 731 --- 13 unchanged lines hidden (view full) --- 745#define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1 746#define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2 747#define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1 748#define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1 749#define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1 750#define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0 751#define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1 752 | 846/* 847 * PC_SLOT_CAP_REG(32bit): 848 * PCIe slot capabilities register 849 */ 850 851#define PCR_AB_SLOT_CAP_REG 0x00000074 852/* falcona0,falconb0=pci_f0_config */ 853 --- 13 unchanged lines hidden (view full) --- 867#define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1 868#define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2 869#define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1 870#define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1 871#define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1 872#define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0 873#define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1 874 |
| 875 |
|
| 753/* 754 * PC_SLOT_CTL_REG(16bit): 755 * PCIe slot control register 756 */ 757 758#define PCR_AB_SLOT_CTL_REG 0x00000078 759/* falcona0,falconb0=pci_f0_config */ 760 --- 11 unchanged lines hidden (view full) --- 772#define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1 773#define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2 774#define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1 775#define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1 776#define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1 777#define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0 778#define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1 779 | 876/* 877 * PC_SLOT_CTL_REG(16bit): 878 * PCIe slot control register 879 */ 880 881#define PCR_AB_SLOT_CTL_REG 0x00000078 882/* falcona0,falconb0=pci_f0_config */ 883 --- 11 unchanged lines hidden (view full) --- 895#define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1 896#define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2 897#define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1 898#define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1 899#define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1 900#define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0 901#define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1 902 |
| 903 |
|
| 780/* 781 * PC_SLOT_STAT_REG(16bit): 782 * PCIe slot status register 783 */ 784 785#define PCR_AB_SLOT_STAT_REG 0x0000007a 786/* falcona0,falconb0=pci_f0_config */ 787 --- 7 unchanged lines hidden (view full) --- 795#define PCRF_AB_SLOT_ATTN_IND_WIDTH 1 796#define PCRF_AB_SLOT_MRL_SENS_LBN 2 797#define PCRF_AB_SLOT_MRL_SENS_WIDTH 1 798#define PCRF_AB_PWR_FLTDET_LBN 1 799#define PCRF_AB_PWR_FLTDET_WIDTH 1 800#define PCRF_AB_ATTN_BUTDET_LBN 0 801#define PCRF_AB_ATTN_BUTDET_WIDTH 1 802 | 904/* 905 * PC_SLOT_STAT_REG(16bit): 906 * PCIe slot status register 907 */ 908 909#define PCR_AB_SLOT_STAT_REG 0x0000007a 910/* falcona0,falconb0=pci_f0_config */ 911 --- 7 unchanged lines hidden (view full) --- 919#define PCRF_AB_SLOT_ATTN_IND_WIDTH 1 920#define PCRF_AB_SLOT_MRL_SENS_LBN 2 921#define PCRF_AB_SLOT_MRL_SENS_WIDTH 1 922#define PCRF_AB_PWR_FLTDET_LBN 1 923#define PCRF_AB_PWR_FLTDET_WIDTH 1 924#define PCRF_AB_ATTN_BUTDET_LBN 0 925#define PCRF_AB_ATTN_BUTDET_WIDTH 1 926 |
| 927 |
|
| 803/* 804 * PC_MSIX_CAP_ID_REG(8bit): 805 * MSIX Capability ID 806 */ 807 808#define PCR_BB_MSIX_CAP_ID_REG 0x00000090 809/* falconb0=pci_f0_config */ 810 811#define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0 812/* sienaa0,hunta0=pci_f0_config */ 813 814#define PCRF_BZ_MSIX_CAP_ID_LBN 0 815#define PCRF_BZ_MSIX_CAP_ID_WIDTH 8 816 | 928/* 929 * PC_MSIX_CAP_ID_REG(8bit): 930 * MSIX Capability ID 931 */ 932 933#define PCR_BB_MSIX_CAP_ID_REG 0x00000090 934/* falconb0=pci_f0_config */ 935 936#define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0 937/* sienaa0,hunta0=pci_f0_config */ 938 939#define PCRF_BZ_MSIX_CAP_ID_LBN 0 940#define PCRF_BZ_MSIX_CAP_ID_WIDTH 8 941 |
| 942 |
|
| 817/* 818 * PC_MSIX_NXT_PTR_REG(8bit): 819 * MSIX Capability Next Capability Ptr 820 */ 821 822#define PCR_BB_MSIX_NXT_PTR_REG 0x00000091 823/* falconb0=pci_f0_config */ 824 825#define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1 826/* sienaa0,hunta0=pci_f0_config */ 827 828#define PCRF_BZ_MSIX_NXT_PTR_LBN 0 829#define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8 830 | 943/* 944 * PC_MSIX_NXT_PTR_REG(8bit): 945 * MSIX Capability Next Capability Ptr 946 */ 947 948#define PCR_BB_MSIX_NXT_PTR_REG 0x00000091 949/* falconb0=pci_f0_config */ 950 951#define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1 952/* sienaa0,hunta0=pci_f0_config */ 953 954#define PCRF_BZ_MSIX_NXT_PTR_LBN 0 955#define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8 956 |
| 957 |
|
| 831/* 832 * PC_MSIX_CTL_REG(16bit): 833 * MSIX control register 834 */ 835 836#define PCR_BB_MSIX_CTL_REG 0x00000092 837/* falconb0=pci_f0_config */ 838 839#define PCR_CZ_MSIX_CTL_REG 0x000000b2 840/* sienaa0,hunta0=pci_f0_config */ 841 842#define PCRF_BZ_MSIX_EN_LBN 15 843#define PCRF_BZ_MSIX_EN_WIDTH 1 844#define PCRF_BZ_MSIX_FUNC_MASK_LBN 14 845#define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1 846#define PCRF_BZ_MSIX_TBL_SIZE_LBN 0 847#define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11 848 | 958/* 959 * PC_MSIX_CTL_REG(16bit): 960 * MSIX control register 961 */ 962 963#define PCR_BB_MSIX_CTL_REG 0x00000092 964/* falconb0=pci_f0_config */ 965 966#define PCR_CZ_MSIX_CTL_REG 0x000000b2 967/* sienaa0,hunta0=pci_f0_config */ 968 969#define PCRF_BZ_MSIX_EN_LBN 15 970#define PCRF_BZ_MSIX_EN_WIDTH 1 971#define PCRF_BZ_MSIX_FUNC_MASK_LBN 14 972#define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1 973#define PCRF_BZ_MSIX_TBL_SIZE_LBN 0 974#define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11 975 |
| 849/* 850 * PC_MSIX_TBL_BASE_REG(32bit): 851 * MSIX Capability Vector Table Base 852 */ | |
| 853 | 976 |
| 854#define PCR_BB_MSIX_TBL_BASE_REG 0x00000094 855/* falconb0=pci_f0_config */ 856 857#define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4 858/* sienaa0,hunta0=pci_f0_config */ 859 860#define PCRF_BZ_MSIX_TBL_OFF_LBN 3 861#define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29 862#define PCRF_BZ_MSIX_TBL_BIR_LBN 0 863#define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3 864 | |
| 865/* | 977/* |
| 866 * PC_DEV_CAP2_REG(32bit): | 978 * PC_DEV_CAP2_REG(16bit): |
| 867 * PCIe Device Capabilities 2 868 */ 869 | 979 * PCIe Device Capabilities 2 980 */ 981 |
| 870#define PCR_CZ_DEV_CAP2_REG 0x00000094 871/* sienaa0=pci_f0_config,hunta0=pci_f0_config */ | 982#define PCR_CC_DEV_CAP2_REG 0x00000094 983/* sienaa0=pci_f0_config */ |
| 872 | 984 |
| 873#define PCRF_DZ_OBFF_SUPPORTED_LBN 18 874#define PCRF_DZ_OBFF_SUPPORTED_WIDTH 2 875#define PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12 876#define PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2 877#define PCRF_DZ_LTR_M_SUPPORTED_LBN 11 878#define PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1 879#define PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4 880#define PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1 881#define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4 882#define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1 | 985#define PCR_DZ_DEV_CAP2_REG 0x000000e4 986/* hunta0=pci_f0_config */ 987 988#define PCRF_CZ_CMPL_TIMEOUT_DIS_LBN 4 989#define PCRF_CZ_CMPL_TIMEOUT_DIS_WIDTH 1 |
| 883#define PCRF_CZ_CMPL_TIMEOUT_LBN 0 884#define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4 885#define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14 886#define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13 887#define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10 888#define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9 889#define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6 890#define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5 891#define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2 892#define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1 893#define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0 894 | 990#define PCRF_CZ_CMPL_TIMEOUT_LBN 0 991#define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4 992#define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14 993#define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13 994#define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10 995#define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9 996#define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6 997#define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5 998#define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2 999#define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1 1000#define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0 1001 |
| 1002 |
|
| 895/* | 1003/* |
| 1004 * PC_MSIX_TBL_BASE_REG(32bit): 1005 * MSIX Capability Vector Table Base 1006 */ 1007 1008#define PCR_BB_MSIX_TBL_BASE_REG 0x00000094 1009/* falconb0=pci_f0_config */ 1010 1011#define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4 1012/* sienaa0,hunta0=pci_f0_config */ 1013 1014#define PCRF_BZ_MSIX_TBL_OFF_LBN 3 1015#define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29 1016#define PCRF_BZ_MSIX_TBL_BIR_LBN 0 1017#define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3 1018 1019 1020/* |
|
| 896 * PC_DEV_CTL2_REG(16bit): 897 * PCIe Device Control 2 898 */ 899 | 1021 * PC_DEV_CTL2_REG(16bit): 1022 * PCIe Device Control 2 1023 */ 1024 |
| 900#define PCR_CZ_DEV_CTL2_REG 0x00000098 901/* sienaa0,hunta0=pci_f0_config */ | 1025#define PCR_CC_DEV_CTL2_REG 0x00000098 1026/* sienaa0=pci_f0_config */ |
| 902 | 1027 |
| 903#define PCRF_DZ_OBFF_ENABLE_LBN 13 904#define PCRF_DZ_OBFF_ENABLE_WIDTH 2 905#define PCRF_DZ_LTR_ENABLE_LBN 10 906#define PCRF_DZ_LTR_ENABLE_WIDTH 1 907#define PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9 908#define PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1 909#define PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8 910#define PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1 | 1028#define PCR_DZ_DEV_CTL2_REG 0x000000e8 1029/* hunta0=pci_f0_config */ 1030 |
| 911#define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4 912#define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1 913#define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0 914#define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4 915 | 1031#define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4 1032#define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1 1033#define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0 1034#define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4 1035 |
| 1036 |
|
| 916/* 917 * PC_MSIX_PBA_BASE_REG(32bit): 918 * MSIX Capability PBA Base 919 */ 920 921#define PCR_BB_MSIX_PBA_BASE_REG 0x00000098 922/* falconb0=pci_f0_config */ 923 924#define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8 925/* sienaa0,hunta0=pci_f0_config */ 926 927#define PCRF_BZ_MSIX_PBA_OFF_LBN 3 928#define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29 929#define PCRF_BZ_MSIX_PBA_BIR_LBN 0 930#define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3 931 | 1037/* 1038 * PC_MSIX_PBA_BASE_REG(32bit): 1039 * MSIX Capability PBA Base 1040 */ 1041 1042#define PCR_BB_MSIX_PBA_BASE_REG 0x00000098 1043/* falconb0=pci_f0_config */ 1044 1045#define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8 1046/* sienaa0,hunta0=pci_f0_config */ 1047 1048#define PCRF_BZ_MSIX_PBA_OFF_LBN 3 1049#define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29 1050#define PCRF_BZ_MSIX_PBA_BIR_LBN 0 1051#define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3 1052 |
| 932/* 933 * PC_LNK_CAP2_REG(32bit): 934 * PCIe Link Capability 2 935 */ | |
| 936 | 1053 |
| 937#define PCR_DZ_LNK_CAP2_REG 0x0000009c 938/* hunta0=pci_f0_config */ 939 940#define PCRF_DZ_LNK_SPEED_SUP_LBN 1 941#define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7 942 | |
| 943/* 944 * PC_LNK_CTL2_REG(16bit): 945 * PCIe Link Control 2 946 */ 947 | 1054/* 1055 * PC_LNK_CTL2_REG(16bit): 1056 * PCIe Link Control 2 1057 */ 1058 |
| 948#define PCR_CZ_LNK_CTL2_REG 0x000000a0 949/* sienaa0,hunta0=pci_f0_config */ | 1059#define PCR_CC_LNK_CTL2_REG 0x000000a0 1060/* sienaa0=pci_f0_config */ |
| 950 | 1061 |
| 1062#define PCR_DZ_LNK_CTL2_REG 0x000000f0 1063/* hunta0=pci_f0_config */ 1064 |
|
| 951#define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12 952#define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1 953#define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11 954#define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1 955#define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10 956#define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1 957#define PCRF_CZ_TRANSMIT_MARGIN_LBN 7 958#define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3 959#define PCRF_CZ_SELECT_DEEMPH_LBN 6 960#define PCRF_CZ_SELECT_DEEMPH_WIDTH 1 961#define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5 962#define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1 963#define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4 964#define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1 965#define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0 966#define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4 | 1065#define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12 1066#define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1 1067#define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11 1068#define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1 1069#define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10 1070#define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1 1071#define PCRF_CZ_TRANSMIT_MARGIN_LBN 7 1072#define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3 1073#define PCRF_CZ_SELECT_DEEMPH_LBN 6 1074#define PCRF_CZ_SELECT_DEEMPH_WIDTH 1 1075#define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5 1076#define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1 1077#define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4 1078#define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1 1079#define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0 1080#define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4 |
| 967#define PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3 968#define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2 969#define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1 | |
| 970 | 1081 |
| 1082 |
|
| 971/* 972 * PC_LNK_STAT2_REG(16bit): 973 * PCIe Link Status 2 974 */ 975 | 1083/* 1084 * PC_LNK_STAT2_REG(16bit): 1085 * PCIe Link Status 2 1086 */ 1087 |
| 976#define PCR_CZ_LNK_STAT2_REG 0x000000a2 977/* sienaa0,hunta0=pci_f0_config */ | 1088#define PCR_CC_LNK_STAT2_REG 0x000000a2 1089/* sienaa0=pci_f0_config */ |
| 978 | 1090 |
| 1091#define PCR_DZ_LNK_STAT2_REG 0x000000f2 1092/* hunta0=pci_f0_config */ 1093 |
|
| 979#define PCRF_CZ_CURRENT_DEEMPH_LBN 0 980#define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1 981 | 1094#define PCRF_CZ_CURRENT_DEEMPH_LBN 0 1095#define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1 1096 |
| 1097 |
|
| 982/* 983 * PC_VPD_CAP_ID_REG(8bit): 984 * VPD data register 985 */ 986 987#define PCR_AB_VPD_CAP_ID_REG 0x000000b0 988/* falcona0,falconb0=pci_f0_config */ 989 990#define PCRF_AB_VPD_CAP_ID_LBN 0 991#define PCRF_AB_VPD_CAP_ID_WIDTH 8 992 | 1098/* 1099 * PC_VPD_CAP_ID_REG(8bit): 1100 * VPD data register 1101 */ 1102 1103#define PCR_AB_VPD_CAP_ID_REG 0x000000b0 1104/* falcona0,falconb0=pci_f0_config */ 1105 1106#define PCRF_AB_VPD_CAP_ID_LBN 0 1107#define PCRF_AB_VPD_CAP_ID_WIDTH 8 1108 |
| 1109 |
|
| 993/* 994 * PC_VPD_NXT_PTR_REG(8bit): 995 * VPD next item pointer 996 */ 997 998#define PCR_AB_VPD_NXT_PTR_REG 0x000000b1 999/* falcona0,falconb0=pci_f0_config */ 1000 1001#define PCRF_AB_VPD_NXT_PTR_LBN 0 1002#define PCRF_AB_VPD_NXT_PTR_WIDTH 8 1003 | 1110/* 1111 * PC_VPD_NXT_PTR_REG(8bit): 1112 * VPD next item pointer 1113 */ 1114 1115#define PCR_AB_VPD_NXT_PTR_REG 0x000000b1 1116/* falcona0,falconb0=pci_f0_config */ 1117 1118#define PCRF_AB_VPD_NXT_PTR_LBN 0 1119#define PCRF_AB_VPD_NXT_PTR_WIDTH 8 1120 |
| 1121 |
|
| 1004/* 1005 * PC_VPD_ADDR_REG(16bit): 1006 * VPD address register 1007 */ 1008 1009#define PCR_AB_VPD_ADDR_REG 0x000000b2 1010/* falcona0,falconb0=pci_f0_config */ 1011 1012#define PCRF_AB_VPD_FLAG_LBN 15 1013#define PCRF_AB_VPD_FLAG_WIDTH 1 1014#define PCRF_AB_VPD_ADDR_LBN 0 1015#define PCRF_AB_VPD_ADDR_WIDTH 15 1016 | 1122/* 1123 * PC_VPD_ADDR_REG(16bit): 1124 * VPD address register 1125 */ 1126 1127#define PCR_AB_VPD_ADDR_REG 0x000000b2 1128/* falcona0,falconb0=pci_f0_config */ 1129 1130#define PCRF_AB_VPD_FLAG_LBN 15 1131#define PCRF_AB_VPD_FLAG_WIDTH 1 1132#define PCRF_AB_VPD_ADDR_LBN 0 1133#define PCRF_AB_VPD_ADDR_WIDTH 15 1134 |
| 1017/* 1018 * PC_VPD_CAP_DATA_REG(32bit): 1019 * documentation to be written for sum_PC_VPD_CAP_DATA_REG 1020 */ | |
| 1021 | 1135 |
| 1022#define PCR_AB_VPD_CAP_DATA_REG 0x000000b4 1023/* falcona0,falconb0=pci_f0_config */ 1024 1025#define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4 1026/* sienaa0,hunta0=pci_f0_config */ 1027 1028#define PCRF_AZ_VPD_DATA_LBN 0 1029#define PCRF_AZ_VPD_DATA_WIDTH 32 1030 | |
| 1031/* | 1136/* |
| 1032 * PC_VPD_CAP_CTL_REG(8bit): 1033 * VPD control and capabilities register 1034 */ 1035 1036#define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0 1037/* sienaa0,hunta0=pci_f0_config */ 1038 1039#define PCRF_CZ_VPD_FLAG_LBN 31 1040#define PCRF_CZ_VPD_FLAG_WIDTH 1 1041#define PCRF_CZ_VPD_ADDR_LBN 16 1042#define PCRF_CZ_VPD_ADDR_WIDTH 15 1043#define PCRF_CZ_VPD_NXT_PTR_LBN 8 1044#define PCRF_CZ_VPD_NXT_PTR_WIDTH 8 1045#define PCRF_CZ_VPD_CAP_ID_LBN 0 1046#define PCRF_CZ_VPD_CAP_ID_WIDTH 8 1047 1048/* | |
| 1049 * PC_AER_CAP_HDR_REG(32bit): 1050 * AER capability header register 1051 */ 1052 1053#define PCR_AZ_AER_CAP_HDR_REG 0x00000100 1054/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1055 1056#define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20 1057#define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12 1058#define PCRF_AZ_AERCAPHDR_VER_LBN 16 1059#define PCRF_AZ_AERCAPHDR_VER_WIDTH 4 1060#define PCRF_AZ_AERCAPHDR_ID_LBN 0 1061#define PCRF_AZ_AERCAPHDR_ID_WIDTH 16 1062 | 1137 * PC_AER_CAP_HDR_REG(32bit): 1138 * AER capability header register 1139 */ 1140 1141#define PCR_AZ_AER_CAP_HDR_REG 0x00000100 1142/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1143 1144#define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20 1145#define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12 1146#define PCRF_AZ_AERCAPHDR_VER_LBN 16 1147#define PCRF_AZ_AERCAPHDR_VER_WIDTH 4 1148#define PCRF_AZ_AERCAPHDR_ID_LBN 0 1149#define PCRF_AZ_AERCAPHDR_ID_WIDTH 16 1150 |
| 1151 |
|
| 1063/* 1064 * PC_AER_UNCORR_ERR_STAT_REG(32bit): 1065 * AER Uncorrectable error status register 1066 */ 1067 1068#define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104 1069/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1070 --- 15 unchanged lines hidden (view full) --- 1086#define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1 1087#define PCRF_AZ_PSON_TLP_STAT_LBN 12 1088#define PCRF_AZ_PSON_TLP_STAT_WIDTH 1 1089#define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4 1090#define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1 1091#define PCRF_AB_TRAIN_ERR_STAT_LBN 0 1092#define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1 1093 | 1152/* 1153 * PC_AER_UNCORR_ERR_STAT_REG(32bit): 1154 * AER Uncorrectable error status register 1155 */ 1156 1157#define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104 1158/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1159 --- 15 unchanged lines hidden (view full) --- 1175#define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1 1176#define PCRF_AZ_PSON_TLP_STAT_LBN 12 1177#define PCRF_AZ_PSON_TLP_STAT_WIDTH 1 1178#define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4 1179#define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1 1180#define PCRF_AB_TRAIN_ERR_STAT_LBN 0 1181#define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1 1182 |
| 1183 |
|
| 1094/* 1095 * PC_AER_UNCORR_ERR_MASK_REG(32bit): 1096 * AER Uncorrectable error mask register 1097 */ 1098 1099#define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108 1100/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1101 | 1184/* 1185 * PC_AER_UNCORR_ERR_MASK_REG(32bit): 1186 * AER Uncorrectable error mask register 1187 */ 1188 1189#define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108 1190/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1191 |
| 1102#define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24 1103#define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1 1104#define PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22 1105#define PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1 | |
| 1106#define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20 1107#define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1 1108#define PCRF_AZ_ECRC_ERR_MASK_LBN 19 1109#define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1 1110#define PCRF_AZ_MALF_TLP_MASK_LBN 18 1111#define PCRF_AZ_MALF_TLP_MASK_WIDTH 1 1112#define PCRF_AZ_RX_OVF_MASK_LBN 17 1113#define PCRF_AZ_RX_OVF_MASK_WIDTH 1 --- 7 unchanged lines hidden (view full) --- 1121#define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1 1122#define PCRF_AZ_PSON_TLP_MASK_LBN 12 1123#define PCRF_AZ_PSON_TLP_MASK_WIDTH 1 1124#define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4 1125#define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1 1126#define PCRF_AB_TRAIN_ERR_MASK_LBN 0 1127#define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1 1128 | 1192#define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20 1193#define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1 1194#define PCRF_AZ_ECRC_ERR_MASK_LBN 19 1195#define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1 1196#define PCRF_AZ_MALF_TLP_MASK_LBN 18 1197#define PCRF_AZ_MALF_TLP_MASK_WIDTH 1 1198#define PCRF_AZ_RX_OVF_MASK_LBN 17 1199#define PCRF_AZ_RX_OVF_MASK_WIDTH 1 --- 7 unchanged lines hidden (view full) --- 1207#define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1 1208#define PCRF_AZ_PSON_TLP_MASK_LBN 12 1209#define PCRF_AZ_PSON_TLP_MASK_WIDTH 1 1210#define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4 1211#define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1 1212#define PCRF_AB_TRAIN_ERR_MASK_LBN 0 1213#define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1 1214 |
| 1215 |
|
| 1129/* 1130 * PC_AER_UNCORR_ERR_SEV_REG(32bit): 1131 * AER Uncorrectable error severity register 1132 */ 1133 1134#define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c 1135/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1136 --- 15 unchanged lines hidden (view full) --- 1152#define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1 1153#define PCRF_AZ_PSON_TLP_SEV_LBN 12 1154#define PCRF_AZ_PSON_TLP_SEV_WIDTH 1 1155#define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4 1156#define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1 1157#define PCRF_AB_TRAIN_ERR_SEV_LBN 0 1158#define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1 1159 | 1216/* 1217 * PC_AER_UNCORR_ERR_SEV_REG(32bit): 1218 * AER Uncorrectable error severity register 1219 */ 1220 1221#define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c 1222/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1223 --- 15 unchanged lines hidden (view full) --- 1239#define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1 1240#define PCRF_AZ_PSON_TLP_SEV_LBN 12 1241#define PCRF_AZ_PSON_TLP_SEV_WIDTH 1 1242#define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4 1243#define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1 1244#define PCRF_AB_TRAIN_ERR_SEV_LBN 0 1245#define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1 1246 |
| 1247 |
|
| 1160/* 1161 * PC_AER_CORR_ERR_STAT_REG(32bit): 1162 * AER Correctable error status register 1163 */ 1164 1165#define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110 1166/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1167 --- 5 unchanged lines hidden (view full) --- 1173#define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1 1174#define PCRF_AZ_BAD_DLLP_STAT_LBN 7 1175#define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1 1176#define PCRF_AZ_BAD_TLP_STAT_LBN 6 1177#define PCRF_AZ_BAD_TLP_STAT_WIDTH 1 1178#define PCRF_AZ_RX_ERR_STAT_LBN 0 1179#define PCRF_AZ_RX_ERR_STAT_WIDTH 1 1180 | 1248/* 1249 * PC_AER_CORR_ERR_STAT_REG(32bit): 1250 * AER Correctable error status register 1251 */ 1252 1253#define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110 1254/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1255 --- 5 unchanged lines hidden (view full) --- 1261#define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1 1262#define PCRF_AZ_BAD_DLLP_STAT_LBN 7 1263#define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1 1264#define PCRF_AZ_BAD_TLP_STAT_LBN 6 1265#define PCRF_AZ_BAD_TLP_STAT_WIDTH 1 1266#define PCRF_AZ_RX_ERR_STAT_LBN 0 1267#define PCRF_AZ_RX_ERR_STAT_WIDTH 1 1268 |
| 1269 |
|
| 1181/* 1182 * PC_AER_CORR_ERR_MASK_REG(32bit): 1183 * AER Correctable error status register 1184 */ 1185 1186#define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114 1187/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1188 --- 5 unchanged lines hidden (view full) --- 1194#define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1 1195#define PCRF_AZ_BAD_DLLP_MASK_LBN 7 1196#define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1 1197#define PCRF_AZ_BAD_TLP_MASK_LBN 6 1198#define PCRF_AZ_BAD_TLP_MASK_WIDTH 1 1199#define PCRF_AZ_RX_ERR_MASK_LBN 0 1200#define PCRF_AZ_RX_ERR_MASK_WIDTH 1 1201 | 1270/* 1271 * PC_AER_CORR_ERR_MASK_REG(32bit): 1272 * AER Correctable error status register 1273 */ 1274 1275#define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114 1276/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1277 --- 5 unchanged lines hidden (view full) --- 1283#define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1 1284#define PCRF_AZ_BAD_DLLP_MASK_LBN 7 1285#define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1 1286#define PCRF_AZ_BAD_TLP_MASK_LBN 6 1287#define PCRF_AZ_BAD_TLP_MASK_WIDTH 1 1288#define PCRF_AZ_RX_ERR_MASK_LBN 0 1289#define PCRF_AZ_RX_ERR_MASK_WIDTH 1 1290 |
| 1291 |
|
| 1202/* 1203 * PC_AER_CAP_CTL_REG(32bit): 1204 * AER capability and control register 1205 */ 1206 1207#define PCR_AZ_AER_CAP_CTL_REG 0x00000118 1208/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1209 1210#define PCRF_AZ_ECRC_CHK_EN_LBN 8 1211#define PCRF_AZ_ECRC_CHK_EN_WIDTH 1 1212#define PCRF_AZ_ECRC_CHK_CAP_LBN 7 1213#define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1 1214#define PCRF_AZ_ECRC_GEN_EN_LBN 6 1215#define PCRF_AZ_ECRC_GEN_EN_WIDTH 1 1216#define PCRF_AZ_ECRC_GEN_CAP_LBN 5 1217#define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1 1218#define PCRF_AZ_1ST_ERR_PTR_LBN 0 1219#define PCRF_AZ_1ST_ERR_PTR_WIDTH 5 1220 | 1292/* 1293 * PC_AER_CAP_CTL_REG(32bit): 1294 * AER capability and control register 1295 */ 1296 1297#define PCR_AZ_AER_CAP_CTL_REG 0x00000118 1298/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1299 1300#define PCRF_AZ_ECRC_CHK_EN_LBN 8 1301#define PCRF_AZ_ECRC_CHK_EN_WIDTH 1 1302#define PCRF_AZ_ECRC_CHK_CAP_LBN 7 1303#define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1 1304#define PCRF_AZ_ECRC_GEN_EN_LBN 6 1305#define PCRF_AZ_ECRC_GEN_EN_WIDTH 1 1306#define PCRF_AZ_ECRC_GEN_CAP_LBN 5 1307#define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1 1308#define PCRF_AZ_1ST_ERR_PTR_LBN 0 1309#define PCRF_AZ_1ST_ERR_PTR_WIDTH 5 1310 |
| 1311 |
|
| 1221/* 1222 * PC_AER_HDR_LOG_REG(128bit): 1223 * AER Header log register 1224 */ 1225 1226#define PCR_AZ_AER_HDR_LOG_REG 0x0000011c 1227/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1228 1229#define PCRF_AZ_HDR_LOG_LBN 0 1230#define PCRF_AZ_HDR_LOG_WIDTH 128 1231 | 1312/* 1313 * PC_AER_HDR_LOG_REG(128bit): 1314 * AER Header log register 1315 */ 1316 1317#define PCR_AZ_AER_HDR_LOG_REG 0x0000011c 1318/* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1319 1320#define PCRF_AZ_HDR_LOG_LBN 0 1321#define PCRF_AZ_HDR_LOG_WIDTH 128 1322 |
| 1323 |
|
| 1232/* 1233 * PC_DEVSN_CAP_HDR_REG(32bit): 1234 * Device serial number capability header register 1235 */ 1236 | 1324/* 1325 * PC_DEVSN_CAP_HDR_REG(32bit): 1326 * Device serial number capability header register 1327 */ 1328 |
| 1237#define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140 1238/* sienaa0,hunta0=pci_f0_config */ | 1329#define PCR_DZ_DEVSN_CAP_HDR_REG 0x00000130 1330/* hunta0=pci_f0_config */ |
| 1239 | 1331 |
| 1332#define PCR_CC_DEVSN_CAP_HDR_REG 0x00000140 1333/* sienaa0=pci_f0_config */ 1334 |
|
| 1240#define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20 1241#define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12 1242#define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16 1243#define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4 1244#define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0 1245#define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16 1246 | 1335#define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20 1336#define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12 1337#define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16 1338#define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4 1339#define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0 1340#define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16 1341 |
| 1342 |
|
| 1247/* 1248 * PC_DEVSN_DWORD0_REG(32bit): 1249 * Device serial number DWORD0 1250 */ 1251 | 1343/* 1344 * PC_DEVSN_DWORD0_REG(32bit): 1345 * Device serial number DWORD0 1346 */ 1347 |
| 1252#define PCR_CZ_DEVSN_DWORD0_REG 0x00000144 1253/* sienaa0,hunta0=pci_f0_config */ | 1348#define PCR_DZ_DEVSN_DWORD0_REG 0x00000134 1349/* hunta0=pci_f0_config */ |
| 1254 | 1350 |
| 1351#define PCR_CC_DEVSN_DWORD0_REG 0x00000144 1352/* sienaa0=pci_f0_config */ 1353 |
|
| 1255#define PCRF_CZ_DEVSN_DWORD0_LBN 0 1256#define PCRF_CZ_DEVSN_DWORD0_WIDTH 32 1257 | 1354#define PCRF_CZ_DEVSN_DWORD0_LBN 0 1355#define PCRF_CZ_DEVSN_DWORD0_WIDTH 32 1356 |
| 1357 |
|
| 1258/* 1259 * PC_DEVSN_DWORD1_REG(32bit): 1260 * Device serial number DWORD0 1261 */ 1262 | 1358/* 1359 * PC_DEVSN_DWORD1_REG(32bit): 1360 * Device serial number DWORD0 1361 */ 1362 |
| 1263#define PCR_CZ_DEVSN_DWORD1_REG 0x00000148 1264/* sienaa0,hunta0=pci_f0_config */ | 1363#define PCR_DZ_DEVSN_DWORD1_REG 0x00000138 1364/* hunta0=pci_f0_config */ |
| 1265 | 1365 |
| 1366#define PCR_CC_DEVSN_DWORD1_REG 0x00000148 1367/* sienaa0=pci_f0_config */ 1368 |
|
| 1266#define PCRF_CZ_DEVSN_DWORD1_LBN 0 1267#define PCRF_CZ_DEVSN_DWORD1_WIDTH 32 1268 | 1369#define PCRF_CZ_DEVSN_DWORD1_LBN 0 1370#define PCRF_CZ_DEVSN_DWORD1_WIDTH 32 1371 |
| 1372 |
|
| 1269/* 1270 * PC_ARI_CAP_HDR_REG(32bit): 1271 * ARI capability header register 1272 */ 1273 | 1373/* 1374 * PC_ARI_CAP_HDR_REG(32bit): 1375 * ARI capability header register 1376 */ 1377 |
| 1274#define PCR_CZ_ARI_CAP_HDR_REG 0x00000150 1275/* sienaa0,hunta0=pci_f0_config */ | 1378#define PCR_DZ_ARI_CAP_HDR_REG 0x00000140 1379/* hunta0=pci_f0_config */ |
| 1276 | 1380 |
| 1381#define PCR_CC_ARI_CAP_HDR_REG 0x00000150 1382/* sienaa0=pci_f0_config */ 1383 |
|
| 1277#define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20 1278#define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12 1279#define PCRF_CZ_ARICAPHDR_VER_LBN 16 1280#define PCRF_CZ_ARICAPHDR_VER_WIDTH 4 1281#define PCRF_CZ_ARICAPHDR_ID_LBN 0 1282#define PCRF_CZ_ARICAPHDR_ID_WIDTH 16 1283 | 1384#define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20 1385#define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12 1386#define PCRF_CZ_ARICAPHDR_VER_LBN 16 1387#define PCRF_CZ_ARICAPHDR_VER_WIDTH 4 1388#define PCRF_CZ_ARICAPHDR_ID_LBN 0 1389#define PCRF_CZ_ARICAPHDR_ID_WIDTH 16 1390 |
| 1391 |
|
| 1284/* 1285 * PC_ARI_CAP_REG(16bit): 1286 * ARI Capabilities 1287 */ 1288 | 1392/* 1393 * PC_ARI_CAP_REG(16bit): 1394 * ARI Capabilities 1395 */ 1396 |
| 1289#define PCR_CZ_ARI_CAP_REG 0x00000154 1290/* sienaa0,hunta0=pci_f0_config */ | 1397#define PCR_DZ_ARI_CAP_REG 0x00000144 1398/* hunta0=pci_f0_config */ |
| 1291 | 1399 |
| 1400#define PCR_CC_ARI_CAP_REG 0x00000154 1401/* sienaa0=pci_f0_config */ 1402 |
|
| 1292#define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8 1293#define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8 1294#define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1 1295#define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1 1296#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0 1297#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1 1298 | 1403#define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8 1404#define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8 1405#define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1 1406#define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1 1407#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0 1408#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1 1409 |
| 1410 |
|
| 1299/* 1300 * PC_ARI_CTL_REG(16bit): 1301 * ARI Control 1302 */ 1303 | 1411/* 1412 * PC_ARI_CTL_REG(16bit): 1413 * ARI Control 1414 */ 1415 |
| 1304#define PCR_CZ_ARI_CTL_REG 0x00000156 1305/* sienaa0,hunta0=pci_f0_config */ | 1416#define PCR_DZ_ARI_CTL_REG 0x00000146 1417/* hunta0=pci_f0_config */ |
| 1306 | 1418 |
| 1419#define PCR_CC_ARI_CTL_REG 0x00000156 1420/* sienaa0=pci_f0_config */ 1421 |
|
| 1307#define PCRF_CZ_ARI_FN_GRP_LBN 4 1308#define PCRF_CZ_ARI_FN_GRP_WIDTH 3 1309#define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1 1310#define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1 1311#define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0 1312#define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1 1313 | 1422#define PCRF_CZ_ARI_FN_GRP_LBN 4 1423#define PCRF_CZ_ARI_FN_GRP_WIDTH 3 1424#define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1 1425#define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1 1426#define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0 1427#define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1 1428 |
| 1314/* 1315 * PC_SEC_PCIE_CAP_REG(32bit): 1316 * Secondary PCIE Capability Register 1317 */ | |
| 1318 | 1429 |
| 1319#define PCR_DZ_SEC_PCIE_CAP_REG 0x00000160 1320/* hunta0=pci_f0_config */ 1321 1322#define PCRF_DZ_SEC_NXT_PTR_LBN 20 1323#define PCRF_DZ_SEC_NXT_PTR_WIDTH 12 1324#define PCRF_DZ_SEC_VERSION_LBN 16 1325#define PCRF_DZ_SEC_VERSION_WIDTH 4 1326#define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0 1327#define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16 1328 | |
| 1329/* 1330 * PC_SRIOV_CAP_HDR_REG(32bit): 1331 * SRIOV capability header register 1332 */ 1333 1334#define PCR_CC_SRIOV_CAP_HDR_REG 0x00000160 1335/* sienaa0=pci_f0_config */ 1336 | 1430/* 1431 * PC_SRIOV_CAP_HDR_REG(32bit): 1432 * SRIOV capability header register 1433 */ 1434 1435#define PCR_CC_SRIOV_CAP_HDR_REG 0x00000160 1436/* sienaa0=pci_f0_config */ 1437 |
| 1337#define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180 | 1438#define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000200 |
| 1338/* hunta0=pci_f0_config */ 1339 1340#define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20 1341#define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12 1342#define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16 1343#define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4 1344#define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0 1345#define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16 1346 | 1439/* hunta0=pci_f0_config */ 1440 1441#define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20 1442#define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12 1443#define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16 1444#define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4 1445#define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0 1446#define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16 1447 |
| 1448 |
|
| 1347/* 1348 * PC_SRIOV_CAP_REG(32bit): 1349 * SRIOV Capabilities 1350 */ 1351 1352#define PCR_CC_SRIOV_CAP_REG 0x00000164 1353/* sienaa0=pci_f0_config */ 1354 | 1449/* 1450 * PC_SRIOV_CAP_REG(32bit): 1451 * SRIOV Capabilities 1452 */ 1453 1454#define PCR_CC_SRIOV_CAP_REG 0x00000164 1455/* sienaa0=pci_f0_config */ 1456 |
| 1355#define PCR_DZ_SRIOV_CAP_REG 0x00000184 | 1457#define PCR_DZ_SRIOV_CAP_REG 0x00000204 |
| 1356/* hunta0=pci_f0_config */ 1357 1358#define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21 1359#define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11 | 1458/* hunta0=pci_f0_config */ 1459 1460#define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21 1461#define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11 |
| 1360#define PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1 1361#define PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1 | |
| 1362#define PCRF_CZ_VF_MIGR_CAP_LBN 0 1363#define PCRF_CZ_VF_MIGR_CAP_WIDTH 1 1364 | 1462#define PCRF_CZ_VF_MIGR_CAP_LBN 0 1463#define PCRF_CZ_VF_MIGR_CAP_WIDTH 1 1464 |
| 1365/* 1366 * PC_LINK_CONTROL3_REG(32bit): 1367 * Link Control 3. 1368 */ | |
| 1369 | 1465 |
| 1370#define PCR_DZ_LINK_CONTROL3_REG 0x00000164 1371/* hunta0=pci_f0_config */ 1372 1373#define PCRF_DZ_LINK_EQ_INT_EN_LBN 1 1374#define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1 1375#define PCRF_DZ_PERFORM_EQL_LBN 0 1376#define PCRF_DZ_PERFORM_EQL_WIDTH 1 1377 | |
| 1378/* | 1466/* |
| 1379 * PC_LANE_ERROR_STAT_REG(32bit): 1380 * Lane Error Status Register. 1381 */ 1382 1383#define PCR_DZ_LANE_ERROR_STAT_REG 0x00000168 1384/* hunta0=pci_f0_config */ 1385 1386#define PCRF_DZ_LANE_STATUS_LBN 0 1387#define PCRF_DZ_LANE_STATUS_WIDTH 8 1388 1389/* | |
| 1390 * PC_SRIOV_CTL_REG(16bit): 1391 * SRIOV Control 1392 */ 1393 1394#define PCR_CC_SRIOV_CTL_REG 0x00000168 1395/* sienaa0=pci_f0_config */ 1396 | 1467 * PC_SRIOV_CTL_REG(16bit): 1468 * SRIOV Control 1469 */ 1470 1471#define PCR_CC_SRIOV_CTL_REG 0x00000168 1472/* sienaa0=pci_f0_config */ 1473 |
| 1397#define PCR_DZ_SRIOV_CTL_REG 0x00000188 | 1474#define PCR_DZ_SRIOV_CTL_REG 0x00000208 |
| 1398/* hunta0=pci_f0_config */ 1399 1400#define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4 1401#define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1 1402#define PCRF_CZ_VF_MSE_LBN 3 1403#define PCRF_CZ_VF_MSE_WIDTH 1 1404#define PCRF_CZ_VF_MIGR_INT_EN_LBN 2 1405#define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1 1406#define PCRF_CZ_VF_MIGR_EN_LBN 1 1407#define PCRF_CZ_VF_MIGR_EN_WIDTH 1 1408#define PCRF_CZ_VF_EN_LBN 0 1409#define PCRF_CZ_VF_EN_WIDTH 1 1410 | 1475/* hunta0=pci_f0_config */ 1476 1477#define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4 1478#define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1 1479#define PCRF_CZ_VF_MSE_LBN 3 1480#define PCRF_CZ_VF_MSE_WIDTH 1 1481#define PCRF_CZ_VF_MIGR_INT_EN_LBN 2 1482#define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1 1483#define PCRF_CZ_VF_MIGR_EN_LBN 1 1484#define PCRF_CZ_VF_MIGR_EN_WIDTH 1 1485#define PCRF_CZ_VF_EN_LBN 0 1486#define PCRF_CZ_VF_EN_WIDTH 1 1487 |
| 1488 |
|
| 1411/* 1412 * PC_SRIOV_STAT_REG(16bit): 1413 * SRIOV Status 1414 */ 1415 1416#define PCR_CC_SRIOV_STAT_REG 0x0000016a 1417/* sienaa0=pci_f0_config */ 1418 | 1489/* 1490 * PC_SRIOV_STAT_REG(16bit): 1491 * SRIOV Status 1492 */ 1493 1494#define PCR_CC_SRIOV_STAT_REG 0x0000016a 1495/* sienaa0=pci_f0_config */ 1496 |
| 1419#define PCR_DZ_SRIOV_STAT_REG 0x0000018a | 1497#define PCR_DZ_SRIOV_STAT_REG 0x0000020a |
| 1420/* hunta0=pci_f0_config */ 1421 1422#define PCRF_CZ_VF_MIGR_STAT_LBN 0 1423#define PCRF_CZ_VF_MIGR_STAT_WIDTH 1 1424 | 1498/* hunta0=pci_f0_config */ 1499 1500#define PCRF_CZ_VF_MIGR_STAT_LBN 0 1501#define PCRF_CZ_VF_MIGR_STAT_WIDTH 1 1502 |
| 1425/* 1426 * PC_LANE01_EQU_CONTROL_REG(32bit): 1427 * Lanes 0,1 Equalization Control Register. 1428 */ | |
| 1429 | 1503 |
| 1430#define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c 1431/* hunta0=pci_f0_config */ 1432 1433#define PCRF_DZ_LANE1_EQ_CTRL_LBN 16 1434#define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16 1435#define PCRF_DZ_LANE0_EQ_CTRL_LBN 0 1436#define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16 1437 | |
| 1438/* 1439 * PC_SRIOV_INITIALVFS_REG(16bit): 1440 * SRIOV Initial VFs 1441 */ 1442 1443#define PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c 1444/* sienaa0=pci_f0_config */ 1445 | 1504/* 1505 * PC_SRIOV_INITIALVFS_REG(16bit): 1506 * SRIOV Initial VFs 1507 */ 1508 1509#define PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c 1510/* sienaa0=pci_f0_config */ 1511 |
| 1446#define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c | 1512#define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000020c |
| 1447/* hunta0=pci_f0_config */ 1448 1449#define PCRF_CZ_VF_INITIALVFS_LBN 0 1450#define PCRF_CZ_VF_INITIALVFS_WIDTH 16 1451 | 1513/* hunta0=pci_f0_config */ 1514 1515#define PCRF_CZ_VF_INITIALVFS_LBN 0 1516#define PCRF_CZ_VF_INITIALVFS_WIDTH 16 1517 |
| 1518 |
|
| 1452/* 1453 * PC_SRIOV_TOTALVFS_REG(10bit): 1454 * SRIOV Total VFs 1455 */ 1456 1457#define PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e 1458/* sienaa0=pci_f0_config */ 1459 | 1519/* 1520 * PC_SRIOV_TOTALVFS_REG(10bit): 1521 * SRIOV Total VFs 1522 */ 1523 1524#define PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e 1525/* sienaa0=pci_f0_config */ 1526 |
| 1460#define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e | 1527#define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000020e |
| 1461/* hunta0=pci_f0_config */ 1462 1463#define PCRF_CZ_VF_TOTALVFS_LBN 0 1464#define PCRF_CZ_VF_TOTALVFS_WIDTH 16 1465 | 1528/* hunta0=pci_f0_config */ 1529 1530#define PCRF_CZ_VF_TOTALVFS_LBN 0 1531#define PCRF_CZ_VF_TOTALVFS_WIDTH 16 1532 |
| 1533 |
|
| 1466/* 1467 * PC_SRIOV_NUMVFS_REG(16bit): 1468 * SRIOV Number of VFs 1469 */ 1470 1471#define PCR_CC_SRIOV_NUMVFS_REG 0x00000170 1472/* sienaa0=pci_f0_config */ 1473 | 1534/* 1535 * PC_SRIOV_NUMVFS_REG(16bit): 1536 * SRIOV Number of VFs 1537 */ 1538 1539#define PCR_CC_SRIOV_NUMVFS_REG 0x00000170 1540/* sienaa0=pci_f0_config */ 1541 |
| 1474#define PCR_DZ_SRIOV_NUMVFS_REG 0x00000190 | 1542#define PCR_DZ_SRIOV_NUMVFS_REG 0x00000210 |
| 1475/* hunta0=pci_f0_config */ 1476 1477#define PCRF_CZ_VF_NUMVFS_LBN 0 1478#define PCRF_CZ_VF_NUMVFS_WIDTH 16 1479 | 1543/* hunta0=pci_f0_config */ 1544 1545#define PCRF_CZ_VF_NUMVFS_LBN 0 1546#define PCRF_CZ_VF_NUMVFS_WIDTH 16 1547 |
| 1480/* 1481 * PC_LANE23_EQU_CONTROL_REG(32bit): 1482 * Lanes 2,3 Equalization Control Register. 1483 */ | |
| 1484 | 1548 |
| 1485#define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170 1486/* hunta0=pci_f0_config */ 1487 1488#define PCRF_DZ_LANE3_EQ_CTRL_LBN 16 1489#define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16 1490#define PCRF_DZ_LANE2_EQ_CTRL_LBN 0 1491#define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16 1492 | |
| 1493/* 1494 * PC_SRIOV_FN_DPND_LNK_REG(16bit): 1495 * SRIOV Function dependency link 1496 */ 1497 1498#define PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172 1499/* sienaa0=pci_f0_config */ 1500 | 1549/* 1550 * PC_SRIOV_FN_DPND_LNK_REG(16bit): 1551 * SRIOV Function dependency link 1552 */ 1553 1554#define PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172 1555/* sienaa0=pci_f0_config */ 1556 |
| 1501#define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192 | 1557#define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000212 |
| 1502/* hunta0=pci_f0_config */ 1503 1504#define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0 1505#define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8 1506 | 1558/* hunta0=pci_f0_config */ 1559 1560#define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0 1561#define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8 1562 |
| 1563 |
|
| 1507/* 1508 * PC_SRIOV_1STVF_OFFSET_REG(16bit): 1509 * SRIOV First VF Offset 1510 */ 1511 1512#define PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174 1513/* sienaa0=pci_f0_config */ 1514 | 1564/* 1565 * PC_SRIOV_1STVF_OFFSET_REG(16bit): 1566 * SRIOV First VF Offset 1567 */ 1568 1569#define PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174 1570/* sienaa0=pci_f0_config */ 1571 |
| 1515#define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194 | 1572#define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000214 |
| 1516/* hunta0=pci_f0_config */ 1517 1518#define PCRF_CZ_VF_1STVF_OFFSET_LBN 0 1519#define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16 1520 | 1573/* hunta0=pci_f0_config */ 1574 1575#define PCRF_CZ_VF_1STVF_OFFSET_LBN 0 1576#define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16 1577 |
| 1521/* 1522 * PC_LANE45_EQU_CONTROL_REG(32bit): 1523 * Lanes 4,5 Equalization Control Register. 1524 */ | |
| 1525 | 1578 |
| 1526#define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174 1527/* hunta0=pci_f0_config */ 1528 1529#define PCRF_DZ_LANE5_EQ_CTRL_LBN 16 1530#define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16 1531#define PCRF_DZ_LANE4_EQ_CTRL_LBN 0 1532#define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16 1533 | |
| 1534/* 1535 * PC_SRIOV_VFSTRIDE_REG(16bit): 1536 * SRIOV VF Stride 1537 */ 1538 1539#define PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176 1540/* sienaa0=pci_f0_config */ 1541 | 1579/* 1580 * PC_SRIOV_VFSTRIDE_REG(16bit): 1581 * SRIOV VF Stride 1582 */ 1583 1584#define PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176 1585/* sienaa0=pci_f0_config */ 1586 |
| 1542#define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196 | 1587#define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000216 |
| 1543/* hunta0=pci_f0_config */ 1544 1545#define PCRF_CZ_VF_VFSTRIDE_LBN 0 1546#define PCRF_CZ_VF_VFSTRIDE_WIDTH 16 1547 | 1588/* hunta0=pci_f0_config */ 1589 1590#define PCRF_CZ_VF_VFSTRIDE_LBN 0 1591#define PCRF_CZ_VF_VFSTRIDE_WIDTH 16 1592 |
| 1548/* 1549 * PC_LANE67_EQU_CONTROL_REG(32bit): 1550 * Lanes 6,7 Equalization Control Register. 1551 */ | |
| 1552 | 1593 |
| 1553#define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178 1554/* hunta0=pci_f0_config */ 1555 1556#define PCRF_DZ_LANE7_EQ_CTRL_LBN 16 1557#define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16 1558#define PCRF_DZ_LANE6_EQ_CTRL_LBN 0 1559#define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16 1560 | |
| 1561/* 1562 * PC_SRIOV_DEVID_REG(16bit): 1563 * SRIOV VF Device ID 1564 */ 1565 1566#define PCR_CC_SRIOV_DEVID_REG 0x0000017a 1567/* sienaa0=pci_f0_config */ 1568 | 1594/* 1595 * PC_SRIOV_DEVID_REG(16bit): 1596 * SRIOV VF Device ID 1597 */ 1598 1599#define PCR_CC_SRIOV_DEVID_REG 0x0000017a 1600/* sienaa0=pci_f0_config */ 1601 |
| 1569#define PCR_DZ_SRIOV_DEVID_REG 0x0000019a | 1602#define PCR_DZ_SRIOV_DEVID_REG 0x0000021a |
| 1570/* hunta0=pci_f0_config */ 1571 1572#define PCRF_CZ_VF_DEVID_LBN 0 1573#define PCRF_CZ_VF_DEVID_WIDTH 16 1574 | 1603/* hunta0=pci_f0_config */ 1604 1605#define PCRF_CZ_VF_DEVID_LBN 0 1606#define PCRF_CZ_VF_DEVID_WIDTH 16 1607 |
| 1608 |
|
| 1575/* 1576 * PC_SRIOV_SUP_PAGESZ_REG(16bit): 1577 * SRIOV Supported Page Sizes 1578 */ 1579 1580#define PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c 1581/* sienaa0=pci_f0_config */ 1582 | 1609/* 1610 * PC_SRIOV_SUP_PAGESZ_REG(16bit): 1611 * SRIOV Supported Page Sizes 1612 */ 1613 1614#define PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c 1615/* sienaa0=pci_f0_config */ 1616 |
| 1583#define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c | 1617#define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000021c |
| 1584/* hunta0=pci_f0_config */ 1585 1586#define PCRF_CZ_VF_SUP_PAGESZ_LBN 0 1587#define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16 1588 | 1618/* hunta0=pci_f0_config */ 1619 1620#define PCRF_CZ_VF_SUP_PAGESZ_LBN 0 1621#define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16 1622 |
| 1623 |
|
| 1589/* 1590 * PC_SRIOV_SYS_PAGESZ_REG(32bit): 1591 * SRIOV System Page Size 1592 */ 1593 1594#define PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180 1595/* sienaa0=pci_f0_config */ 1596 | 1624/* 1625 * PC_SRIOV_SYS_PAGESZ_REG(32bit): 1626 * SRIOV System Page Size 1627 */ 1628 1629#define PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180 1630/* sienaa0=pci_f0_config */ 1631 |
| 1597#define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0 | 1632#define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x00000220 |
| 1598/* hunta0=pci_f0_config */ 1599 1600#define PCRF_CZ_VF_SYS_PAGESZ_LBN 0 1601#define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16 1602 | 1633/* hunta0=pci_f0_config */ 1634 1635#define PCRF_CZ_VF_SYS_PAGESZ_LBN 0 1636#define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16 1637 |
| 1638 |
|
| 1603/* 1604 * PC_SRIOV_BAR0_REG(32bit): 1605 * SRIOV VF Bar0 1606 */ 1607 1608#define PCR_CC_SRIOV_BAR0_REG 0x00000184 1609/* sienaa0=pci_f0_config */ 1610 | 1639/* 1640 * PC_SRIOV_BAR0_REG(32bit): 1641 * SRIOV VF Bar0 1642 */ 1643 1644#define PCR_CC_SRIOV_BAR0_REG 0x00000184 1645/* sienaa0=pci_f0_config */ 1646 |
| 1611#define PCR_DZ_SRIOV_BAR0_REG 0x000001a4 | 1647#define PCR_DZ_SRIOV_BAR0_REG 0x00000224 |
| 1612/* hunta0=pci_f0_config */ 1613 1614#define PCRF_CC_VF_BAR_ADDRESS_LBN 0 1615#define PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 | 1648/* hunta0=pci_f0_config */ 1649 1650#define PCRF_CC_VF_BAR_ADDRESS_LBN 0 1651#define PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 |
| 1616#define PCRF_DZ_VF_BAR0_ADDRESS_LBN 4 1617#define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28 1618#define PCRF_DZ_VF_BAR0_PREF_LBN 3 1619#define PCRF_DZ_VF_BAR0_PREF_WIDTH 1 1620#define PCRF_DZ_VF_BAR0_TYPE_LBN 1 1621#define PCRF_DZ_VF_BAR0_TYPE_WIDTH 2 1622#define PCRF_DZ_VF_BAR0_IOM_LBN 0 1623#define PCRF_DZ_VF_BAR0_IOM_WIDTH 1 | 1652#define PCRF_DZ_VF_BAR0_ADDRESS_LBN 0 1653#define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 32 |
| 1624 | 1654 |
| 1655 |
|
| 1625/* 1626 * PC_SRIOV_BAR1_REG(32bit): 1627 * SRIOV Bar1 1628 */ 1629 1630#define PCR_CC_SRIOV_BAR1_REG 0x00000188 1631/* sienaa0=pci_f0_config */ 1632 | 1656/* 1657 * PC_SRIOV_BAR1_REG(32bit): 1658 * SRIOV Bar1 1659 */ 1660 1661#define PCR_CC_SRIOV_BAR1_REG 0x00000188 1662/* sienaa0=pci_f0_config */ 1663 |
| 1633#define PCR_DZ_SRIOV_BAR1_REG 0x000001a8 | 1664#define PCR_DZ_SRIOV_BAR1_REG 0x00000228 |
| 1634/* hunta0=pci_f0_config */ 1635 1636/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1637/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1638#define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0 1639#define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32 1640 | 1665/* hunta0=pci_f0_config */ 1666 1667/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1668/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1669#define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0 1670#define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32 1671 |
| 1672 |
|
| 1641/* 1642 * PC_SRIOV_BAR2_REG(32bit): 1643 * SRIOV Bar2 1644 */ 1645 1646#define PCR_CC_SRIOV_BAR2_REG 0x0000018c 1647/* sienaa0=pci_f0_config */ 1648 | 1673/* 1674 * PC_SRIOV_BAR2_REG(32bit): 1675 * SRIOV Bar2 1676 */ 1677 1678#define PCR_CC_SRIOV_BAR2_REG 0x0000018c 1679/* sienaa0=pci_f0_config */ 1680 |
| 1649#define PCR_DZ_SRIOV_BAR2_REG 0x000001ac | 1681#define PCR_DZ_SRIOV_BAR2_REG 0x0000022c |
| 1650/* hunta0=pci_f0_config */ 1651 1652/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1653/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ | 1682/* hunta0=pci_f0_config */ 1683 1684/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1685/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ |
| 1654#define PCRF_DZ_VF_BAR2_ADDRESS_LBN 4 1655#define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28 1656#define PCRF_DZ_VF_BAR2_PREF_LBN 3 1657#define PCRF_DZ_VF_BAR2_PREF_WIDTH 1 1658#define PCRF_DZ_VF_BAR2_TYPE_LBN 1 1659#define PCRF_DZ_VF_BAR2_TYPE_WIDTH 2 1660#define PCRF_DZ_VF_BAR2_IOM_LBN 0 1661#define PCRF_DZ_VF_BAR2_IOM_WIDTH 1 | 1686#define PCRF_DZ_VF_BAR2_ADDRESS_LBN 0 1687#define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 32 |
| 1662 | 1688 |
| 1689 |
|
| 1663/* 1664 * PC_SRIOV_BAR3_REG(32bit): 1665 * SRIOV Bar3 1666 */ 1667 1668#define PCR_CC_SRIOV_BAR3_REG 0x00000190 1669/* sienaa0=pci_f0_config */ 1670 | 1690/* 1691 * PC_SRIOV_BAR3_REG(32bit): 1692 * SRIOV Bar3 1693 */ 1694 1695#define PCR_CC_SRIOV_BAR3_REG 0x00000190 1696/* sienaa0=pci_f0_config */ 1697 |
| 1671#define PCR_DZ_SRIOV_BAR3_REG 0x000001b0 | 1698#define PCR_DZ_SRIOV_BAR3_REG 0x00000230 |
| 1672/* hunta0=pci_f0_config */ 1673 1674/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1675/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1676#define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0 1677#define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32 1678 | 1699/* hunta0=pci_f0_config */ 1700 1701/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1702/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1703#define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0 1704#define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32 1705 |
| 1706 |
|
| 1679/* 1680 * PC_SRIOV_BAR4_REG(32bit): 1681 * SRIOV Bar4 1682 */ 1683 1684#define PCR_CC_SRIOV_BAR4_REG 0x00000194 1685/* sienaa0=pci_f0_config */ 1686 | 1707/* 1708 * PC_SRIOV_BAR4_REG(32bit): 1709 * SRIOV Bar4 1710 */ 1711 1712#define PCR_CC_SRIOV_BAR4_REG 0x00000194 1713/* sienaa0=pci_f0_config */ 1714 |
| 1687#define PCR_DZ_SRIOV_BAR4_REG 0x000001b4 | 1715#define PCR_DZ_SRIOV_BAR4_REG 0x00000234 |
| 1688/* hunta0=pci_f0_config */ 1689 1690/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1691/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1692#define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0 1693#define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32 1694 | 1716/* hunta0=pci_f0_config */ 1717 1718/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1719/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1720#define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0 1721#define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32 1722 |
| 1723 |
|
| 1695/* 1696 * PC_SRIOV_BAR5_REG(32bit): 1697 * SRIOV Bar5 1698 */ 1699 1700#define PCR_CC_SRIOV_BAR5_REG 0x00000198 1701/* sienaa0=pci_f0_config */ 1702 | 1724/* 1725 * PC_SRIOV_BAR5_REG(32bit): 1726 * SRIOV Bar5 1727 */ 1728 1729#define PCR_CC_SRIOV_BAR5_REG 0x00000198 1730/* sienaa0=pci_f0_config */ 1731 |
| 1703#define PCR_DZ_SRIOV_BAR5_REG 0x000001b8 | 1732#define PCR_DZ_SRIOV_BAR5_REG 0x00000238 |
| 1704/* hunta0=pci_f0_config */ 1705 1706/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1707/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1708#define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0 1709#define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32 1710 | 1733/* hunta0=pci_f0_config */ 1734 1735/* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1736/* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1737#define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0 1738#define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32 1739 |
| 1711/* 1712 * PC_SRIOV_RSVD_REG(16bit): 1713 * Reserved register 1714 */ | |
| 1715 | 1740 |
| 1716#define PCR_DZ_SRIOV_RSVD_REG 0x00000198 1717/* hunta0=pci_f0_config */ 1718 1719#define PCRF_DZ_VF_RSVD_LBN 0 1720#define PCRF_DZ_VF_RSVD_WIDTH 16 1721 | |
| 1722/* 1723 * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit): 1724 * SRIOV VF Migration State Array Offset 1725 */ 1726 1727#define PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c 1728/* sienaa0=pci_f0_config */ 1729 | 1741/* 1742 * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit): 1743 * SRIOV VF Migration State Array Offset 1744 */ 1745 1746#define PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c 1747/* sienaa0=pci_f0_config */ 1748 |
| 1730#define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc | 1749#define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000023c |
| 1731/* hunta0=pci_f0_config */ 1732 1733#define PCRF_CZ_VF_MIGR_OFFSET_LBN 3 1734#define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29 1735#define PCRF_CZ_VF_MIGR_BIR_LBN 0 1736#define PCRF_CZ_VF_MIGR_BIR_WIDTH 3 1737 | 1750/* hunta0=pci_f0_config */ 1751 1752#define PCRF_CZ_VF_MIGR_OFFSET_LBN 3 1753#define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29 1754#define PCRF_CZ_VF_MIGR_BIR_LBN 0 1755#define PCRF_CZ_VF_MIGR_BIR_WIDTH 3 1756 |
| 1757 |
|
| 1738/* | 1758/* |
| 1759 * PC_LTR_CAP_HDR_REG(32bit): 1760 * Latency Tolerance Reporting Cap Header Reg 1761 */ 1762 1763#define PCR_DZ_LTR_CAP_HDR_REG 0x00000240 1764/* hunta0=pci_f0_config */ 1765 1766#define PCRF_DZ_LTR_NXT_PTR_LBN 20 1767#define PCRF_DZ_LTR_NXT_PTR_WIDTH 12 1768#define PCRF_DZ_LTR_VERSION_LBN 16 1769#define PCRF_DZ_LTR_VERSION_WIDTH 4 1770#define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0 1771#define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16 1772 1773 1774/* 1775 * PC_LTR_MAX_SNOOP_REG(32bit): 1776 * LTR Maximum Snoop/No Snoop Register 1777 */ 1778 1779#define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000244 1780/* hunta0=pci_f0_config */ 1781 1782#define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26 1783#define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3 1784#define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16 1785#define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10 1786#define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10 1787#define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3 1788#define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0 1789#define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10 1790 1791 1792/* |
|
| 1739 * PC_TPH_CAP_HDR_REG(32bit): 1740 * TPH Capability Header Register 1741 */ 1742 | 1793 * PC_TPH_CAP_HDR_REG(32bit): 1794 * TPH Capability Header Register 1795 */ 1796 |
| 1743#define PCR_DZ_TPH_CAP_HDR_REG 0x000001c0 | 1797#define PCR_DZ_TPH_CAP_HDR_REG 0x00000274 |
| 1744/* hunta0=pci_f0_config */ 1745 1746#define PCRF_DZ_TPH_NXT_PTR_LBN 20 1747#define PCRF_DZ_TPH_NXT_PTR_WIDTH 12 1748#define PCRF_DZ_TPH_VERSION_LBN 16 1749#define PCRF_DZ_TPH_VERSION_WIDTH 4 1750#define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0 1751#define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16 1752 | 1798/* hunta0=pci_f0_config */ 1799 1800#define PCRF_DZ_TPH_NXT_PTR_LBN 20 1801#define PCRF_DZ_TPH_NXT_PTR_WIDTH 12 1802#define PCRF_DZ_TPH_VERSION_LBN 16 1803#define PCRF_DZ_TPH_VERSION_WIDTH 4 1804#define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0 1805#define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16 1806 |
| 1807 |
|
| 1753/* 1754 * PC_TPH_REQ_CAP_REG(32bit): 1755 * TPH Requester Capability Register 1756 */ 1757 | 1808/* 1809 * PC_TPH_REQ_CAP_REG(32bit): 1810 * TPH Requester Capability Register 1811 */ 1812 |
| 1758#define PCR_DZ_TPH_REQ_CAP_REG 0x000001c4 | 1813#define PCR_DZ_TPH_REQ_CAP_REG 0x00000278 |
| 1759/* hunta0=pci_f0_config */ 1760 1761#define PCRF_DZ_ST_TBLE_SIZE_LBN 16 1762#define PCRF_DZ_ST_TBLE_SIZE_WIDTH 11 1763#define PCRF_DZ_ST_TBLE_LOC_LBN 9 1764#define PCRF_DZ_ST_TBLE_LOC_WIDTH 2 1765#define PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8 1766#define PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1 1767#define PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2 1768#define PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1 1769#define PCRF_DZ_TPH_INT_MODE_SUP_LBN 1 1770#define PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1 1771#define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0 1772#define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1 1773 | 1814/* hunta0=pci_f0_config */ 1815 1816#define PCRF_DZ_ST_TBLE_SIZE_LBN 16 1817#define PCRF_DZ_ST_TBLE_SIZE_WIDTH 11 1818#define PCRF_DZ_ST_TBLE_LOC_LBN 9 1819#define PCRF_DZ_ST_TBLE_LOC_WIDTH 2 1820#define PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8 1821#define PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1 1822#define PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2 1823#define PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1 1824#define PCRF_DZ_TPH_INT_MODE_SUP_LBN 1 1825#define PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1 1826#define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0 1827#define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1 1828 |
| 1829 |
|
| 1774/* 1775 * PC_TPH_REQ_CTL_REG(32bit): 1776 * TPH Requester Control Register 1777 */ 1778 | 1830/* 1831 * PC_TPH_REQ_CTL_REG(32bit): 1832 * TPH Requester Control Register 1833 */ 1834 |
| 1779#define PCR_DZ_TPH_REQ_CTL_REG 0x000001c8 | 1835#define PCR_DZ_TPH_REQ_CTL_REG 0x0000027c |
| 1780/* hunta0=pci_f0_config */ 1781 1782#define PCRF_DZ_TPH_REQ_ENABLE_LBN 8 1783#define PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2 1784#define PCRF_DZ_TPH_ST_MODE_LBN 0 1785#define PCRF_DZ_TPH_ST_MODE_WIDTH 3 1786 | 1836/* hunta0=pci_f0_config */ 1837 1838#define PCRF_DZ_TPH_REQ_ENABLE_LBN 8 1839#define PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2 1840#define PCRF_DZ_TPH_ST_MODE_LBN 0 1841#define PCRF_DZ_TPH_ST_MODE_WIDTH 3 1842 |
| 1843 |
|
| 1787/* | 1844/* |
| 1788 * PC_LTR_CAP_HDR_REG(32bit): 1789 * Latency Tolerance Reporting Cap Header Reg | 1845 * PC_SEC_PCIE_CAP_REG(32bit): 1846 * Secondary PCIE Capability Register |
| 1790 */ 1791 | 1847 */ 1848 |
| 1792#define PCR_DZ_LTR_CAP_HDR_REG 0x00000290 | 1849#define PCR_DZ_SEC_PCIE_CAP_REG 0x00000300 |
| 1793/* hunta0=pci_f0_config */ 1794 | 1850/* hunta0=pci_f0_config */ 1851 |
| 1795#define PCRF_DZ_LTR_NXT_PTR_LBN 20 1796#define PCRF_DZ_LTR_NXT_PTR_WIDTH 12 1797#define PCRF_DZ_LTR_VERSION_LBN 16 1798#define PCRF_DZ_LTR_VERSION_WIDTH 4 1799#define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0 1800#define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16 | 1852#define PCRF_DZ_SEC_NXT_PTR_LBN 20 1853#define PCRF_DZ_SEC_NXT_PTR_WIDTH 12 1854#define PCRF_DZ_SEC_VERSION_LBN 16 1855#define PCRF_DZ_SEC_VERSION_WIDTH 4 1856#define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0 1857#define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16 |
| 1801 | 1858 |
| 1859 |
|
| 1802/* | 1860/* |
| 1803 * PC_LTR_MAX_SNOOP_REG(32bit): 1804 * LTR Maximum Snoop/No Snoop Register | 1861 * PC_LINK_CONTROL3_REG(32bit): 1862 * Link Control 3. |
| 1805 */ 1806 | 1863 */ 1864 |
| 1807#define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294 | 1865#define PCR_DZ_LINK_CONTROL3_REG 0x00000304 |
| 1808/* hunta0=pci_f0_config */ 1809 | 1866/* hunta0=pci_f0_config */ 1867 |
| 1810#define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26 1811#define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3 1812#define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16 1813#define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10 1814#define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10 1815#define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3 1816#define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0 1817#define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10 | 1868#define PCRF_DZ_LINK_EQ_INT_EN_LBN 1 1869#define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1 1870#define PCRF_DZ_PERFORM_EQL_LBN 0 1871#define PCRF_DZ_PERFORM_EQL_WIDTH 1 |
| 1818 | 1872 |
| 1873 |
|
| 1819/* | 1874/* |
| 1875 * PC_LANE_ERROR_STAT_REG(32bit): 1876 * Lane Error Status Register. 1877 */ 1878 1879#define PCR_DZ_LANE_ERROR_STAT_REG 0x00000308 1880/* hunta0=pci_f0_config */ 1881 1882#define PCRF_DZ_LANE_STATUS_LBN 0 1883#define PCRF_DZ_LANE_STATUS_WIDTH 8 1884 1885 1886/* 1887 * PC_LANE01_EQU_CONTROL_REG(32bit): 1888 * Lanes 0,1 Equalization Control Register. 1889 */ 1890 1891#define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000030c 1892/* hunta0=pci_f0_config */ 1893 1894#define PCRF_DZ_LANE1_EQ_CTRL_LBN 16 1895#define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16 1896#define PCRF_DZ_LANE0_EQ_CTRL_LBN 0 1897#define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16 1898 1899 1900/* 1901 * PC_LANE23_EQU_CONTROL_REG(32bit): 1902 * Lanes 2,3 Equalization Control Register. 1903 */ 1904 1905#define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000310 1906/* hunta0=pci_f0_config */ 1907 1908#define PCRF_DZ_LANE3_EQ_CTRL_LBN 16 1909#define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16 1910#define PCRF_DZ_LANE2_EQ_CTRL_LBN 0 1911#define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16 1912 1913 1914/* 1915 * PC_LANE45_EQU_CONTROL_REG(32bit): 1916 * Lanes 4,5 Equalization Control Register. 1917 */ 1918 1919#define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000314 1920/* hunta0=pci_f0_config */ 1921 1922#define PCRF_DZ_LANE5_EQ_CTRL_LBN 16 1923#define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16 1924#define PCRF_DZ_LANE4_EQ_CTRL_LBN 0 1925#define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16 1926 1927 1928/* 1929 * PC_LANE67_EQU_CONTROL_REG(32bit): 1930 * Lanes 6,7 Equalization Control Register. 1931 */ 1932 1933#define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000318 1934/* hunta0=pci_f0_config */ 1935 1936#define PCRF_DZ_LANE7_EQ_CTRL_LBN 16 1937#define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16 1938#define PCRF_DZ_LANE6_EQ_CTRL_LBN 0 1939#define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16 1940 1941 1942/* |
|
| 1820 * PC_ACK_LAT_TMR_REG(32bit): 1821 * ACK latency timer & replay timer register 1822 */ 1823 1824#define PCR_AC_ACK_LAT_TMR_REG 0x00000700 1825/* falcona0,falconb0,sienaa0=pci_f0_config */ 1826 1827#define PCRF_AC_RT_LBN 16 1828#define PCRF_AC_RT_WIDTH 16 1829#define PCRF_AC_ALT_LBN 0 1830#define PCRF_AC_ALT_WIDTH 16 1831 | 1943 * PC_ACK_LAT_TMR_REG(32bit): 1944 * ACK latency timer & replay timer register 1945 */ 1946 1947#define PCR_AC_ACK_LAT_TMR_REG 0x00000700 1948/* falcona0,falconb0,sienaa0=pci_f0_config */ 1949 1950#define PCRF_AC_RT_LBN 16 1951#define PCRF_AC_RT_WIDTH 16 1952#define PCRF_AC_ALT_LBN 0 1953#define PCRF_AC_ALT_WIDTH 16 1954 |
| 1955 |
|
| 1832/* 1833 * PC_OTHER_MSG_REG(32bit): 1834 * Other message register 1835 */ 1836 1837#define PCR_AC_OTHER_MSG_REG 0x00000704 1838/* falcona0,falconb0,sienaa0=pci_f0_config */ 1839 1840#define PCRF_AC_OM_CRPT3_LBN 24 1841#define PCRF_AC_OM_CRPT3_WIDTH 8 1842#define PCRF_AC_OM_CRPT2_LBN 16 1843#define PCRF_AC_OM_CRPT2_WIDTH 8 1844#define PCRF_AC_OM_CRPT1_LBN 8 1845#define PCRF_AC_OM_CRPT1_WIDTH 8 1846#define PCRF_AC_OM_CRPT0_LBN 0 1847#define PCRF_AC_OM_CRPT0_WIDTH 8 1848 | 1956/* 1957 * PC_OTHER_MSG_REG(32bit): 1958 * Other message register 1959 */ 1960 1961#define PCR_AC_OTHER_MSG_REG 0x00000704 1962/* falcona0,falconb0,sienaa0=pci_f0_config */ 1963 1964#define PCRF_AC_OM_CRPT3_LBN 24 1965#define PCRF_AC_OM_CRPT3_WIDTH 8 1966#define PCRF_AC_OM_CRPT2_LBN 16 1967#define PCRF_AC_OM_CRPT2_WIDTH 8 1968#define PCRF_AC_OM_CRPT1_LBN 8 1969#define PCRF_AC_OM_CRPT1_WIDTH 8 1970#define PCRF_AC_OM_CRPT0_LBN 0 1971#define PCRF_AC_OM_CRPT0_WIDTH 8 1972 |
| 1973 |
|
| 1849/* 1850 * PC_FORCE_LNK_REG(24bit): 1851 * Port force link register 1852 */ 1853 1854#define PCR_AC_FORCE_LNK_REG 0x00000708 1855/* falcona0,falconb0,sienaa0=pci_f0_config */ 1856 1857#define PCRF_AC_LFS_LBN 16 1858#define PCRF_AC_LFS_WIDTH 6 1859#define PCRF_AC_FL_LBN 15 1860#define PCRF_AC_FL_WIDTH 1 1861#define PCRF_AC_LN_LBN 0 1862#define PCRF_AC_LN_WIDTH 8 1863 | 1974/* 1975 * PC_FORCE_LNK_REG(24bit): 1976 * Port force link register 1977 */ 1978 1979#define PCR_AC_FORCE_LNK_REG 0x00000708 1980/* falcona0,falconb0,sienaa0=pci_f0_config */ 1981 1982#define PCRF_AC_LFS_LBN 16 1983#define PCRF_AC_LFS_WIDTH 6 1984#define PCRF_AC_FL_LBN 15 1985#define PCRF_AC_FL_WIDTH 1 1986#define PCRF_AC_LN_LBN 0 1987#define PCRF_AC_LN_WIDTH 8 1988 |
| 1989 |
|
| 1864/* 1865 * PC_ACK_FREQ_REG(32bit): 1866 * ACK frequency register 1867 */ 1868 1869#define PCR_AC_ACK_FREQ_REG 0x0000070c 1870/* falcona0,falconb0,sienaa0=pci_f0_config */ 1871 --- 7 unchanged lines hidden (view full) --- 1879#define PCRF_CC_COMM_NFTS_WIDTH 8 1880#define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16 1881#define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3 1882#define PCRF_AC_MAX_FTS_LBN 8 1883#define PCRF_AC_MAX_FTS_WIDTH 8 1884#define PCRF_AC_ACK_FREQ_LBN 0 1885#define PCRF_AC_ACK_FREQ_WIDTH 8 1886 | 1990/* 1991 * PC_ACK_FREQ_REG(32bit): 1992 * ACK frequency register 1993 */ 1994 1995#define PCR_AC_ACK_FREQ_REG 0x0000070c 1996/* falcona0,falconb0,sienaa0=pci_f0_config */ 1997 --- 7 unchanged lines hidden (view full) --- 2005#define PCRF_CC_COMM_NFTS_WIDTH 8 2006#define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16 2007#define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3 2008#define PCRF_AC_MAX_FTS_LBN 8 2009#define PCRF_AC_MAX_FTS_WIDTH 8 2010#define PCRF_AC_ACK_FREQ_LBN 0 2011#define PCRF_AC_ACK_FREQ_WIDTH 8 2012 |
| 2013 |
|
| 1887/* 1888 * PC_PORT_LNK_CTL_REG(32bit): 1889 * Port link control register 1890 */ 1891 1892#define PCR_AC_PORT_LNK_CTL_REG 0x00000710 1893/* falcona0,falconb0,sienaa0=pci_f0_config */ 1894 --- 21 unchanged lines hidden (view full) --- 1916#define PCRF_AC_RA_WIDTH 1 1917#define PCRF_AC_LE_LBN 2 1918#define PCRF_AC_LE_WIDTH 1 1919#define PCRF_AC_SD_LBN 1 1920#define PCRF_AC_SD_WIDTH 1 1921#define PCRF_AC_OMR_LBN 0 1922#define PCRF_AC_OMR_WIDTH 1 1923 | 2014/* 2015 * PC_PORT_LNK_CTL_REG(32bit): 2016 * Port link control register 2017 */ 2018 2019#define PCR_AC_PORT_LNK_CTL_REG 0x00000710 2020/* falcona0,falconb0,sienaa0=pci_f0_config */ 2021 --- 21 unchanged lines hidden (view full) --- 2043#define PCRF_AC_RA_WIDTH 1 2044#define PCRF_AC_LE_LBN 2 2045#define PCRF_AC_LE_WIDTH 1 2046#define PCRF_AC_SD_LBN 1 2047#define PCRF_AC_SD_WIDTH 1 2048#define PCRF_AC_OMR_LBN 0 2049#define PCRF_AC_OMR_WIDTH 1 2050 |
| 2051 |
|
| 1924/* 1925 * PC_LN_SKEW_REG(32bit): 1926 * Lane skew register 1927 */ 1928 1929#define PCR_AC_LN_SKEW_REG 0x00000714 1930/* falcona0,falconb0,sienaa0=pci_f0_config */ 1931 --- 7 unchanged lines hidden (view full) --- 1939#define PCRF_AC_FCD_WIDTH 1 1940#define PCRF_AC_LS2_LBN 16 1941#define PCRF_AC_LS2_WIDTH 8 1942#define PCRF_AC_LS1_LBN 8 1943#define PCRF_AC_LS1_WIDTH 8 1944#define PCRF_AC_LS0_LBN 0 1945#define PCRF_AC_LS0_WIDTH 8 1946 | 2052/* 2053 * PC_LN_SKEW_REG(32bit): 2054 * Lane skew register 2055 */ 2056 2057#define PCR_AC_LN_SKEW_REG 0x00000714 2058/* falcona0,falconb0,sienaa0=pci_f0_config */ 2059 --- 7 unchanged lines hidden (view full) --- 2067#define PCRF_AC_FCD_WIDTH 1 2068#define PCRF_AC_LS2_LBN 16 2069#define PCRF_AC_LS2_WIDTH 8 2070#define PCRF_AC_LS1_LBN 8 2071#define PCRF_AC_LS1_WIDTH 8 2072#define PCRF_AC_LS0_LBN 0 2073#define PCRF_AC_LS0_WIDTH 8 2074 |
| 2075 |
|
| 1947/* 1948 * PC_SYM_NUM_REG(16bit): 1949 * Symbol number register 1950 */ 1951 1952#define PCR_AC_SYM_NUM_REG 0x00000718 1953/* falcona0,falconb0,sienaa0=pci_f0_config */ 1954 --- 11 unchanged lines hidden (view full) --- 1966#define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1 1967#define PCRF_CC_NUM_SKP_SYMS_LBN 8 1968#define PCRF_CC_NUM_SKP_SYMS_WIDTH 3 1969#define PCRF_AB_TS2_LBN 4 1970#define PCRF_AB_TS2_WIDTH 4 1971#define PCRF_AC_TS1_LBN 0 1972#define PCRF_AC_TS1_WIDTH 4 1973 | 2076/* 2077 * PC_SYM_NUM_REG(16bit): 2078 * Symbol number register 2079 */ 2080 2081#define PCR_AC_SYM_NUM_REG 0x00000718 2082/* falcona0,falconb0,sienaa0=pci_f0_config */ 2083 --- 11 unchanged lines hidden (view full) --- 2095#define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1 2096#define PCRF_CC_NUM_SKP_SYMS_LBN 8 2097#define PCRF_CC_NUM_SKP_SYMS_WIDTH 3 2098#define PCRF_AB_TS2_LBN 4 2099#define PCRF_AB_TS2_WIDTH 4 2100#define PCRF_AC_TS1_LBN 0 2101#define PCRF_AC_TS1_WIDTH 4 2102 |
| 2103 |
|
| 1974/* 1975 * PC_SYM_TMR_FLT_MSK_REG(16bit): 1976 * Symbol timer and Filter Mask Register 1977 */ 1978 1979#define PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c 1980/* sienaa0=pci_f0_config */ 1981 1982#define PCRF_CC_DEFAULT_FLT_MSK1_LBN 16 1983#define PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16 1984#define PCRF_CC_FC_WDOG_TMR_DIS_LBN 15 1985#define PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1 1986#define PCRF_CC_SI1_LBN 8 1987#define PCRF_CC_SI1_WIDTH 3 1988#define PCRF_CC_SKIP_INT_VAL_LBN 0 1989#define PCRF_CC_SKIP_INT_VAL_WIDTH 11 1990#define PCRF_CC_SI0_LBN 0 1991#define PCRF_CC_SI0_WIDTH 8 1992 | 2104/* 2105 * PC_SYM_TMR_FLT_MSK_REG(16bit): 2106 * Symbol timer and Filter Mask Register 2107 */ 2108 2109#define PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c 2110/* sienaa0=pci_f0_config */ 2111 2112#define PCRF_CC_DEFAULT_FLT_MSK1_LBN 16 2113#define PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16 2114#define PCRF_CC_FC_WDOG_TMR_DIS_LBN 15 2115#define PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1 2116#define PCRF_CC_SI1_LBN 8 2117#define PCRF_CC_SI1_WIDTH 3 2118#define PCRF_CC_SKIP_INT_VAL_LBN 0 2119#define PCRF_CC_SKIP_INT_VAL_WIDTH 11 2120#define PCRF_CC_SI0_LBN 0 2121#define PCRF_CC_SI0_WIDTH 8 2122 |
| 2123 |
|
| 1993/* 1994 * PC_SYM_TMR_REG(16bit): 1995 * Symbol timer register 1996 */ 1997 1998#define PCR_AB_SYM_TMR_REG 0x0000071c 1999/* falcona0,falconb0=pci_f0_config */ 2000 2001#define PCRF_AB_ET_LBN 11 2002#define PCRF_AB_ET_WIDTH 4 2003#define PCRF_AB_SI1_LBN 8 2004#define PCRF_AB_SI1_WIDTH 3 2005#define PCRF_AB_SI0_LBN 0 2006#define PCRF_AB_SI0_WIDTH 8 2007 | 2124/* 2125 * PC_SYM_TMR_REG(16bit): 2126 * Symbol timer register 2127 */ 2128 2129#define PCR_AB_SYM_TMR_REG 0x0000071c 2130/* falcona0,falconb0=pci_f0_config */ 2131 2132#define PCRF_AB_ET_LBN 11 2133#define PCRF_AB_ET_WIDTH 4 2134#define PCRF_AB_SI1_LBN 8 2135#define PCRF_AB_SI1_WIDTH 3 2136#define PCRF_AB_SI0_LBN 0 2137#define PCRF_AB_SI0_WIDTH 8 2138 |
| 2008/* 2009 * PC_FLT_MSK_REG(32bit): 2010 * Filter Mask Register 2 2011 */ | |
| 2012 | 2139 |
| 2013#define PCR_CC_FLT_MSK_REG 0x00000720 2014/* sienaa0=pci_f0_config */ 2015 2016#define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0 2017#define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32 2018 | |
| 2019/* 2020 * PC_PHY_STAT_REG(32bit): 2021 * PHY status register 2022 */ 2023 2024#define PCR_AB_PHY_STAT_REG 0x00000720 2025/* falcona0,falconb0=pci_f0_config */ 2026 --- 4 unchanged lines hidden (view full) --- 2031#define PCRF_AC_SSL_WIDTH 1 2032#define PCRF_AC_SSR_LBN 2 2033#define PCRF_AC_SSR_WIDTH 1 2034#define PCRF_AC_SSCL_LBN 1 2035#define PCRF_AC_SSCL_WIDTH 1 2036#define PCRF_AC_SSCD_LBN 0 2037#define PCRF_AC_SSCD_WIDTH 1 2038 | 2140/* 2141 * PC_PHY_STAT_REG(32bit): 2142 * PHY status register 2143 */ 2144 2145#define PCR_AB_PHY_STAT_REG 0x00000720 2146/* falcona0,falconb0=pci_f0_config */ 2147 --- 4 unchanged lines hidden (view full) --- 2152#define PCRF_AC_SSL_WIDTH 1 2153#define PCRF_AC_SSR_LBN 2 2154#define PCRF_AC_SSR_WIDTH 1 2155#define PCRF_AC_SSCL_LBN 1 2156#define PCRF_AC_SSCL_WIDTH 1 2157#define PCRF_AC_SSCD_LBN 0 2158#define PCRF_AC_SSCD_WIDTH 1 2159 |
| 2160 |
|
| 2039/* | 2161/* |
| 2162 * PC_FLT_MSK_REG(32bit): 2163 * Filter Mask Register 2 2164 */ 2165 2166#define PCR_CC_FLT_MSK_REG 0x00000720 2167/* sienaa0=pci_f0_config */ 2168 2169#define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0 2170#define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32 2171 2172 2173/* |
|
| 2040 * PC_PHY_CTL_REG(32bit): 2041 * PHY control register 2042 */ 2043 2044#define PCR_AB_PHY_CTL_REG 0x00000724 2045/* falcona0,falconb0=pci_f0_config */ 2046 2047#define PCR_CC_PHY_CTL_REG 0x00000814 --- 11 unchanged lines hidden (view full) --- 2059#define PCRF_AC_SNR_WIDTH 1 2060#define PCRF_AC_RX_NOT_DET_LBN 2 2061#define PCRF_AC_RX_NOT_DET_WIDTH 1 2062#define PCRF_AC_FORCE_LOS_VAL_LBN 1 2063#define PCRF_AC_FORCE_LOS_VAL_WIDTH 1 2064#define PCRF_AC_FORCE_LOS_EN_LBN 0 2065#define PCRF_AC_FORCE_LOS_EN_WIDTH 1 2066 | 2174 * PC_PHY_CTL_REG(32bit): 2175 * PHY control register 2176 */ 2177 2178#define PCR_AB_PHY_CTL_REG 0x00000724 2179/* falcona0,falconb0=pci_f0_config */ 2180 2181#define PCR_CC_PHY_CTL_REG 0x00000814 --- 11 unchanged lines hidden (view full) --- 2193#define PCRF_AC_SNR_WIDTH 1 2194#define PCRF_AC_RX_NOT_DET_LBN 2 2195#define PCRF_AC_RX_NOT_DET_WIDTH 1 2196#define PCRF_AC_FORCE_LOS_VAL_LBN 1 2197#define PCRF_AC_FORCE_LOS_VAL_WIDTH 1 2198#define PCRF_AC_FORCE_LOS_EN_LBN 0 2199#define PCRF_AC_FORCE_LOS_EN_WIDTH 1 2200 |
| 2201 |
|
| 2067/* 2068 * PC_DEBUG0_REG(32bit): 2069 * Debug register 0 2070 */ 2071 2072#define PCR_AC_DEBUG0_REG 0x00000728 2073/* falcona0,falconb0,sienaa0=pci_f0_config */ 2074 2075#define PCRF_AC_CDI03_LBN 24 2076#define PCRF_AC_CDI03_WIDTH 8 2077#define PCRF_AC_CDI0_LBN 0 2078#define PCRF_AC_CDI0_WIDTH 32 2079#define PCRF_AC_CDI02_LBN 16 2080#define PCRF_AC_CDI02_WIDTH 8 2081#define PCRF_AC_CDI01_LBN 8 2082#define PCRF_AC_CDI01_WIDTH 8 2083#define PCRF_AC_CDI00_LBN 0 2084#define PCRF_AC_CDI00_WIDTH 8 2085 | 2202/* 2203 * PC_DEBUG0_REG(32bit): 2204 * Debug register 0 2205 */ 2206 2207#define PCR_AC_DEBUG0_REG 0x00000728 2208/* falcona0,falconb0,sienaa0=pci_f0_config */ 2209 2210#define PCRF_AC_CDI03_LBN 24 2211#define PCRF_AC_CDI03_WIDTH 8 2212#define PCRF_AC_CDI0_LBN 0 2213#define PCRF_AC_CDI0_WIDTH 32 2214#define PCRF_AC_CDI02_LBN 16 2215#define PCRF_AC_CDI02_WIDTH 8 2216#define PCRF_AC_CDI01_LBN 8 2217#define PCRF_AC_CDI01_WIDTH 8 2218#define PCRF_AC_CDI00_LBN 0 2219#define PCRF_AC_CDI00_WIDTH 8 2220 |
| 2221 |
|
| 2086/* 2087 * PC_DEBUG1_REG(32bit): 2088 * Debug register 1 2089 */ 2090 2091#define PCR_AC_DEBUG1_REG 0x0000072c 2092/* falcona0,falconb0,sienaa0=pci_f0_config */ 2093 2094#define PCRF_AC_CDI13_LBN 24 2095#define PCRF_AC_CDI13_WIDTH 8 2096#define PCRF_AC_CDI1_LBN 0 2097#define PCRF_AC_CDI1_WIDTH 32 2098#define PCRF_AC_CDI12_LBN 16 2099#define PCRF_AC_CDI12_WIDTH 8 2100#define PCRF_AC_CDI11_LBN 8 2101#define PCRF_AC_CDI11_WIDTH 8 2102#define PCRF_AC_CDI10_LBN 0 2103#define PCRF_AC_CDI10_WIDTH 8 2104 | 2222/* 2223 * PC_DEBUG1_REG(32bit): 2224 * Debug register 1 2225 */ 2226 2227#define PCR_AC_DEBUG1_REG 0x0000072c 2228/* falcona0,falconb0,sienaa0=pci_f0_config */ 2229 2230#define PCRF_AC_CDI13_LBN 24 2231#define PCRF_AC_CDI13_WIDTH 8 2232#define PCRF_AC_CDI1_LBN 0 2233#define PCRF_AC_CDI1_WIDTH 32 2234#define PCRF_AC_CDI12_LBN 16 2235#define PCRF_AC_CDI12_WIDTH 8 2236#define PCRF_AC_CDI11_LBN 8 2237#define PCRF_AC_CDI11_WIDTH 8 2238#define PCRF_AC_CDI10_LBN 0 2239#define PCRF_AC_CDI10_WIDTH 8 2240 |
| 2241 |
|
| 2105/* 2106 * PC_XPFCC_STAT_REG(24bit): 2107 * documentation to be written for sum_PC_XPFCC_STAT_REG 2108 */ 2109 2110#define PCR_AC_XPFCC_STAT_REG 0x00000730 2111/* falcona0,falconb0,sienaa0=pci_f0_config */ 2112 2113#define PCRF_AC_XPDC_LBN 12 2114#define PCRF_AC_XPDC_WIDTH 8 2115#define PCRF_AC_XPHC_LBN 0 2116#define PCRF_AC_XPHC_WIDTH 12 2117 | 2242/* 2243 * PC_XPFCC_STAT_REG(24bit): 2244 * documentation to be written for sum_PC_XPFCC_STAT_REG 2245 */ 2246 2247#define PCR_AC_XPFCC_STAT_REG 0x00000730 2248/* falcona0,falconb0,sienaa0=pci_f0_config */ 2249 2250#define PCRF_AC_XPDC_LBN 12 2251#define PCRF_AC_XPDC_WIDTH 8 2252#define PCRF_AC_XPHC_LBN 0 2253#define PCRF_AC_XPHC_WIDTH 12 2254 |
| 2255 |
|
| 2118/* 2119 * PC_XNPFCC_STAT_REG(24bit): 2120 * documentation to be written for sum_PC_XNPFCC_STAT_REG 2121 */ 2122 2123#define PCR_AC_XNPFCC_STAT_REG 0x00000734 2124/* falcona0,falconb0,sienaa0=pci_f0_config */ 2125 2126#define PCRF_AC_XNPDC_LBN 12 2127#define PCRF_AC_XNPDC_WIDTH 8 2128#define PCRF_AC_XNPHC_LBN 0 2129#define PCRF_AC_XNPHC_WIDTH 12 2130 | 2256/* 2257 * PC_XNPFCC_STAT_REG(24bit): 2258 * documentation to be written for sum_PC_XNPFCC_STAT_REG 2259 */ 2260 2261#define PCR_AC_XNPFCC_STAT_REG 0x00000734 2262/* falcona0,falconb0,sienaa0=pci_f0_config */ 2263 2264#define PCRF_AC_XNPDC_LBN 12 2265#define PCRF_AC_XNPDC_WIDTH 8 2266#define PCRF_AC_XNPHC_LBN 0 2267#define PCRF_AC_XNPHC_WIDTH 12 2268 |
| 2269 |
|
| 2131/* 2132 * PC_XCFCC_STAT_REG(24bit): 2133 * documentation to be written for sum_PC_XCFCC_STAT_REG 2134 */ 2135 2136#define PCR_AC_XCFCC_STAT_REG 0x00000738 2137/* falcona0,falconb0,sienaa0=pci_f0_config */ 2138 2139#define PCRF_AC_XCDC_LBN 12 2140#define PCRF_AC_XCDC_WIDTH 8 2141#define PCRF_AC_XCHC_LBN 0 2142#define PCRF_AC_XCHC_WIDTH 12 2143 | 2270/* 2271 * PC_XCFCC_STAT_REG(24bit): 2272 * documentation to be written for sum_PC_XCFCC_STAT_REG 2273 */ 2274 2275#define PCR_AC_XCFCC_STAT_REG 0x00000738 2276/* falcona0,falconb0,sienaa0=pci_f0_config */ 2277 2278#define PCRF_AC_XCDC_LBN 12 2279#define PCRF_AC_XCDC_WIDTH 8 2280#define PCRF_AC_XCHC_LBN 0 2281#define PCRF_AC_XCHC_WIDTH 12 2282 |
| 2283 |
|
| 2144/* 2145 * PC_Q_STAT_REG(8bit): 2146 * documentation to be written for sum_PC_Q_STAT_REG 2147 */ 2148 2149#define PCR_AC_Q_STAT_REG 0x0000073c 2150/* falcona0,falconb0,sienaa0=pci_f0_config */ 2151 2152#define PCRF_AC_RQNE_LBN 2 2153#define PCRF_AC_RQNE_WIDTH 1 2154#define PCRF_AC_XRNE_LBN 1 2155#define PCRF_AC_XRNE_WIDTH 1 2156#define PCRF_AC_RCNR_LBN 0 2157#define PCRF_AC_RCNR_WIDTH 1 2158 | 2284/* 2285 * PC_Q_STAT_REG(8bit): 2286 * documentation to be written for sum_PC_Q_STAT_REG 2287 */ 2288 2289#define PCR_AC_Q_STAT_REG 0x0000073c 2290/* falcona0,falconb0,sienaa0=pci_f0_config */ 2291 2292#define PCRF_AC_RQNE_LBN 2 2293#define PCRF_AC_RQNE_WIDTH 1 2294#define PCRF_AC_XRNE_LBN 1 2295#define PCRF_AC_XRNE_WIDTH 1 2296#define PCRF_AC_RCNR_LBN 0 2297#define PCRF_AC_RCNR_WIDTH 1 2298 |
| 2299 |
|
| 2159/* 2160 * PC_VC_XMIT_ARB1_REG(32bit): 2161 * VC Transmit Arbitration Register 1 2162 */ 2163 2164#define PCR_CC_VC_XMIT_ARB1_REG 0x00000740 2165/* sienaa0=pci_f0_config */ 2166 | 2300/* 2301 * PC_VC_XMIT_ARB1_REG(32bit): 2302 * VC Transmit Arbitration Register 1 2303 */ 2304 2305#define PCR_CC_VC_XMIT_ARB1_REG 0x00000740 2306/* sienaa0=pci_f0_config */ 2307 |
| 2308 2309 |
|
| 2167/* 2168 * PC_VC_XMIT_ARB2_REG(32bit): 2169 * VC Transmit Arbitration Register 2 2170 */ 2171 2172#define PCR_CC_VC_XMIT_ARB2_REG 0x00000744 2173/* sienaa0=pci_f0_config */ 2174 | 2310/* 2311 * PC_VC_XMIT_ARB2_REG(32bit): 2312 * VC Transmit Arbitration Register 2 2313 */ 2314 2315#define PCR_CC_VC_XMIT_ARB2_REG 0x00000744 2316/* sienaa0=pci_f0_config */ 2317 |
| 2318 2319 |
|
| 2175/* 2176 * PC_VC0_P_RQ_CTL_REG(32bit): 2177 * VC0 Posted Receive Queue Control 2178 */ 2179 2180#define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748 2181/* sienaa0=pci_f0_config */ 2182 | 2320/* 2321 * PC_VC0_P_RQ_CTL_REG(32bit): 2322 * VC0 Posted Receive Queue Control 2323 */ 2324 2325#define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748 2326/* sienaa0=pci_f0_config */ 2327 |
| 2328 2329 |
|
| 2183/* 2184 * PC_VC0_NP_RQ_CTL_REG(32bit): 2185 * VC0 Non-Posted Receive Queue Control 2186 */ 2187 2188#define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c 2189/* sienaa0=pci_f0_config */ 2190 | 2330/* 2331 * PC_VC0_NP_RQ_CTL_REG(32bit): 2332 * VC0 Non-Posted Receive Queue Control 2333 */ 2334 2335#define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c 2336/* sienaa0=pci_f0_config */ 2337 |
| 2338 2339 |
|
| 2191/* 2192 * PC_VC0_C_RQ_CTL_REG(32bit): 2193 * VC0 Completion Receive Queue Control 2194 */ 2195 2196#define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750 2197/* sienaa0=pci_f0_config */ 2198 | 2340/* 2341 * PC_VC0_C_RQ_CTL_REG(32bit): 2342 * VC0 Completion Receive Queue Control 2343 */ 2344 2345#define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750 2346/* sienaa0=pci_f0_config */ 2347 |
| 2348 2349 |
|
| 2199/* 2200 * PC_GEN2_REG(32bit): 2201 * Gen2 Register 2202 */ 2203 2204#define PCR_CC_GEN2_REG 0x0000080c 2205/* sienaa0=pci_f0_config */ 2206 --- 5 unchanged lines hidden (view full) --- 2212#define PCRF_CC_CFG_TX_SWING_WIDTH 1 2213#define PCRF_CC_DIR_SPEED_CHANGE_LBN 17 2214#define PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1 2215#define PCRF_CC_LANE_ENABLE_LBN 8 2216#define PCRF_CC_LANE_ENABLE_WIDTH 9 2217#define PCRF_CC_NUM_FTS_LBN 0 2218#define PCRF_CC_NUM_FTS_WIDTH 8 2219 | 2350/* 2351 * PC_GEN2_REG(32bit): 2352 * Gen2 Register 2353 */ 2354 2355#define PCR_CC_GEN2_REG 0x0000080c 2356/* sienaa0=pci_f0_config */ 2357 --- 5 unchanged lines hidden (view full) --- 2363#define PCRF_CC_CFG_TX_SWING_WIDTH 1 2364#define PCRF_CC_DIR_SPEED_CHANGE_LBN 17 2365#define PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1 2366#define PCRF_CC_LANE_ENABLE_LBN 8 2367#define PCRF_CC_LANE_ENABLE_WIDTH 9 2368#define PCRF_CC_NUM_FTS_LBN 0 2369#define PCRF_CC_NUM_FTS_WIDTH 8 2370 |
| 2371 |
|
| 2220#ifdef __cplusplus 2221} 2222#endif 2223 2224#endif /* _SYS_EFX_REGS_PCI_H */ | 2372#ifdef __cplusplus 2373} 2374#endif 2375 2376#endif /* _SYS_EFX_REGS_PCI_H */ |