nxge_txdma.c (75d94465) nxge_txdma.c (e3d11eee)
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

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1118 * Registers accessed:
1119 * TX_CS DMC+0x40028 Transmit Control And Status
1120 * PIO_LDSV
1121 *
1122 * Context:
1123 * Any domain
1124 */
1125uint_t
1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE

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1118 * Registers accessed:
1119 * TX_CS DMC+0x40028 Transmit Control And Status
1120 * PIO_LDSV
1121 *
1122 * Context:
1123 * Any domain
1124 */
1125uint_t
1126nxge_tx_intr(void *arg1, void *arg2)
1126nxge_tx_intr(char *arg1, char *arg2)
1127{
1128 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1;
1129 p_nxge_t nxgep = (p_nxge_t)arg2;
1130 p_nxge_ldg_t ldgp;
1131 uint8_t channel;
1132 uint32_t vindex;
1133 npi_handle_t handle;
1134 tx_cs_t cs;

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1329
1330 if (nxgep->tx_rings == 0 || nxgep->tx_rings->rings == 0) {
1331 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1332 "<== nxge_txdma_hw_mode: NULL ring pointer(s)"));
1333 return (NXGE_ERROR);
1334 }
1335
1336 /* Enable or disable all of the TDCs owned by us. */
1127{
1128 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1;
1129 p_nxge_t nxgep = (p_nxge_t)arg2;
1130 p_nxge_ldg_t ldgp;
1131 uint8_t channel;
1132 uint32_t vindex;
1133 npi_handle_t handle;
1134 tx_cs_t cs;

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1329
1330 if (nxgep->tx_rings == 0 || nxgep->tx_rings->rings == 0) {
1331 NXGE_DEBUG_MSG((nxgep, TX_CTL,
1332 "<== nxge_txdma_hw_mode: NULL ring pointer(s)"));
1333 return (NXGE_ERROR);
1334 }
1335
1336 /* Enable or disable all of the TDCs owned by us. */
1337 rs = 0;
1337 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1338 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) {
1339 if ((1 << tdc) & set->owned.map) {
1340 tx_ring_t *ring = nxgep->tx_rings->rings[tdc];
1341 if (ring) {
1342 NXGE_DEBUG_MSG((nxgep, MEM3_CTL,
1343 "==> nxge_txdma_hw_mode: channel %d", tdc));
1344 if (enable) {

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2528nxge_map_txdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel,
2529 p_nxge_dma_common_t *dma_buf_p,
2530 p_tx_ring_t *tx_desc_p, uint32_t num_chunks)
2531{
2532 p_nxge_dma_common_t dma_bufp, tmp_bufp;
2533 p_nxge_dma_common_t dmap;
2534 nxge_os_dma_handle_t tx_buf_dma_handle;
2535 p_tx_ring_t tx_ring_p;
1338 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1339 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) {
1340 if ((1 << tdc) & set->owned.map) {
1341 tx_ring_t *ring = nxgep->tx_rings->rings[tdc];
1342 if (ring) {
1343 NXGE_DEBUG_MSG((nxgep, MEM3_CTL,
1344 "==> nxge_txdma_hw_mode: channel %d", tdc));
1345 if (enable) {

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2529nxge_map_txdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel,
2530 p_nxge_dma_common_t *dma_buf_p,
2531 p_tx_ring_t *tx_desc_p, uint32_t num_chunks)
2532{
2533 p_nxge_dma_common_t dma_bufp, tmp_bufp;
2534 p_nxge_dma_common_t dmap;
2535 nxge_os_dma_handle_t tx_buf_dma_handle;
2536 p_tx_ring_t tx_ring_p;
2536 p_tx_msg_t tx_msg_ring;
2537 p_tx_msg_t tx_msg_ring = NULL;
2537 nxge_status_t status = NXGE_OK;
2538 int ddi_status = DDI_SUCCESS;
2538 nxge_status_t status = NXGE_OK;
2539 int ddi_status = DDI_SUCCESS;
2539 int i, j, index;
2540 uint32_t size, bsize;
2540 int i, j, index = 0;
2541 uint32_t size = 0, bsize;
2541 uint32_t nblocks, nmsgs;
2542 char qname[TASKQ_NAMELEN];
2543
2544 NXGE_DEBUG_MSG((nxgep, MEM3_CTL,
2545 "==> nxge_map_txdma_channel_buf_ring"));
2546
2547 dma_bufp = tmp_bufp = *dma_buf_p;
2548 NXGE_DEBUG_MSG((nxgep, MEM3_CTL,

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3332 * Reset the tail (kick) register to 0.
3333 * (Hardware will not reset it. Tx overflow fatal
3334 * error if tail is not set to 0 after reset!
3335 */
3336 TXDMA_REG_WRITE64(handle, TX_RING_KICK_REG, channel, 0);
3337
3338 /* Restart TXDMA channel */
3339
2542 uint32_t nblocks, nmsgs;
2543 char qname[TASKQ_NAMELEN];
2544
2545 NXGE_DEBUG_MSG((nxgep, MEM3_CTL,
2546 "==> nxge_map_txdma_channel_buf_ring"));
2547
2548 dma_bufp = tmp_bufp = *dma_buf_p;
2549 NXGE_DEBUG_MSG((nxgep, MEM3_CTL,

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3333 * Reset the tail (kick) register to 0.
3334 * (Hardware will not reset it. Tx overflow fatal
3335 * error if tail is not set to 0 after reset!
3336 */
3337 TXDMA_REG_WRITE64(handle, TX_RING_KICK_REG, channel, 0);
3338
3339 /* Restart TXDMA channel */
3340
3341 tx_mbox_p = NULL;
3340 if (!isLDOMguest(nxgep)) {
3341 tx_mbox_p = nxge_txdma_get_mbox(nxgep, channel);
3342
3343 // XXX This is a problem in HIO!
3344 /*
3345 * Initialize the TXDMA channel specific FZC control
3346 * configurations. These FZC registers are pertaining
3347 * to each TX channel (i.e. logical pages).

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3419{
3420 nxge_grp_set_t *set = &nxgep->tx_set;
3421 nxge_channel_t tdc;
3422
3423 tx_ring_t *ring;
3424 tx_mbox_t *mailbox;
3425
3426 npi_handle_t handle;
3342 if (!isLDOMguest(nxgep)) {
3343 tx_mbox_p = nxge_txdma_get_mbox(nxgep, channel);
3344
3345 // XXX This is a problem in HIO!
3346 /*
3347 * Initialize the TXDMA channel specific FZC control
3348 * configurations. These FZC registers are pertaining
3349 * to each TX channel (i.e. logical pages).

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3421{
3422 nxge_grp_set_t *set = &nxgep->tx_set;
3423 nxge_channel_t tdc;
3424
3425 tx_ring_t *ring;
3426 tx_mbox_t *mailbox;
3427
3428 npi_handle_t handle;
3427 nxge_status_t status;
3429 nxge_status_t status = NXGE_OK;
3428 npi_status_t rs;
3429
3430 NXGE_DEBUG_MSG((nxgep, TX_CTL, "<== nxge_tx_port_fatal_err_recover"));
3431 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3432 "Recovering from TxPort error..."));
3433
3434 if (isLDOMguest(nxgep)) {
3435 return (NXGE_OK);

--- 251 unchanged lines hidden --- 		3430 npi_status_t rs;
3431
3432 NXGE_DEBUG_MSG((nxgep, TX_CTL, "<== nxge_tx_port_fatal_err_recover"));
3433 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3434 "Recovering from TxPort error..."));
3435
3436 if (isLDOMguest(nxgep)) {
3437 return (NXGE_OK);

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